| Entries |
| Document | Title | Date |
|---|
| 20080224115 | Fabricating a Set of Semiconducting Nanowires, and Electric Device Comprising a Set of Nanowires - The method of fabricating a set of semiconducting nanowires ( | 09-18-2008 |
| 20080251777 | Field Effect Device with a Channel with a Switchable Conductivity - A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material that is reversibly switchable between a lower conductivity state and a higher conductivity state. The first conductivity state has an electrical conductivity which is lower than an electrical conductivity of the second conductivity state. Each of the conductivity states is persistent without the need for a sustaining excitation signal including an electrical field, heat and/or light applied to the device. | 10-16-2008 |
| 20080315170 | Quantum coherent switch utilizing commensurate nanoelectrode and charge density periodicities - A quantum coherent switch having a substrate formed from a density wave (DW) material capable of having a periodic electron density modulation or spin density modulation, a dielectric layer formed onto a surface of the substrate that is orthogonal to an intrinsic wave vector of the DW material; and structure for applying an external spatially periodic electrostatic potential over the dielectric layer. | 12-25-2008 |
| 20090283735 | CARBON NANO-FILM REVERSIBLE RESISTANCE-SWITCHABLE ELEMENTS AND METHODS OF FORMING THE SAME - Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided. | 11-19-2009 |
| 20100193757 | TWO-TERMINAL RESISTANCE SWITCHING DEVICE AND SEMICONDUCTOR DEVICE - The present invention is contemplated for providing a resistance switching device having a very small device size of approximately 20 nm×20 nm in its entirety, by taking advantage of a small diameter of a multilayered carbon nanotube or a multilayered carbon nanofiber per se, via a simpler manner that does not require any molecule inclusion step, with an excellent electric conductivity. | 08-05-2010 |
| 20100301299 | Material and device properties modification by electrochemical charge injection in the absence of contacting electrolyte for either local spatial or final states - In some embodiments, the present invention is directed to processes for the combination of injecting charge in a material electrochemically via non-faradaic (double-layer) charging, and retaining this charge and associated desirable properties changes when the electrolyte is removed. The present invention is also directed to compositions and applications using material property changes that are induced electrochemically by double-layer charging and retained during subsequent electrolyte removal. In some embodiments, the present invention provides reversible processes for electrochemically injecting charge into material that is not in direct contact with an electrolyte. Additionally, in some embodiments, the present invention is directed to devices and other material applications that use properties changes resulting from reversible electrochemical charge injection in the absence of an electrolyte. | 12-02-2010 |
| 20110024710 | MEMRISTOR WITH A NON-PLANAR SUBSTRATE - A memristor includes a substrate having a plurality of protrusions, wherein each of the plurality of protrusions extends in a first direction, a first electrode provided over at least one of the plurality of protrusions, wherein the first electrode conforms to the shape of the at least one protrusion such that the first electrode has a crest, a switching material positioned upon the first electrode; and a second electrode positioned upon the switching material such that a portion of the second electrode is substantially in line with the crest of the first electrode along the first direction, wherein an active region in the switching material is operable to be formed between the crest of the first electrode and the portion of the second electrode that is substantially in line with the crest of the first electrode. | 02-03-2011 |
| 20110024711 | APPARATUS FOR REDUCING PHOTODIODE THERMAL GAIN COEFFICIENT AND METHOD OF MAKING SAME - An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer. | 02-03-2011 |
| 20110084247 | Self-Aligned Bipolar Junction Transistors - A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips. | 04-14-2011 |
| 20110133147 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 06-09-2011 |
| 20110193042 | MEMORY CELL FORMED USING A RECESS AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided. | 08-11-2011 |
| 20110210300 | Reducing Temporal Changes in Phase Change Memories - A phase change memory in the reset state may be heated to reduce or eliminate electrical drift. | 09-01-2011 |
| 20110220858 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same. The semiconductor device may include a lower electrode having a hollow cylindrical shape of which an upper portion is open, the lower electrode being disposed on a substrate, an insulating structure wrapping the lower electrode and including a nitride, a variable resistance pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the variable resistance pattern. | 09-15-2011 |
| 20110220859 | Two-Terminal Nanotube Devices And Systems And Methods Of Making Same - A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. | 09-15-2011 |
| 20110240941 | Silicon-Based Memristive Device - A memristive device ( | 10-06-2011 |
| 20110248233 | METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL - A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer. | 10-13-2011 |
| 20110248234 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 10-13-2011 |
| 20110278527 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect. | 11-17-2011 |
| 20110297908 | Phase Change Memory Cells and Fabrication Thereof - A phase change memory cell, e.g. a line-cell ( | 12-08-2011 |
| 20110297909 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY - A magnetic memory element includes: a first magnetization free layer formed of a ferromagnetic material having perpendicular magnetic anisotropy; a second magnetization free layer provided near the first magnetization free layer and formed of a ferromagnetic material having in-plane magnetic anisotropy; a reference layer formed of a ferromagnetic material having in-plane magnetic anisotropy; and a non-magnetic layer provided between the second magnetization free layer and the reference layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region which is connected to the first magnetization fixed region and the second magnetization fixed region, and of which magnetization can be switched. The second magnetization free layer is included in the first magnetization free layer in a plane parallel to a substrate. The second magnetization free layer is provided in a first direction away from the magnetization free region in the plane. | 12-08-2011 |
| 20110303887 | MEMORY STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells. | 12-15-2011 |
| 20110315942 | SOLID-STATE MEMORY - A solid-state memory that requires a lower current during recording and erasing data and can repeatedly rewrite data an increased number of times. In at least one example embodiment, the solid-state memory includes a recording layer that includes a laminated structure in which electric properties are changed in response to a phase separation. The laminated structure includes a film containing an Sb atom(s) and a film containing a Ge atom(s), which films constitute a superlattice structure. In the laminated structure, phase separation of the film containing the Sb atom and the film containing the Ge atom allows data to be recorded and erased efficiently. | 12-29-2011 |
| 20120007031 | PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR - A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure. | 01-12-2012 |
| 20120037871 | NOVEL BIFUNCTIONAL MOLECULES COMPRISING A CYCLOALKYNE OR HETEROCYCLOALKYNE GROUP AND A REDOX GROUP - The invention relates to compounds comprising a cycloalkyne or heterocycloalkyne group and a redox group. Said compounds are of general formula (I) wherein Z is a cycloalkyne or heterocycloalkyne with at least 8 links, optionally substituted by a halogen atom or a linear or branched C1 to C5 alkyl, A is an organic structure having oxidation-reduction properties, and B is an organic link between the cycloalkyne or heterocycloalkyne cycle and the organic structure A. The invention is especially applicable to the field of molecular electronics. | 02-16-2012 |
| 20120061637 | 3-D STRUCTURED NONVOLATILE MEMORY ARRAY AND METHOD FOR FABRICATING THE SAME - The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced. | 03-15-2012 |
| 20120061638 | MEMORY ELEMENT AND MEMORY DEVICE - There are provided a memory element and a memory device in which the state of erasing remains stable by deactivation of a localized site(s) formed inside of a resistance change layer. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer including an n-type dopant or a p-type dopant, and disposed on the first electrode side, and an ion source layer disposed between the resistance change layer and the second electrode. | 03-15-2012 |
| 20120068136 | Phase Change Memory Device, Storage System Having the Same and Fabricating Method Thereof - Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other. | 03-22-2012 |
| 20120132879 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements. | 05-31-2012 |
| 20120168704 | METHOD OF ETCHING A PROGRAMMABLE MEMORY MICROELECTRONIC DEVICE - A method of etching a programmable memory microelectronic device ( | 07-05-2012 |
| 20120175580 | VARIABLE RESISTANCE MEMORY - A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode. | 07-12-2012 |
| 20120205605 | ORGANIC REDOX ACTIVE COMPOUNDS WITH REVERSIBLE STORAGE OF CHARGES AND SUBSTRATES AND MOLECULAR MEMORY DEVICES COMPRISING THEM - An organic redox active compound with reversible storage of charge is disclosed. The material characterized by a formula R-M-Y-T. According to some aspects, R represents a deconjugating group, M represents an organic redox active fragment, not comprising any metal ion or metal, capable of reversibly storing at least one charge, T represents a tripod group comprising three groups F, capable of being chemically grafted to a surface of a solid substrate, and Y represents a spacer group separating M from T. A substrate on which the compounds are grafted, a molecular memory device including the compound or the substrate, and an electronic apparatus including the molecular memory device are also disclosed. | 08-16-2012 |
| 20120211715 | SEMICONDUCTOR DEVICE INCLUDING PHASE CHANGE MATERIAL AND METHOD OF MANUFACTURING SAME - Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film. | 08-23-2012 |
| 20120228573 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 09-13-2012 |
| 20120241704 | LATERAL PHASE CHANGE MEMORY - A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region. | 09-27-2012 |
| 20120280195 | RESISTANCE VARIABLE MEMORY CELLS AND METHODS - Resistance variable memory cells and methods are described herein. One or more methods of forming a resistance variable memory cell include forming a silicide material on a terminal of a select device associated with the resistance variable memory cell, forming a modified region of the silicide material by modifying a resistivity of a region of the silicide material, forming a conductive element on at least a portion of the modified region, and forming a resistance variable material on the conductive element. | 11-08-2012 |
| 20120280196 | ELECTROFORMING FREE MEMRISTOR - An electroforming free memristor ( | 11-08-2012 |
| 20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 11-08-2012 |
| 20120298945 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device of the present invention includes a substrate ( | 11-29-2012 |
| 20120298946 | Shaping a Phase Change Layer in a Phase Change Memory Cell - A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer. | 11-29-2012 |
| 20120305872 | PHASE-CHANGE MEMORY DEVICE INCLUDING A VERTICALLY-STACKED CAPACITOR AND A METHOD OF THE SAME - A phase change memory device includes a vertically-stacked capacitor structure having large capacitance and small area. The phase change memory device includes a phase change memory structure, and the vertically-stacked capacitor structure electrically connected to the phase change memory structure and comprising a first capacitor and a second capacitor that are stacked and electrically connected in parallel to each other. | 12-06-2012 |
| 20120305873 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 12-06-2012 |
| 20120326109 | PHASE CHANGE MEMORY CELL AND PHASE CHAGE MEMORY - A phase change memory cell includes a first circuit and a second circuit. The first circuit comprises a first electrode, a carbon nanotube layer and a second electrode electrically connected in series. The first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit comprises a third electrode, a phase change layer and a fourth electrode electrically connected in series, at least part of the phase change layer is overlapped with the carbon nanotube layer. The second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell. | 12-27-2012 |
| 20120326110 | PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern. | 12-27-2012 |
| 20130001494 | Memory Cell - A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage. | 01-03-2013 |
| 20130026434 | MEMRISTOR WITH CONTROLLED ELECTRODE GRAIN SIZE - A memristor with a controlled electrode grain size includes an adhesion layer, a first electrode having a first surface contacting the adhesion layer and a second surface opposite the first surface, in which the first electrode is formed of an alloy of a base material and at least one second material, and in which the alloy has a relatively smaller grain size than a grain size of the base material. The memristor also includes a switching layer positioned adjacent to the second surface of the first electrode and a second electrode positioned adjacent to the switching layer. | 01-31-2013 |
| 20130032775 | MRAM with sidewall protection and method of fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. | 02-07-2013 |
| 20130126812 | Memory Cells, Integrated Devices, and Methods of Forming Memory Cells - Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. | 05-23-2013 |
| 20130134371 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 05-30-2013 |
| 20130134372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers. | 05-30-2013 |
| 20130168628 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device includes a first trench extending in a first direction formed in a first insulation layer, a first conductive layer in the first trench, a protective layer over the first conductive layer in the first trench, a second insulation layer over the first insulation layer and the protective layer, a second trench formed in the second insulation layer and extending in a second direction that crosses the first direction, a gap formed in the protective layer exposing the first conductive layer at an intersection between the first trench and the second trench, a variable resistance layer positioned in the gap and coupled to the first conductive layer, and a second conductive layer formed in the second trench and coupled to the variable resistance layer. | 07-04-2013 |
| 20130175490 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure. | 07-11-2013 |
| 20130175491 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region. | 07-11-2013 |
| 20130181180 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element. | 07-18-2013 |
| 20130200320 | Self-Isolated Conductive Bridge Memory Device - A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator. | 08-08-2013 |
| 20130214230 | MEMORY STRUCTURES, MEMORY ARRAYS, METHODS OF FORMING MEMORY STRUCTURES AND METHODS OF FORMING MEMORY ARRAYS - Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays. | 08-22-2013 |
| 20130221306 | VARIABLE RESISTIVE MEMORY DEVICE - A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug. | 08-29-2013 |
| 20130234086 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment comprises a semiconductor layer, a variable resistance layer, a sidewall layer, and a buried layer. The semiconductor layer functions as a rectifying device. The variable resistance layer is provided above or below the semiconductor layer and reversibly changes its resistance. The sidewall layer is in contact with a sidewall of the semiconductor layer. The buried layer is embedded in the sidewall layer and is made of material different from that of the sidewall layer. These configurations may adjust the electrical characteristics of the rectifying device to any value. | 09-12-2013 |
| 20130234087 | NON-VOLATILE RESISTANCE CHANGE DEVICE - A non-volatile resistance change device includes a first electrode made of a metallic element, a second electrode, a variable resistance layer formed between the first electrode and the second electrode, first wiring formed on the first electrode on a side opposite to the variable resistance layer, and second wiring formed on the second electrode on a side opposite to the variable resistance layer. If the width of the first wiring is represented as A (nm), the width of the second wiring represented as B (nm), and the distance between the first electrode and the second electrode represented as L | 09-12-2013 |
| 20130234088 | Semiconductor device - According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material. | 09-12-2013 |
| 20130248795 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a first function layer. The first function layer includes a first electrode layer, a second electrode layer, and a variable resistance layer. The second electrode layer is opposed to the first electrode layer. The variable resistance layer is provided between the first electrode layer and the second electrode layer. Resistance state of the variable resistance layer is variable. The first function layer includes a first intermediate layer. The first intermediate layer is provided between the first electrode layer and the variable resistance layer. The first intermediate layer contacts the first electrode layer and the variable resistance layer. | 09-26-2013 |
| 20130248796 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer. | 09-26-2013 |
| 20130277635 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 10-24-2013 |
| 20130299763 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent. | 11-14-2013 |
| 20130320283 | Memory Arrays And Methods Of Forming An Array Of Memory Cells - A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed. | 12-05-2013 |
| 20130328005 | THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY DEVICES, METHODS OF OPERATING THE SAME, AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar. | 12-12-2013 |
| 20140014888 | Thermally-Confined Spacer PCM Cells - A memory device includes an array of contacts and a patterned insulating layer over the array of contacts. The patterned insulating layer includes a trench. The trench includes a sidewall aligned over a plurality of contacts in the array. A plurality of bottom electrodes on a lower portion of the sidewall contacts respective top surfaces of the contacts in the plurality of contacts. A thermally confined spacer of memory material between the patterned insulating layer and an insulating fill material is formed on an upper portion of the sidewall in contact with the plurality of bottom electrodes. | 01-16-2014 |
| 20140014889 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers. | 01-16-2014 |
| 20140021426 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic device comprises a memory cell comprising a magnetic resistance device and lower and upper electrodes with the magnetic resistance device interposed therebetween to apply current to the magnetic resistance device. The magnetic resistance device includes: a buffer layer for controlling a crystalline axis for inducing perpendicular magnetic anisotropy (PMA) in the magnetic resistance device, the buffer layer being in contact with the lower electrode; a seed layer being in contact with the buffer layer and being oriented to a hexagonal close-packed lattice (HCP) (0001) crystal plane; and a perpendicularly magnetized pinned layer being in contact with the seed layer and having an L1 | 01-23-2014 |
| 20140021427 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect. | 01-23-2014 |
| 20140027697 | MAGNETIC RANDOM ACCESS MEMORY WITH SWITCHING ASSIST LAYER - A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer. | 01-30-2014 |
| 20140097395 | RESISTIVE MEMORY DEVICE FABRICATED FROM SINGLE POLYMER MATERIAL - A polymer-based device comprising a substrate; a first electrode disposed on the substrate; an active polymer layer disposed on and in contact with the first electrode; and a second electrode disposed on and in contact with the active polymer layer, wherein the first and the second electrodes are organic electrodes comprising a doped electroconductive organic polymer, the active polymer layer comprises the electroconductive organic polymer of the first and the second electrodes, and the first and the second electrodes have conductivity at least three orders of magnitude higher than the conductivity of the active polymer layer. | 04-10-2014 |
| 20140151620 | SELF-ALIGNED WIRE FOR SPINTRONIC DEVICE - A method for fabricating a spintronic cell includes forming a cavity in a substrate, forming a wire in the cavity, depositing a spacer layer over exposed portions of the substrate and the conductive field line, depositing a layer of conductive material on a portion of the spacer layer, removing portions of the layer of conductive material to define a conductive strap portion, wherein the conductive strap portion has a first distal region a second distal region and a medial region arranged therebetween, wherein the medial region has a cross sectional area that is less than a cross sectional area of the first distal region and a cross sectional area of the second distal region, and forming an spintronic device stack on the conductive strap portion above the conductive field line. | 06-05-2014 |
| 20140158963 | EMBEDDED NON-VOLATILE MEMORY - The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F | 06-12-2014 |
| 20140166956 | Using saturated and unsaturated ALD processes to deposit oxides as ReRAM switching layer - A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer. | 06-19-2014 |
| 20140166957 | HYBRID CIRCUIT OF NITRIDE-BASED TRANSISTOR AND MEMRISTOR - A hybrid circuit comprises a nitride-based transistor portion and a memristor portion. The transistor includes a source and a drain and a gate for controlling conductance of a channel region between the source and the drain. The memristor includes a first electrode and a second electrode separated by an active switching region. The source or drain of the transistor forms one of the electrodes of the memristor. | 06-19-2014 |
| 20140166958 | Controlling ReRam Forming Voltage with Doping - An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode. | 06-19-2014 |
| 20140284533 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode. | 09-25-2014 |
| 20140284534 | MAGNETORESISTIVE ELEMENT AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a first magnetic layer having a variable magnetization direction. A first nonmagnetic layer is provided on the first magnetic layer. A second magnetic layer having a fixed magnetization direction is provided on the first nonmagnetic layer. The first magnetic layer, the first nonmagnetic layer and the second magnetic layer are preferredly oriented in a cubical crystal (111) plane. | 09-25-2014 |
| 20160380195 | Method of forming controllably conductive oxide - In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer. | 12-29-2016 |
