| Entries |
| Document | Title | Date |
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| 20080197335 | Semiconductor device and fabrications thereof - A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure. | 08-21-2008 |
| 20080197336 | Nonvolatile memory devices and methods of forming the same - A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. | 08-21-2008 |
| 20080197337 | PHASE-CHANGE TaN RESISTOR BASED TRIPLE-STATE/MULTI-STATE READ ONLY MEMORY - The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application. | 08-21-2008 |
| 20080210923 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device including a heater electrode formed in a contact hole formed in an interlayer insulation film to expose a lower electrode, the heater electrode includes at least three heater electrode layers which are successively laminated and successively increased in specific resistivity in a direction from the lower electrode towards a phase change film in this order. The interlayer insulation film is formed on a semiconductor substrate to cover the lower electrode. The phase change film is formed in contact with an upper surface of the heater electrode. An upper electrode is formed on an upper surface of the phase change film. | 09-04-2008 |
| 20080210924 | Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same - A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode. | 09-04-2008 |
| 20080217600 | MULTI-LEVEL DATA MEMORISATION DEVICE WITH PHASE CHANGE MATERIAL - The invention relates to a data memorisation device ( | 09-11-2008 |
| 20080224117 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance. | 09-18-2008 |
| 20080224118 | HEAT-SHIELDED LOW POWER PCM-BASED REPROGRAMMABLE EFUSE DEVICE - An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes. | 09-18-2008 |
| 20080224119 | PHASE CHANGE MEMORY ELEMENT AND METHOD OF MAKING THE SAME - Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer. | 09-18-2008 |
| 20080230762 | PHASE CHANGE MEMORY ELEMENTS HAVING A CONFINED PORTION OF PHASE CHANGE MATERIAL ON A RECESSED CONTACT - Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided. | 09-25-2008 |
| 20080237565 | PHASE CHANGE MEMORY DEVICE TO PREVENT THERMAL CROSS-TALK AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including the lower electrodes having holes for exposing the respective lower electrodes. Heaters are formed on the surfaces of the respective holes to contact the lower electrodes. A second insulation layer is formed to fill the holes in which the heaters are formed. A mask pattern is then formed on the first and second insulation layers, including the heaters, to have openings that expose portions of the respective heaters having a constant pitch. A phase change layer is formed on the mask pattern including the exposed portions of the heaters and the first and second insulation layers and subsequently, upper electrodes are formed on the phase change layer. | 10-02-2008 |
| 20080237566 | Phase change memory device and method of fabricating the same - A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane | 10-02-2008 |
| 20080237567 | OPTIMIZED SOLID ELECTROLYTE FOR PROGRAMMABLE METALLIZATION CELL DEVICES AND STRUCTURES - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 10-02-2008 |
| 20080246014 | Memory Structure with Reduced-Size Memory Element Between Memory Material Portions - A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer. | 10-09-2008 |
| 20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
| 20080251778 | FOUR-TERMINAL PROGRAMMABLE VIA-CONTAINING STRUCTURE AND METHOD OF FABRICATING SAME - A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure. | 10-16-2008 |
| 20080258126 | Memory Cell Sidewall Contacting Side Electrode - A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element. | 10-23-2008 |
| 20080258127 | Precursor, thin layer prepared including the precursor, method of preparing the thin layer and phase-change memory device - A Te precursor containing Te, a 15-group compound (for example, N) and/or a 14-group compound (for example, Si), a method of preparing the Te precursor, a Te-containing chalcogenide thin layer including the Te precursor, a method of preparing the thin layer; and a phase-change memory device. The Te precursor may be deposited at lower temperatures for forming a Te-containing chalcogenide thin layer doped with a 15-group compound (for example, N) and/or a 14-group compound (for example, Si). For example, the Te precursor may employ plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD) at lower deposition temperatures. The GST phase-change layer doped with a 15-group compound (for example, N) and/or a 14-group compound (for example, Si) formed by employing the Te precursor may have a decreased reset current, and thus when a memory device including the same is employed, its integration may be possible, and operation with higher capacity and/or higher speed may be possible. | 10-23-2008 |
| 20080258128 | PHASE-CHANGEABLE MEMORY DEVICES - A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed. | 10-23-2008 |
| 20080265239 | INTEGRATED CIRCUIT INCLUDING SPACER MATERIAL LAYER - An integrated circuit includes a first electrode and a dielectric material layer contacting a first portion of the first electrode. The integrated circuit includes a spacer material layer contacting a sidewall portion of the dielectric material layer and a second portion of the first electrode. The second portion is within the first portion. The integrated circuit includes resistivity changing material contacting the spacer material layer and a third portion of the first electrode. The third portion is within the second portion. The integrated circuit includes a second electrode contacting the resistivity changing material. | 10-30-2008 |
| 20080265240 | Memory device with improved performance - The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less. | 10-30-2008 |
| 20080272358 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer. | 11-06-2008 |
| 20080272359 | PHASE CHANGEABLE MEMORY CELLS - A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells. | 11-06-2008 |
| 20080272360 | PROGRAMMABLE METALLIZATION CELL STRUCTURES INCLUDING AN OXIDE ELECTROLYTE, DEVICES INCLUDING THE STRUCTURE AND METHOD OF FORMING SAME - A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an oxide ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 11-06-2008 |
| 20080277641 | Inverted variable resistance memory cell and method of making the same - An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer deposited over a semiconductor substrate, etching the top portion of the opening to have a substantially hemispherical-shape, forming a metal layer in the opening, and overlying a variable resistance material over the metal layer. | 11-13-2008 |
| 20080277642 | Fabrication of Phase-Change Resistor Using a Backend Process - A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure ( | 11-13-2008 |
| 20080277643 | PHASE CHANGE MEMORY DEVICE USING PNP-BJT FOR PREVENTING CHANGE IN PHASE CHANGE LAYER COMPOSITION AND WIDENING BIT LINE SENSING MARGIN - A phase change memory device includes a semiconductor substrate having bar-shaped active regions which extend in a first direction; base regions and emitter regions alternately formed in each active region; lower electrodes formed over the emitter regions to connect to the respective emitter regions; a phase change layer and an upper electrode stacked on each of the lower electrodes; sub bit lines formed over the upper electrodes to come into contact with the corresponding upper electrodes; word lines arranged over the sub bit lines to come into contact with the base regions; and a main bit line formed over the word line to come into contact with the sub bit lines. The phase change memory device is able to prevent a change in the composition of the phase change layer and additionally is able to widen the sensing margin of a bit line. | 11-13-2008 |
| 20080283814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material. | 11-20-2008 |
| 20080283815 | Variable resistance memory device having reduced bottom contact area and method of forming the same - A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit. | 11-20-2008 |
| 20080283816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with silicon pillars arranged in a matrix and formed substantially perpendicularly to a main surface of a substrate, bit lines provided above the silicon pillars, gate electrodes covering a side surface of each silicon pillars via gate insulation films, first and second diffusion layers provided at an upper part and a lower part of the silicon pillar, respectively, a reference potential wiring provided in common to the plural silicon pillars for supplying a reference potential to the first diffusion layers, and memory elements connected between the second diffusion layers and the bit lines. The gate electrodes covering the silicon pillars adjacent in a first direction crossing the bit line are in contact with each other, and gate electrodes covering the silicon pillars adjacent in a second direction parallel with the bit line are isolated from each other. | 11-20-2008 |
| 20080283817 | PHASE-CHANGE NONVOLATILE MEMORY DEVICE USING Sb-Zn ALLOY AND MANUFACTURING METHOD THEREOF - Provided are a phase-change nonvolatile memory device and a manufacturing method thereof. The device includes: a substrate; and a stack structure disposed on the substrate and including a phase-change material layer. The phase-change material layer is formed of an alloy of antimony (Sb) and zinc (Zn), so that the phase-change memory device can stably operate at high speed and reduce power consumption. | 11-20-2008 |
| 20080290335 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers. | 11-27-2008 |
| 20080296553 | INTEGRATED CIRCUIT HAVING CONTACT INCLUDING MATERIAL BETWEEN SIDEWALLS - An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit includes first material between the sidewalls of the contact. | 12-04-2008 |
| 20080296554 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device includes an array of phase change memory cells. Each phase change memory cell includes a selecting transistor disposed on a substrate. An upright electrode structure is electrically connected to the selecting transistor. An upright phase change memory layer is stacked on the upright electrode structure with a contact area therebetween, wherein the contact area serves as the location where phase transition takes place. | 12-04-2008 |
| 20080308784 | VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer. | 12-18-2008 |
| 20080308785 | PHASE CHANGE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a phase change memory device and a method for forming the phase change memory device. The method includes forming a phase change material layer by providing reactive radicals to a substrate. The reactive radicals may comprise precursors for a phase change material and nitrogen. | 12-18-2008 |
| 20080315171 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the first electrode and the second electrode. | 12-25-2008 |
| 20080315172 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a vertical diode defined by crossed line lithography. | 12-25-2008 |
| 20080315173 | INTEGRATED CIRCUIT HAVING MULTILAYER ELECTRODE - An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode. | 12-25-2008 |
| 20080315174 | VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME - Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode. | 12-25-2008 |
| 20090001341 | Phase Change Memory with Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 01-01-2009 |
| 20090001342 | MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a reversible resistance-switching element above the first conductor using a selective growth process; (3) forming a diode above the first conductor; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided. | 01-01-2009 |
| 20090001343 | MEMORY CELL THAT EMPLOYS A SELECTIVELY DEPOSITED REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided. | 01-01-2009 |
| 20090001344 | MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a reversible resistance-switching element above the first conductor using a selective growth process; (3) forming a diode above the first conductor; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided. | 01-01-2009 |
| 20090001345 | MEMORY CELL THAT EMPLOYS A SELECTIVELY DEPOSITED REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided. | 01-01-2009 |
| 20090001346 | Non-Volatile Polymer Bistability Memory Device - The present invention relates to non-volatile memory device utilizing multi-layered self-assembled Ni1-xFex nanocrystalline arrays embedded in a polymer thin film without source and drain regions and the fabrication method thereof. It is possible to fabricate nano-crystallines more simply than hitherto method according to the present invention. More particularly, it is possible to control size and density of nano-crystallines without agglomeration of the crystallines since the crystallines, which have uniform distribution, are besieged to polymer layer. Furthermore, the present invention provides the non-volatile bistable memory device having chemical and electrical stability of higher efficiency and lower cost than conventional flash memory devices with a nano floating gate. Also, source and drain region is unnecessary in the device of the present invention, it can reduce the throughput time and cost. | 01-01-2009 |
| 20090001347 | 3D R/W cell with reduced reverse leakage - A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element. | 01-01-2009 |
| 20090001348 | SEMICONDUCTOR DEVICE - A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal. | 01-01-2009 |
| 20090008623 | Methods of fabricating nonvolatile memory device and a nonvolatile memory device - Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas. | 01-08-2009 |
| 20090014706 | 4F2 SELF ALIGN FIN BOTTOM ELECTRODES FET DRIVE PHASE CHANGE MEMORY - Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include memory elements comprising programmable resistive material and self-aligned bottom electrodes. In preferred embodiments the area of the memory cell is 4F | 01-15-2009 |
| 20090014707 | NON-VOLATILE SOLID STATE RESISTIVE SWITCHING DEVICES - Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer. | 01-15-2009 |
| 20090014708 | SEMICONDUCTOR DEVICE - A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path. | 01-15-2009 |
| 20090020742 | SOLID ELECTROLYTE SWITCHING ELEMENT, AND FABRICATION METHOD OF THE SOLID ELECTROLYTE ELEMENT, AND INTEGRATED CIRCUIT - The switching element of the present invention is of a configuration that includes: a first electrode ( | 01-22-2009 |
| 20090020743 | SEMICONDUCTOR STRUCTURE, IN PARTICULAR PHASE CHANGE MEMORY DEVICE HAVING A UNIFORM HEIGHT HEATER - A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics. | 01-22-2009 |
| 20090020744 | STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film. | 01-22-2009 |
| 20090020745 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE - Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer. | 01-22-2009 |
| 20090020746 | SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY - A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material. | 01-22-2009 |
| 20090026437 | Copper compatible chalcogenide phase change memory with adjustable threshold voltage - A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer. | 01-29-2009 |
| 20090026438 | SOLID STATE ELECTROLYTE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a solid state electrolytes memory device is provided. An insulator layer is formed on a substrate. A conductive layer is formed on the insulator layer. At least two openings partially overlapped and capable of communicating with each other are formed in the conductive layer, so that the conductive layer forms at least a pair of tip electrodes. Thereafter, solid state electrolytes are filled in the openings. | 01-29-2009 |
| 20090026439 | Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other - Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided. | 01-29-2009 |
| 20090032793 | Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact - A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form. | 02-05-2009 |
| 20090032794 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side of the bottom electrode opposite the sidewall of the first dielectric layer. A top electrode couples the bottom electrode through a phase change layer. | 02-05-2009 |
| 20090032795 | Schottky diode and memory device including the same - A Schottky diode and a memory device including the same are provided. The Schottky diode includes a first metal layer and an Nb-oxide layer formed on the first metal layer. | 02-05-2009 |
| 20090039331 | PHASE CHANGE MATERIAL STRUCTURES - Structures including a phase change material are disclosed. The structure may include a first electrode; a second electrode; a phase change material electrically connecting the first electrode and the second electrode for passing a current therethrough; and a tantalum nitride heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-12-2009 |
| 20090039332 | RESISTIVE NON-VOLATILE MEMORY DEVICE - The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance. | 02-12-2009 |
| 20090039333 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer. | 02-12-2009 |
| 20090039334 | PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced. | 02-12-2009 |
| 20090039335 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - On an insulating film ( | 02-12-2009 |
| 20090039336 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen. | 02-12-2009 |
| 20090039337 | MEMORY ELEMENT AND MEMORY DEVICE - A memory element having a storage layer containing an ion source layer between a first electrode and a second electrode is provided. The memory element stores information by changing an electrical characteristic of the storage layer, wherein at least Zr is added to the ion source layer as a metal element together with an ion conducting material. | 02-12-2009 |
| 20090039338 | Phase change memory devices and fabrication methods thereof - In a memory device, at least one conductive contact having a width of less than, or equal to, about 30 nm may be formed on a first electrode. A dielectric layer may be formed on the sides of the at least one conductive contact, and a phase change material film may be formed on the conductive contact. A second electrode may be formed on the phase change material. | 02-12-2009 |
| 20090045387 | Resistively switching semiconductor memory - One embodiment provides a non-volatile semiconductor memory with CBRAM memory cells at which there exists, between the Ag-doped GeSe layer and the Ag top electrode, a chemically inert barrier layer improving the switching properties of the CBRAM memory cell. The active matrix material layer of the memory cell includes a GeSe/Ge:H double layer with a vitreous GeSe layer and an amorphous Ge:H layer. The amorphous Ge:H layer is positioned between the GeSe layer and the second electrode. Thus, the forming of AgSe conglomerates in the Ag doping and/or electrode layer is inhibited, so that precipitations are prevented and a homogeneous deposition of the silver doping layer is enabled. By means of the GeSe/Ge:H double layer system, the resistive non-volatile storage effect of the CBRAM memory cell is, on the one hand, preserved and, on the other hand, the chemical stability of the top electrode positioned thereabove is ensured by means of the thin Ge:H layer. | 02-19-2009 |
| 20090045388 | PHASE CHANGE MATERIAL STRUCTURE AND RELATED METHOD - A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-19-2009 |
| 20090045389 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes. | 02-19-2009 |
| 20090045390 | Multi-resistive state memory device with conductive oxide electrodes - A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO | 02-19-2009 |
| 20090050873 | System Including Memory with Resistivity Changing Material and Method of Making the Same - A method of manufacturing a memory cell includes: forming a first electrode, depositing a first insulator material over the first electrode, forming a via in the first insulator material, depositing a resistivity changing material in the via without completely filling the via, and forming a second electrode contacting the resistivity changing material. | 02-26-2009 |
| 20090057642 | Memory Device - A memory or switching device includes a mesa and a first electrode conforming to said mesa. The device also includes a second electrode and a phase-change or switching material disposed between said first and second electrodes. The phase-change or switching material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. Also described is a method for making a memory or switching device. The method includes providing a first insulator and configuring the first insulator to provide a mesa. A first conductive layer is provided conforming to the mesa. A phase-change or switching material is provided over a portion of the first conductive layer, and a second conductive layer is provided over the phase-change or switching material. | 03-05-2009 |
| 20090057643 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer. | 03-05-2009 |
| 20090057644 | Phase-change memory units, methods of forming the phase-change memory units, phase-change memory devices having the phase-change memory units and methods of manufacturung the phase-change memory devices - A phase-change memory unit includes a lower electrode on a substrate, a phase-change material layer pattern including germanium-antimony-tellurium (GST) and carbon on the lower electrode, a transition metal layer pattern on the phase-change material layer pattern, and an upper electrode on the first transition metal layer pattern. The phase-change memory unit may have good electrical characteristics. | 03-05-2009 |
| 20090057645 | Memory element with improved contacts - A phase-change memory element comprising a phase-change memory material, a first electrical contact and a second electrical contact. At least one of the electrical contacts having a sidewall electrically coupled to the memory material. | 03-05-2009 |
| 20090065757 | Nonvolatile Memory Element - A nonvolatile memory element in which Rb | 03-12-2009 |
| 20090065758 | PHASE CHANGE MEMORY ARRAY AND FABRICATION THEREOF - A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers. | 03-12-2009 |
| 20090065759 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a PN junction diode formed over a semiconductor substrate. Insulating films may be formed over the PN junction diode and patterned to have via holes. A resistive random access memory including a first metal pattern may be in contact with a first region of the PN junction diode. An oxide film pattern may be formed over the first metal pattern and a second metal pattern formed over the oxide film pattern. The first metal pattern, the oxide film pattern and the second metal pattern may be formed in the via holes. | 03-12-2009 |
| 20090065760 | RESISTIVE MEMORY DEVICES AND METHODS OF FORMING RESISTIVE MEMORY DEVICES - Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed. | 03-12-2009 |
| 20090072215 | PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned. | 03-19-2009 |
| 20090072216 | PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings. | 03-19-2009 |
| 20090072217 | Integrated Circuits; Methods for Manufacturing an Integrated Circuit and Memory Module - Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate having a main processing surface, at least two first electrodes, wherein each of the two first electrodes has a side surface being arranged at a respective angle with regard to the main processing surface, the side surfaces facing one another. The programmable arrangement may further include at least one second electrode and ion conducting material between each of the at least two first electrodes and the at least one second electrode, wherein the at least one second electrode is arranged partially between the side surfaces of the two first electrodes facing one another. | 03-19-2009 |
| 20090072218 | Higher threshold voltage phase change memory - A phase change memory may be formed of a phase change material alloy that produces a higher threshold voltage and, in some cases, is operable at higher temperatures. For example, the formulation may include a poor metal, antimony, and at least one of tellurium or selenium. | 03-19-2009 |
| 20090078925 | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers. | 03-26-2009 |
| 20090078926 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed. | 03-26-2009 |
| 20090085024 | PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers. | 04-02-2009 |
| 20090085025 | MEMORY DEVICE INCLUDING RESISTANCE-CHANGING FUNCTION BODY - A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost. | 04-02-2009 |
| 20090090899 | Phase change memory device and method of manufacturing the same - A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole. | 04-09-2009 |
| 20090095950 | Nanoscale Wire-Based Data Storage - The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example, a nanoscale wire may comprise a core and an electrically-polarizable shell. In some cases, the electrically-polarizable region is able to retain its polarization state in the absence of an external electric field. All, or only a portion, of the electricallypolarizable region may be polarized, for example, to encode one or more bits of data. In one set of embodiments, the electrically-polarizable region comprises a functional oxide or a ferroelectric oxide material, for example, BaTiO | 04-16-2009 |
| 20090095951 | Memory Device With Low Reset Current - An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer. | 04-16-2009 |
| 20090095952 | Storage node, phase change memory device and methods of operating and fabricating the same - A storage node, a phase change memory device, and methods of operating and fabricating the same are provided. The storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer. A thickness of the phase change layer may be about 100 nm or less, and the lower electrode may be composed of an n-type thermoelectric material, and the upper electrode may be composed of a p-type thermoelectric material, or they may be composed on the contrary to the above. Seeback coefficients of the lower electrode, the phase change layer, and the upper electrode may be different from each other. | 04-16-2009 |
| 20090095953 | PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY DEVICES - A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical communication with the phase change medium, an optical phase change storage device in which data is read and written optically, or a storage device based on the principle of scanning probe microscopy. | 04-16-2009 |
| 20090114899 | RESISTANCE MEMORY AND METHOD FOR MANUFACTURING THE SAME - A resistance memory is manufactured using semiconductor processing to comprise planar dual-tip electrodes so that the electric field in the resistance memory is concentrated to reduce the number of fuses in the dielectric material and improve the device characteristics. The resistance memory comprises: a first memory cell including a first bottom electrode and a common top electrode; and a second memory cell including a second bottom electrode and the common top electrode shared with the first memory cell; wherein the first bottom electrode, the second bottom electrode and the common top electrode are disposed on the same plane and are separated by a resistive conversion layer; wherein the common top electrode is connected to the ground through a via, while the first bottom electrode and the second bottom electrode are connected to the source of a transistor through a plug, respectively. | 05-07-2009 |
| 20090121209 | SEMICONDUCTOR DEVICE WITH TUNABLE ENERGY BAND GAP - The present invention relates to a semiconductor device in which energy band gap can be reversibly varied. An idea of the present invention is to provide a device, which is based on a semiconducting material ( | 05-14-2009 |
| 20090121210 | FORMATION OF SELF-ASSEMBLED MONOLAYERS ON SILICON SUBSTRATES - This invention provides a new method of forming a self-assembling monolayer (SAM) of alcohol-terminated or thiol-terminated organic molecules (e.g. ferrocenes, porphyrins, etc.) on a silicon or other group IV element surface. The assembly is based on the formation of an E-O— or an E-S— bond where E is the group IV element (e.g. Si, Ge, etc.). The procedure has been successfully used on both P- and n-type group IV element surfaces. The assemblies are stable under ambient conditions and can be exposed to repeated electrochemical cycling. | 05-14-2009 |
| 20090121211 | Solution-Based Deposition Process for Metal Chalcogenides - A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices. | 05-14-2009 |
| 20090121212 | SMALL ELECTRODE FOR PHASE CHANGE MEMORIES - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided. | 05-14-2009 |
| 20090127536 | INTEGRATED CIRCUIT HAVING DIELECTRIC LAYER INCLUDING NANOCRYSTALS - An integrated circuit includes a first electrode, resistivity changing material coupled to the first electrode, and a second electrode. The integrated circuit includes a dielectric material layer between the resistivity changing material and the second electrode. The dielectric material layer includes nanocrystals. | 05-21-2009 |
| 20090127537 | ELECTRIC DEVICE WITH PHASE CHANGE RESISTOR - An electric device has an electrically switchable resistor ( | 05-21-2009 |
| 20090140231 | Semiconductor device and method of manufacturing the same - It is an object of the present invention to provide a technique in which a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield. A memory device according to the present invention has a first conductive layer including a plurality of insulators, an organic compound layer over the first conductive layer including the insulators, and a second conductive layer over the organic compound layer. | 06-04-2009 |
| 20090140232 | Resistive Memory Element - An integrated circuit including a resistive memory element is described. The resistive memory element includes a first solid electrolyte layer including a metal doped glass material, the glass material being at least partially amorphous, and a second solid electrolyte layer including the metal doped glass material. The resistive memory element also includes a middle layer disposed between the first and second solid electrolyte layers, the middle layer including a carbide composition. | 06-04-2009 |
| 20090140233 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a large storage capacity and stabilized rewriting conditions in which a memory cell includes a nonvolatile recording material layer, a selector element and a semiconductor layer provided between the nonvolatile recording material layer and the selector element and having a thickness ranging from 5 to 200 nm. | 06-04-2009 |
| 20090140234 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film. | 06-04-2009 |
| 20090146128 | ELECTRICAL DEVICE USING PHASE CHANGE MATERIAL, PHASE CHANGE MEMORY DEVICE USING SOLID STATE REACTION AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed. | 06-11-2009 |
| 20090146129 | MULTI-BIT MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor memory cell including phase change material. A multi-bit memory cell may implement phase change material. Various kinds of information can be stored in one memory cell. A chip size may be minimized without sacrificing capacity and/or memory performance, as compared with a one-bit memory cell. | 06-11-2009 |
| 20090146130 | Nitrogenated Carbon Electrode for Chalcogenide Device and Method of Making Same - A nitrogenated carbon electrode suitable for use in a chalcogenide device and method of making the same are described. The electrode comprises nitrogenated carbon and is in electrical communication with a chalcogenide material. The nitrogenated carbon material may be produced by combining nitrogen and vaporized carbon in a physical vapor deposition process. | 06-11-2009 |
| 20090152526 | Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof - The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients. | 06-18-2009 |
| 20090159868 | Phase change material layer and phase change memory device including the same - Provided are a phase change material layer and a phase change random access memory (PRAM) device including the same. By providing a phase change material layer formed of a III-V family material and a chalcogenide, a PRAM device with a set time shorter than that of a conventional PRAM device and improved retention characteristics can be provided. | 06-25-2009 |
| 20090166602 | PHASE-CHANGE MEMORY DEVICE CAPABLE OF IMPROVING CONTACT RESISTANCE AND RESET CURRENT AND METHOD OF MANUFACTURING THE SAME - A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom electrode contact in contact with the switching device through a first contact area and in contact with the phase-change layer through a second contact area, which is smaller than the first contact area. | 07-02-2009 |
| 20090166603 | METHOD OF FORMING A SMALL CONTACT IN PHASE-CHANGE MEMORY - A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells. | 07-02-2009 |
| 20090166604 | RESISTANCE TYPE MEMORY DEVICE - A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity. | 07-02-2009 |
| 20090173930 | MEMORY ELEMENT AND MEMORY DEVICE - A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen. | 07-09-2009 |
| 20090184309 | PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR - A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure. | 07-23-2009 |
| 20090184310 | MEMORY CELL WITH MEMORY ELEMENT CONTACTING AN INVERTED T-SHAPED BOTTOM ELECTRODE - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element is on the top surface of the pillar portion and comprises memory material having at least two solid phases. A top electrode is on the memory element. | 07-23-2009 |
| 20090189140 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal. | 07-30-2009 |
| 20090189141 | Phase change memory device and method of forming the same - A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact. | 07-30-2009 |
| 20090189142 | Phase-Change Memory - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 07-30-2009 |
| 20090194758 | HEATING CENTER PCRAM STRUCTURE AND METHODS FOR MAKING - Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials. | 08-06-2009 |
| 20090194759 | PHASE CHANGE MEMORY DEVICE - A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly of gallium (Ga), antimony (Sb) and tellurium (Te) and unavoidable impurities, having the composition range of Ga | 08-06-2009 |
| 20090194760 | Memory element and display device - Disclosed herein is a memory element, including a parallel combination of a thin film transistor; and a resistance change element, the thin film transistor including a semiconductor thin film in which a channel region, and an input terminal and an output terminal located on both sides of the channel region, respectively, are formed, and a gate electrode overlapping the channel region through an insulating film to become a control terminal, the resistance change element including one conductive layer connected to the input terminal side of the thin film transistor, the other conductive layer connected to the output terminal side of the thin film transistor, and at least one oxide film layer disposed between the one conductive layer and the other conductive layer. | 08-06-2009 |
| 20090200536 | Method for manufacturing an electric device with a layer of conductive material contracted by nanowire - The electric device ( | 08-13-2009 |
| 20090200537 | PHASE CHANGE MEMORY DEVICE PREVENTING CONTACT LOSS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change cells. A plurality of bit lines are electrically connected to the contacts. A contact plug is formed on the silicon substrate in a region outside of the phase change cell region, and a word line is formed over the silicon substrate and is connected to the contact plug. | 08-13-2009 |
| 20090206315 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact. | 08-20-2009 |
| 20090206316 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact. | 08-20-2009 |
| 20090206317 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a phase change memory device includes steps of forming a first encapsulation layer on a semiconductor substrate having a bottom electrode contact and a phase change material layer stack structure contacting the bottom electrode contact, and forming a plurality of encapsulation spacers on sidewalls of the phase change material layer stack structure using a spacer etching process. | 08-20-2009 |
| 20090206318 | Nonvolatile memory device and method of manufacturing the same - A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen. | 08-20-2009 |
| 20090212273 | Semiconductor Devices Having Resistive Memory Elements - Provided is a semiconductor device including a resistive memory element. The semiconductor device includes a substrate and the resistive memory element disposed on the substrate. The resistive memory element has resistance states of a plurality of levels according to generation and dissipation of at least one platinum bridge therein. | 08-27-2009 |
| 20090218558 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate. | 09-03-2009 |
| 20090230378 | RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. An insulating layer enclosing a resistive memory element and an insulating layer enclosing a conductive line connected with the resistive memory element have different stresses, hardness, porosity degrees, dielectric constant or heat conductivities. | 09-17-2009 |
| 20090236583 | Method of fabricating a phase change memory and phase change memory - The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated. | 09-24-2009 |
| 20090242867 | PHASE CHANGE MEMORY DEVICE HAVING PROTECTIVE LAYER FOR PROTECTING PHASE CHANGE MATERIAL AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate, a plurality of bottom electrodes formed on the substrate, a plurality of phase change structures formed on the semiconductor substrate, each respectively contacting one of the bottom electrodes, and each having a phase change material layer and a top electrode stacked one upon the other, and a protective layer formed to a substantially uniform thickness on surfaces of the plurality of phase change structures and the semiconductor substrate, wherein the protective layer contains diffusion barrier ions. | 10-01-2009 |
| 20090242868 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably. | 10-01-2009 |
| 20090250681 | Non-Volatile Resistive Oxide Memory Cells, Non-Volatile Resistive Oxide Memory Arrays, And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells And Memory Arrays - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated. | 10-08-2009 |
| 20090250682 | PHASE CHANGE MEMORY DEVICE - Provided is a phase change memory device. The phase change memory device includes a first electrode and a second electrode. A phase change material pattern is interposed between the first and second electrodes. A phase change auxiliary pattern is in contact with at least one side of the phase change material pattern. The phase change auxiliary pattern includes a compound having a chemical formula expressed as D | 10-08-2009 |
| 20090256129 | Sidewall structured switchable resistor cell - A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction. | 10-15-2009 |
| 20090256130 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT, AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided. | 10-15-2009 |
| 20090256131 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT FORMED OVER A BOTTOM CONDUCTOR AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided. | 10-15-2009 |
| 20090256132 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described. | 10-15-2009 |
| 20090261313 | MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME - Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element. | 10-22-2009 |
| 20090261314 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer. | 10-22-2009 |
| 20090267047 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material. | 10-29-2009 |
| 20090272960 | Non-Volatile Resistive Oxide Memory Cells, and Methods Of Forming Non-Volatile Resistive Oxide Memory Cells - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section. | 11-05-2009 |
| 20090272961 | SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS - This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution. | 11-05-2009 |
| 20090272962 | REDUCTION OF FORMING VOLTAGE IN SEMICONDUCTOR DEVICES - This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (RRAM) that use techniques to provide a memory device with more predictable operation. In particular, forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or through the use of an anneal in a reducing environment. One or more of these techniques may be applied, depending on desired application and results. | 11-05-2009 |
| 20090278108 | Phase change memory device having phase change material layer containing phase change nano particles and method of fabricating the same - A phase change memory device including a phase change material layer having phase change nano particles and a method of fabricating the same are provided. The phase change memory device may include a first electrode and a second electrode facing each other, a phase change material layer containing phase change nano particles interposed between the first electrode and the second electrode and/or a switching device electrically connected to the first electrode. The phase change material layer may include an insulating material. | 11-12-2009 |
| 20090278109 | CONFINEMENT TECHNIQUES FOR NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Confinment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode. | 11-12-2009 |
| 20090278110 | NON-VOLATILE RESISTIVE-SWITCHING MEMORIES FORMED USING ANODIZATION - Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element. | 11-12-2009 |
| 20090278111 | RESISTIVE CHANGING DEVICE - A device that incorporates teachings of the present disclosure may include, for example, a memory array having a first array of nanotubes, a second array of nanotubes, and a resistive change material located between the first and second array of nanotubes. Other embodiments are disclosed. | 11-12-2009 |
| 20090283738 | Phase-change memory using single element semimetallic layer - Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material. | 11-19-2009 |
| 20090283739 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - There is provided a nonvolatile storage device including a plurality of component memory layers. The plurality of component memory layers are stacked In a direction perpendicular to a layer surface. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring and a stacked structure unit provided between the first wiring and the second wiring and including a recording layer. At least one of the first wiring and the second wiring includes a protruding portion provided on a portion opposed to the recording layer and protruding toward the recording layer side. | 11-19-2009 |
| 20090283740 | OPTIMIZED SOLID ELECTROLYTE FOR PROGRAMMABLE METALLIZATION CELL DEVICES AND STRUCTURES - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 11-19-2009 |
| 20090283741 | METHOD OF FORMING A PHASE CHANGEABLE STRUCTURE - The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern. | 11-19-2009 |
| 20090289243 | SHORT BRIDGE PHASE CHANGE MEMORY CELLS AND METHOD OF MAKING - Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge. | 11-26-2009 |
| 20090294750 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively. | 12-03-2009 |
| 20090294751 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated. | 12-03-2009 |
| 20090302298 | Forming sublithographic phase change memory heaters - A phase change memory may be formed with a sublithographic heater by using a mask with a sidewall spacer to etch an opening in a dielectric layer. The opening then has a sublithographic lateral extent. The resulting via may be filled with a heater material to form a sublithographic heater. | 12-10-2009 |
| 20090302299 | PHASE CHANGE MEMORY DEVICE HAVING A WORD LINE CONTACT AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having a word line contact includes an N+ base layer formed in a surface of a semiconductor substrate. A word line is formed over the N+ base layer. The word line contact is formed to connect the N+ base layer to the word line. The word line contact includes a first contact plug, a barrier layer formed on the first contact plug, and a second contact plug formed on the barrier layer coaxially with the first contact plug. The barrier layer prevents unwanted etching of the first contact plug when the second contact plug is being formed. | 12-10-2009 |
| 20090302300 | PHASE CHANGE MEMORY DEVICE HAVING DECREASED CONTACT RESISTANCE OF HEATER AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a silicon substrate having cell and peripheral regions. A first insulation layer with a plurality of holes is formed in the cell region. Recessed cell switching elements are formed in the holes. Heat sinks are formed in the holes in which the cell switching elements are formed, and the heat sinks project out of the first insulation layer. A gate is formed in the peripheral region and has a stack structure of a gate insulation layer, a first gate conductive layer, a second gate conductive layer, and a hard mask layer. A second insulation layer is formed on the surface of the silicon substrate. The second insulation layer has contact holes exposing the heat sinks. Heaters are formed in the contact holes, and stack patterns of a phase change layer and a top electrode are formed on the heaters. | 12-10-2009 |
| 20090302301 | RESISTANCE RAM DEVICE HAVING A CARBON NANO-TUBE AND METHOD FOR MANUFACTURING THE SAME - A resistance RAM (ReRAM) device and method of manufacturing the same are presented. The ReRAM exhibits an improved set resistance distribution and an improved reset resistance distribution. The ReRAM device includes a lower electrode contact that has at least one carbon nano-tube; and a binary oxide layer formed over the lower electrode contact. The binary oxide layer is for storing information in accordance to two different resistance states of the binary oxide layer. | 12-10-2009 |
| 20090302302 | METAL OXIDE RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME - Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein. | 12-10-2009 |
| 20090321706 | Resistive Memory Devices with Improved Resistive Changing Elements - An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states. | 12-31-2009 |
| 20090321707 | Intersubstrate-dielectric nanolaminate layer for improved temperature stability of gate dielectric films - Embodiments of an apparatus with a crystallization-resistant high-κ dielectric and nanolaminate layer stack in a device and methods for forming crystallization-resistant high-κ dielectric and nanolaminate layer stack are generally described herein. Other embodiments may be described and claimed. | 12-31-2009 |
| 20090321708 | PHASE CHANGE MEMORY DEVICE HAVING PROTECTIVE LAYER AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a plurality of phase change structures, each with a phase change material layer, disposed on a semiconductor substrate, a first protective layer formed to cover surfaces of the plurality of phase change structures, an atom adsorption enhancement layer formed on a surface of the first protective layer, and a second protective layer formed on a surface of the atom adsorption enhancement layer. | 12-31-2009 |
| 20090321709 | MEMORY ELEMENT, MEMORY APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A memory element comprises a first electrode, a second electrode, and a resistance variable film | 12-31-2009 |
| 20090321710 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration. | 12-31-2009 |
| 20100001252 | Resistance Changing Memory Cell - An integrated circuit includes a plurality of programmable metallization memory cells. Each memory cell includes a memory element having a first electrode layer, a second electrode layer, and a resistance changing material layer arranged between the first electrode layer and the second electrode layer. The resistance changing material layer includes an active matrix material layer made of a chalcogenide material including at least one chalcogen and at least one electropositive element, wherein the chalcogenide material is not GeS, GeSe, AgSe or CuS. | 01-07-2010 |
| 20100001253 | Method for delineation of phase change memory cell via film resistivity modification - A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power. | 01-07-2010 |
| 20100001254 | RESISTANCE MEMORY ELEMENT - A resistance memory element is provided which has a relatively high switching voltage and whose resistance can be changed at a relatively high rate. The resistance memory element includes an elementary body and a pair of electrodes opposing each other with at least part of the elementary body therebetween. The elementary body is made of a semiconductor ceramic expressed by a formula: {(Sr | 01-07-2010 |
| 20100006813 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed. | 01-14-2010 |
| 20100006814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer. | 01-14-2010 |
| 20100006815 | PHASE CHANGE MEMORY AND RECORDING MATERIAL FOR PHASE CHANGE MEMORY - A recording material for a phase change solid memory may include a uniform-mixed phase that includes: at least one of a Te-containing alkali metal iodide phase and a Te-containing silver iodide phase, and an Sb—Te alloy phase. The recording material shows at least one of a phase change and a phase separation which changes at least one of optical property and electrical property of the recording material. | 01-14-2010 |
| 20100012916 | PHASE CHANGE MEMORY - A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line. | 01-21-2010 |
| 20100012917 | SEMICONDUCTOR DEVIC - On an insulating film ( | 01-21-2010 |
| 20100019218 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A resistive memory device includes: a substrate, an insulation layer arranged over the substrate, a first electrode plug penetrating the insulation layer from the substrate, having a portion protruded out of an upper portion of the insulation layer, and having peaks at edges of the protruded portion, a resistive layer disposed over the insulation layer and covering the first electrode plug, and a second electrode arranged over the resistive layer. | 01-28-2010 |
| 20100019219 | RESISTIVE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A resistive memory device and a method for manufacturing the same are disclosed. The resistive memory device includes a lower electrode formed over a substrate, a resistive layer disposed over the lower electrode, an upper electrode formed over the resistive layer, and an oxygen-diffusion barrier pattern provided in an interface between the resistive layer and the upper electrode. The above-described resistive memory device and a method for manufacturing the same may prevent the out diffusion of oxygen in the interface of the upper electrode to avoid set-stuck phenomenon occurring upon the operation of the resistive memory device, thereby improving the endurance of the resistive memory device. | 01-28-2010 |
| 20100019220 | Phase change random access memory device, method of fabricating the same, and method of operating the same - Provided are a phase change random access memory (PRAM), a method of fabricating the PRAM, and a method of operating the PRAM. The PRAM may include a gate electrode configured to temporarily increase an electrical resistance of the lower electrode contact layer if a voltage is applied to the gate electrode, and around the lower electrode contact layer between a switching device and a phase change layer. A spacer insulating layer is disposed between the lower electrode contact layer and the gate electrode. | 01-28-2010 |
| 20100032642 | Method of Manufacturing a Resistivity Changing Memory Cell, Resistivity Changing Memory Cell, Integrated Circuit, and Memory Module - According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask. | 02-11-2010 |
| 20100032643 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by (a) depositing a layer of the carbon material above a substrate; (b) doping the deposited carbon layer with a dopant; (c) depositing a layer of the carbon material over the doped carbon layer; and (d) iteratively repeating steps (b) and (c) to form a stack of doped carbon layers having a desired thickness. Other aspects are also provided. | 02-11-2010 |
| 20100038622 | CONNECTIBLE NANOTUBE CIRCUIT - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 02-18-2010 |
| 20100038623 | METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING - Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the memory element, but not the steering element, to form multiple memory cells that share a single steering element. Memory cells formed from such methods, as well as numerous other aspects are also disclosed. | 02-18-2010 |
| 20100038624 | MEMORY DEVICE HAVING HIGHLY INTEGRATED CELL STRUCTURE AND METHOD OF ITS FABRICATION - In an embodiment, a memory device, with a highly integrated cell structure, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern. | 02-18-2010 |
| 20100044670 | Semiconductor device structures having single-crystalline switching device on conducting lines and methods thereof - A memory device includes a composite dielectric layer overlying a substrate. The composite dielectric layer includes a first dielectric layer, a bonding interface, and a second dielectric layer. The first and the second dielectric layers are bonded together at the bonding interface. A first plurality of conductive lines overlies the combined dielectric layer. One or more semiconductor switching devices formed in a single-crystalline semiconductor layer overlie and are coupled with one of the first plurality of conductive lines. The memory device also has one or more two-terminal memory elements, each of which overlies and is coupled to a corresponding one of the single-crystalline switching device. A second plurality of conductive lines overlies the memory elements. In the memory device, each of the memory elements is coupled to one of the first plurality of conductive lines and one of the second plurality of conductive lines. | 02-25-2010 |
| 20100044671 | METHODS FOR INCREASING CARBON NANO-TUBE (CNT) YIELD IN MEMORY DEVICES - In some aspects, a method of forming a carbon nano-tube (CNT) memory cell is provided that includes ( | 02-25-2010 |
| 20100044672 | SEMICONDUCTOR MEMORY - Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer. | 02-25-2010 |
| 20100051895 | PHASE CHANGE MATERIAL, A PHASE CHANGE RANDOM ACCESS MEMORY DEVICE INCLUDING THE PHASE CHANGE MATERIAL, A SEMICONDUCTOR STRUCTURE INCLUDING THE PHASE CHANGE MATERIAL, AND METHODS OF FORMING THE PHASE CHANGE MATERIAL - A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed. | 03-04-2010 |
| 20100051896 | VARIABLE RESISTANCE MEMORY DEVICE USING A CHANNEL-SHAPED VARIABLE RESISTANCE PATTERN - A variable resistance memory device includes a substrate and a plurality of spaced apart lower electrodes on the substrate. The device further includes a variable resistance material pattern comprising two vertically opposed wall members connected by a bottom member disposed on and electrically connected to at least one of the plurality of lower electrodes and an upper electrode on the variable resistance material pattern. An area of contact of the variable resistance material pattern with the at least one lower electrode may be rectangular, circular, ring-shaped, or arc-shaped. Fabrication methods are also described. | 03-04-2010 |
| 20100065803 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a resistance variable non-volatile memory device using a trap-controlled Space Charge Limited Current (SCLC), and a manufacturing method thereof. The memory device includes a bottom electrode; an inter-electrode dielectric thin film diffusion prevention film formed on the bottom electrode; a dielectric thin film formed on the inter-electrode dielectric thin film diffusion prevention film and having a plurality of layers with different charge trap densities; and a top electrode formed on the dielectric thin film. | 03-18-2010 |
| 20100065804 | PHASE CHANGE MEMORY DEVICE HAVING MULTIPLE METAL SILICIDE LAYERS AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having multiple metal silicide layers which enhances the current driving capability of switching elements and a method of manufacturing the same are presented. The device also includes switching elements, heaters, stack patterns, top electrodes, bit lines, word line contacts and word lines. The bottom of the switching elements are in electrical contact with the lower metal silicide layer and with an active area of silicon substrate. An upper metal silicide layer is interfaced between the top of the switching elements and the heaters. The stack patterns include phase change layers and top electrodes and are between the heaters and the top electrodes are in electrical contact with the top electrodes. The bit lines contact with the top electrode contacts. The word line contacts to the lower metal silicide film. | 03-18-2010 |
| 20100065805 | PHASE CHANGE MEMORY DEVICE HAVING A BOTTLENECK CONSTRICTION AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a bottleneck constriction and method of making same are presented. The phase change memory device includes a semiconductor substrate, a lower electrode, an interlayer film, an insulator, a phase change layer and an upper electrode. The interlayer film is formed on the semiconductor substrate having the lower electrode. The interlayer film includes a laminate of a first insulating film, a silicon film and a second insulating film with a hole formed therethrough. The insulator is disposed along the exposed surface of the silicon film around the inner circumference of the hole. The phase change layer is embedded within the hole having the insulator which constricts the shape of the phase change layer to a bottleneck constriction. A method of manufacturing the phase change memory device is also provided. | 03-18-2010 |
| 20100065806 | PROGRAMMABLE RESISTANCE MEMORY DEVICES AND SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed. | 03-18-2010 |
| 20100072448 | PLANAR PROGRAMMABLE METALLIZATION MEMORY CELLS - Programmable metallization memory cells that have an inert electrode and an active electrode positioned in a non-overlapping manner in relation to a substrate. A fast ion conductor material is in electrical contact with and extends from the inert electrode to the active electrode, the fast ion conductor including superionic clusters extending from the inert electrode to the active electrode. A metal layer extends from the inert electrode to the active electrode, yet is electrically insulated from each of the inert electrode and the active electrode by the fast ion conductor material. Methods for forming programmable metallization cells are also disclosed. | 03-25-2010 |
| 20100072449 | RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND METHOD OF MAKING THE SAME - A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light. | 03-25-2010 |
| 20100072450 | PHASE CHANGE MEMORY DEVICE WITH HEATER ELECTRODES HAVING FINE CONTACT AREA AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode. | 03-25-2010 |
| 20100072451 | SEMICONDUCTOR DEVICE - A recording layer | 03-25-2010 |
| 20100072452 | Non-volatile memory device - Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer. | 03-25-2010 |
| 20100078620 | SEMICONDUCTOR DEVICE WITH THERMALLY COUPLED PHASE CHANGE LAYERS - Various embodiments of the present invention are generally directed to an apparatus and method associated with a semiconductor device with thermally coupled phase change layers. The semiconductor device comprises a first phase change layer selectively configurable in a relatively low resistance crystalline phase and a relatively high resistance amorphous phase, and a second phase change layer thermally coupled to the first phase change layer. The second phase change layer is characterized as a metal-insulator transition material. A programming pulse is applied to the semiconductor device from a first electrode layer to a second electrode layer to provide the first phase change layer with a selected resistance. | 04-01-2010 |
| 20100078621 | METHOD TO REDUCE RESET CURRENT OF PCM USING STRESS LINER LAYERS - A memory cell structure and method for forming the same. The method includes forming a via within a dielectric layer. The via is formed over the center of an electrically conducting bottom electrode. The method includes depositing a stress liner along at least one sidewall of the via. The stress liner imparting stress on material proximate the stress liner. In one embodiment, the stress liner provides a stress in the range of 500 to 5000 MPa on the material enclosed within its volume. The method includes depositing phase change material within the via and the volume enclosed by the stress liner. The method also includes forming an electrically conducting top electrode above the phase change material. | 04-01-2010 |
| 20100078622 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes: a substrate; a stacked structure member including a plurality of dielectric films and a plurality of electrode films alternately stacked on the substrate and including a through-hole penetrating through the plurality of the dielectric films and the plurality of the electrode films in a stacking direction of the plurality of the dielectric films and the plurality of the electrode films; a semiconductor pillar provided in the through-hole; and a charge storage layer provided between the semiconductor pillar and each of the plurality of the electrode films. At least one of the dielectric films includes a film generating one of a compressive stress and a tensile stress, and at least one of the electrode films includes a film generating the other of the compressive stress and the tensile stress. | 04-01-2010 |
| 20100084625 | Memory Device - An electrical device includes a first electrode and a second electrode. A first active material is between the first electrode and second electrode. A second active material is between the first electrode and second electrode. A nonlinear electrode material is disposed between the first electrode and the second electrode. The nonlinear electrode material is electrically in series with the first electrode, the first active material, the second active material, and the second electrode. The first electrode and the first active material undergo no chemical or electrochemical reaction when current passes between the first electrode and the second electrode. | 04-08-2010 |
| 20100084626 | ELECTRONIC DEVICE COMPRISING A CONVERTIBLE STRUCTURE, AND A METHOD OF MANUFACTURING AN ELECTRONIC DEVICE - An electronic device ( | 04-08-2010 |
| 20100090192 | METHOD FOR CONTROLLED FORMATION OF THE RESISTIVE SWITCHING MATERIAL IN A RESISTIVE SWITCHING DEVICE AND DEVICE OBTAINED THEREOF - For improved scalability of resistive switching memories, a cross-point resistive switching structure is disclosed wherein the plug itself is used to store the resistive switching material and where the top electrode layer is self-aligned to the plug using, for example, chemical-mechanical-polishing (CMP) or simply mechanical-polishing. | 04-15-2010 |
| 20100090193 | NONVOLATILE MEMORY ELEMENT ARRAY AND MANUFACTURING METHOD THEREOF - A lower electrode ( | 04-15-2010 |
| 20100090194 | MULTI-BIT PHASE-CHANGE RANDOM ACCESS MEMORY (PRAM) WITH DIAMETER-CONTROLLED CONTACTS AND METHODS OF FABRICATING AND PROGRAMMING THE SAME - A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact. | 04-15-2010 |
| 20100096611 | VERTICALLY INTEGRATED MEMORY STRUCTURES - A device including a transistor that includes a source region; a drain region; and a channel region, wherein the channel region electrically connects the source region and the drain region along a channel axis; and a memory cell, wherein the memory cell is disposed adjacent the drain region so that the channel axis runs through the memory cell. | 04-22-2010 |
| 20100096612 | PHASE CHANGE MEMORY DEVICE HAVING AN INVERSELY TAPERED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having an inversely tapered bottom electrode and a method for forming the same is presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a bottom electrode contact and a phase change pattern. The insulation layer includes a bottom electrode contact hole having an insulation sidewall spacer such that the bottom electrode contact hole has an upper portion diameter that is smaller than a lower portion diameter. The bottom electrode contact is formed within the bottom electrode contact hole. The phase change pattern is formed on the bottom electrode contact. | 04-22-2010 |
| 20100096613 | SEMICONDUCTOR DEVICE - A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony. | 04-22-2010 |
| 20100102290 | SILICON BASED NANOSCALE CROSSBAR MEMORY - The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials. | 04-29-2010 |
| 20100102291 | CARBON-BASED MEMORY ELEMENTS EXHIBITING REDUCED DELAMINATION AND METHODS OF FORMING THE SAME - A method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including forming a first conducting layer comprising a degenerately doped semiconductor material, and forming a carbon-based reversible resistance-switching material above the first conducting layer. Other aspects are also provided. | 04-29-2010 |
| 20100108975 | NON-VOLATILE MEMORY CELL FORMATION - A method and apparatus for forming a non-volatile memory cell, such as a PMC memory cell. In some embodiments, a first electrode is connected to a source while a second electrode is connected to a ground. An ionic region is located between the first and second electrodes and comprises a doping layer, composite layer, and electrolyte layer. The composite layer has a low resistive state and the electrolyte layer switches from a high resistive state to a low resistive state based on the presence of a filament. | 05-06-2010 |
| 20100108976 | ELECTRONIC DEVICES INCLUDING CARBON-BASED FILMS, AND METHODS OF FORMING SUCH DEVICES - Methods in accordance with this invention form microelectronic structures, such as non-volatile memories, that include carbon layers, such as carbon nanotube (“CNT”) films, in a way that protects the CNT film against damage and short-circuiting. Microelectronic structures, such as non-volatile memories, in accordance with this invention are formed in accordance with such techniques. | 05-06-2010 |
| 20100108977 | NONVOLATILE PROGRAMMABLE SWITCH DEVICE USING PHASE-CHANGE MEMORY DEVICE AND METHOD OF MANURACTURING THE SAME - A nonvolatile programmable switch device using a phase-change memory device and a method of manufacturing the same are provided. The switch device includes a substrate, a first metal electrode layer disposed on the substrate and including a plurality of terminals, a phase-change material layer disposed on the substrate and having a self-heating channel structure, the phase-change material layer having a plurality of introduction regions electrically contacting the terminals of the first metal electrode layer and a channel region interposed between the introduction regions, an insulating layer disposed on the first metal electrode layer and the phase-change material layer, a via hole disposed on the first metal electrode layer, and a second metal electrode layer disposed to fill the via hole. The switch device performs memory operations using resistive heating of a phase-change material without an additional heater electrode, thereby minimizing thermal loss due to thermal conductivity of a metal electrode to reduce power consumption of the switch device. | 05-06-2010 |
| 20100108978 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal | 05-06-2010 |
| 20100108979 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device and a manufacturing method thereof that can reduce RC delay within the semiconductor device. Embodiments provide a semiconductor device including: a first interlayer dielectric layer formed over the a semiconductor substrate, a first metal wire and a second metal wire formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first and second metal wires, and a phase change material layer formed between the first and second metal wires. | 05-06-2010 |
| 20100117048 | MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS - A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions. | 05-13-2010 |
| 20100117049 | MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS - A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions. | 05-13-2010 |
| 20100117050 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 05-13-2010 |
| 20100117051 | MEMORY CELLS INCLUDING NANOPOROUS LAYERS CONTAINING CONDUCTIVE MATERIAL - A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer. | 05-13-2010 |
| 20100117052 | PROGRAMMABLE METALLIZATION CELLS AND METHODS OF FORMING THE SAME - A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed. | 05-13-2010 |
| 20100117053 | METAL OXIDE MATERIALS AND ELECTRODES FOR RE-RAM - Rewritable switching materials and methods for forming the same are described herein. One embodiment is a storage device comprising a first electrode, a state change element in contact with the first electrode, the state change element comprises Zr | 05-13-2010 |
| 20100117054 | NON-VOLATILE MEMORY DEVICE WITH DATA STORAGE LAYER - Provided is a non-volatile memory device including at least one horizontal electrode, at least one vertical electrode, at least one data storage layer and at least one reaction prevention layer. The least one vertical electrode crosses the at least one horizontal electrode. The at least one data storage layer is located in regions in which the at least one vertical electrode crosses the at least one horizontal electrode, and stores data by varying its electrical resistance. The at least one reaction prevention layer is located in the regions in which the at least one vertical electrode crosses the at least one horizontal electrode. | 05-13-2010 |
| 20100123116 | SWITCHING MATERIALS COMPRISING MIXED NANOSCOPIC PARTICLES AND CARBON NANOTUBES AND METHOD OF MAKING AND USING THE SAME - An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed. | 05-20-2010 |
| 20100127234 | PHASE CHANGE MEMORY DEVICE HAVING AN INCREASED SENSING MARGIN FOR CELL EFFICIENCY AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having an increased sensing margin for improved cell efficiency. The phase change memory device includes a plurality of diodes formed in an active region of a semiconductor substrate; an insulation layer pattern formed on the respective diodes; a phase change layer formed on the insulation layer pattern in such a way as not to be electrically connected with the diodes; bit lines formed over the phase change layer; and a global X-decoder line formed over the bit lines. The present invention suppresses current flow in a phase change memory device because the dummy cell string and the dummy active region are not electrically connected with each other under the global X-decoder line, whereby preventing parasitic current from being produced in the phase change memory device. | 05-27-2010 |
| 20100133501 | SWITCHING ELEMENT AND METHOD FOR MANUFACTURING SWITCHING ELEMENT - A switching element of the present invention utilizes electro-chemical reactions to operate, and comprises ion conductive layer | 06-03-2010 |
| 20100133502 | CMOS-Process-Compatible Programmable Via Device - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer. | 06-03-2010 |
| 20100140582 | CHALCOGENIDE NANOIONIC-BASED RADIO FREQUENCY SWITCH - A nonvolatile nanoionic switch is disclosed. A thin layer of chalcogenide glass engages a substrate and a metal selected from the group of silver and copper photo-dissolved in the chalcogenide glass. A first oxidizable electrode and a second inert electrode engage the chalcogenide glass and are spaced apart from each other forming a gap therebetween. A direct current voltage source is applied with positive polarity applied to the oxidizable electrode and negative polarity applied to the inert electrode which electrodeposits silver or copper across the gap closing the switch. Reversing the polarity of the switch dissolves the electrodeposited metal and returns it to the oxidizable electrode. A capacitor arrangement may be formed with the same structure and process. | 06-10-2010 |
| 20100140583 | PHASE CHANGE MEMORY DEVICE AND FABRICATING METHOD THEREFOR - A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer. | 06-10-2010 |
| 20100148142 | ALUMINUM COPPER OXIDE BASED MEMORY DEVICES AND METHODS FOR MANUFACTURE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode. | 06-17-2010 |
| 20100155686 | MEMRISTIVE DEVICE - A memristive device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least one of the first and second electrodes is a metal oxide electrode. | 06-24-2010 |
| 20100155687 | METHOD FOR MANUFACTURING A RESISTIVE SWITCHING MEMORY DEVICE AND DEVICES OBTAINED THEREOF - A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices. | 06-24-2010 |
| 20100155688 | ELECTRIC DEVICE WITH NANOWIRES COMPRISING A PHASE CHANGE MATERIAL - The method according to the invention is directed to manufacturing an electric device ( | 06-24-2010 |
| 20100163832 | SELF-ALIGNED NANO-CROSS-POINT PHASE CHANGE MEMORY - One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique. | 07-01-2010 |
| 20100163833 | ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD - A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST. | 07-01-2010 |
| 20100163834 | CONTACT STRUCTURE, METHOD OF MANUFACTURING THE SAME, PHASE CHANGEABLE MEMORY DEVICE HAVING THE SAME, AND METHOD OF MANUFACTURING PHASE CHANGEABLE MEMORY DEVICE - A contact structure, a method of manufacturing the same, a phase-changeable memory device having the same, and a method of manufacturing the phase-changeable memory device are described. The phase-changeable memory device includes: an upper electrode, a bit line, and a bit line contact unit. The upper electrode is on a semiconductor substrate having a phase-change pattern. The bit line is on the upper electrode. The bit line contact unit is interposed between the upper electrode and the bit line and electrically couples together the upper electrode to the bit line. The bit line contact unit includes a main conductive layer, a first and second barrier film. The first barrier film surrounds a bottom portion and a side portion of the main conductive layer. The second barrier film is on the main conductive layer. | 07-01-2010 |
| 20100171090 | Semiconductor phase-change memory device - A semiconductor phase-change memory device comprises a data line disposed on a semiconductor substrate and a data storage structure disposed under the data line and having a concave portion extending in a direction along the data line. A data contact structure is configured to contact the data storage structure, and having a lower portion filling the concave portion of the data storage structure and an upper portion surrounding at least a lower portion of the data line. Each of sidewalls of the data storage structure is disposed at substantially the same plane as a corresponding one of sidewalls of the upper portion of the data contact structure. | 07-08-2010 |
| 20100176366 | Nonvolatile memory cell including carbon storage element formed on a silicide layer - A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars. | 07-15-2010 |
| 20100176367 | MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT - Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell. | 07-15-2010 |
| 20100187493 | Semiconductor storage device and method of manufacturing the same - Disclosed is a semiconductor storage device including a first electrode formed by being embedded in an insulating film formed on a substrate, a second electrode formed to be opposed to the first electrode, a storage layer formed between the first electrode and the second electrode, the storage layer being on a side of the first electrode, an ion source layer formed between the storage layer and the second electrode, and a diffusion prevention layer formed of a manganese oxide layer between the insulating film and the first electrode. | 07-29-2010 |
| 20100193761 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 08-05-2010 |
| 20100193762 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening. | 08-05-2010 |
| 20100193763 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 08-05-2010 |
| 20100193764 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. | 08-05-2010 |
| 20100193765 | INVERTED VARIABLE RESISTANCE MEMORY CELL AND METHOD OF MAKING THE SAME - An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer deposited over a semiconductor substrate, etching the top portion of the opening to have a substantially hemispherical-shape, forming a metal layer in the opening, and overlying a variable resistance material over the metal layer. | 08-05-2010 |
| 20100200830 | MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE - Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess. | 08-12-2010 |
| 20100200831 | Non-volatile memory devices and methods of fabricating the same - Non-volatile memory devices including a lower electrode formed on a substrate; an active memory material formed on the lower electrode; an upper electrode formed on the active memory material; and an adhesive layer formed in part of a region between the active memory material and the upper electrode. | 08-12-2010 |
| 20100200832 | RESISTANCE VARIABLE ELEMENT - A resistance variable device is provided, which is capable of making a bipolar operation based on a predetermined operation principle. The resistance variable device is usable as a storage device. The resistance variable device has a laminated structure which include, for example, a first electrode, a second electrode, and a hole conductive layer between the first and second electrodes. The hole conductive layer gives anions to the second electrode, thereby changing its state from a reference electric field state to a positive electric field state. The hole conductive layer also receives anions from the second electrode, thereby changing its state from the positive electric field state to the reference electric field state. | 08-12-2010 |
| 20100207093 | Semiconductor device and method of manufacturing semiconductor device - Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto. | 08-19-2010 |
| 20100207094 | NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE SEMICONDUCTOR DEVICE USING THE NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element of the present invention comprises a first electrode ( | 08-19-2010 |
| 20100207095 | RESISTOR RANDOM ACCESS MEMORY CELL WITH L-SHAPED ELECTRODE - A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member. | 08-19-2010 |
| 20100213432 | PHASE CHANGE MEMORY DEVICE AND FABRICATION THEREOF - A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer. | 08-26-2010 |
| 20100213433 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon. | 08-26-2010 |
| 20100219393 | Connectible nanotube circuit - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 09-02-2010 |
| 20100224849 | Oxide diode, method of manufacturing the same, and electronic device and resistive memory device including the same - Provided are an oxide diode, a method of fabricating the oxide diode, and an electronic device including the oxide diode. The oxide diode may include an n-type oxide layer treated with plasma, and a p-type oxide layer on the n-type oxide layer. The plasma may include nitrogen. | 09-09-2010 |
| 20100224850 | Non-Volatile Memory Cells Employing a Transition Metal Oxide Layer as a Data Storage Material Layer and Methods of Manufacturing the Same - Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula M | 09-09-2010 |
| 20100230653 | PHASE-CHANGE MEMORY ELEMENT AND METHOD FOR FABRICATING THE SAME - A phase-change memory element is provided. The phase-change memory element includes: a first electrode formed on a substrate; a first dielectric layer, with an opening, formed on the first electrode, wherein the opening exposes a top surface of the first electrode; a pillar structure formed directly on the first electrode within the opening; an inner phase-change material layer surrounding the pillar structure, directly contacting the first electrode; a second dielectric layer surrounding the inner phase-change material layer; an outer phase-change material layer surrounding the second dielectric layer; a phase-change material collar formed between the second dielectric layer and the first electrode, connecting the inner phase-change material layer with the outer phase-change material layer; and a second electrode formed directly on the pillar structure, directly contacting the top surface of the inner phase-change material layer. | 09-16-2010 |
| 20100230654 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 09-16-2010 |
| 20100237316 | 4F2 SELF ALIGN SIDE WALL ACTIVE PHASE CHANGE MEMORY - Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F | 09-23-2010 |
| 20100237317 | RESISTIVE RANDOM ACCESS MEMORY, NONVOLATILE MEMORY, AND METHOD OF MANUFACTURING RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory includes a lower electrode; a metal oxide film formed on the lower electrode and having a variable resistance, the metal oxide film having a first portion containing a metal element forming the metal oxide film and a second portion richer in oxygen than the first portion; and an upper electrode formed on the metal oxide film. | 09-23-2010 |
| 20100237318 | PHASE CHANGE MEMORY DEVICE USING CARBON NANOTUBE - Provided are a phase change memory device that can operate at low power and improve the scale of integration by reducing a contact area between a phase change material and a bottom electrode, and a method for fabricating the same. The phase change memory comprises a current source electrode, a phase change material layer, a plurality of carbon nanotube electrodes, and an insulation layer. The current source electrode supplies external current to a target. The phase change material layer is disposed to face the current source electrode in side direction. The carbon nanotube electrodes are disposed between the current source electrode and the phase change material layer. The insulation layer is formed outside the carbon nanotube electrodes and functions to reduce the loss of heat generated at the carbon nanotube electrodes. | 09-23-2010 |
| 20100243983 | CONTROLLED LOCALIZED DEFECT PATHS FOR RESISTIVE MEMORIES - Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions. | 09-30-2010 |
| 20100252796 | RESISTANCE CHANGE ELEMENT AND METHOD OF MANUFACTURING THE SAME - In a resistance change element (ReRAM) storing data by utilizing change in resistance of a resistance change element, the resistance change element is configured of a lower electrode made of a noble metal such as Pt, a transition metal film made of a transition metal such as Ni, a transition metal oxide film made of a transition metal oxide such as NiOx, and a lower electrode made of a noble metal such as Pt. | 10-07-2010 |
| 20100252797 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device, includes: a memory layer having a resistance changeable by performing at least one selected from applying an electric field and providing a current, the memory layer having a first major surface and a second major surface opposite to the first major surface; a plurality of first electrodes provided on the first major surface; a second electrode provided on the second major surface; a probe electrode disposed to face the plurality of first electrodes, the probe electrode having a changeable relative positional relationship with the first electrodes; and a drive unit connected to the probe electrode and the second electrode to record information in the memory layer by causing at least one selected from applying the electric field and providing the current via the probe electrode to the memory layer between the second electrode and at least one of the plurality of first electrodes. | 10-07-2010 |
| 20100252798 | STORAGE ELEMENT, METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR STORAGE DEVICE - Disclosed herein is a storage element including: a first electrode; a second electrode formed in a position opposed to the first electrode; and a variable-resistance layer formed so as to be interposed between the first electrode and the second electrode. The first electrode is a tubular object, and is formed so as to be thicker on an opposite side from the variable-resistance layer than on a side of the variable-resistance layer. | 10-07-2010 |
| 20100258781 | RESISTIVE SWITCHING MEMORY ELEMENT INCLUDING DOPED SILICON ELECTRODE - A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa. | 10-14-2010 |
| 20100258782 | RESISTIVE-SWITCHING MEMORY ELEMENTS HAVING IMPROVED SWITCHING CHARACTERISTICS - Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness. | 10-14-2010 |
| 20100264397 | MEMRISTIVE DEVICE WITH A BI-METALLIC ELECTRODE - A memristive device having a bimetallic electrode includes a memristive matrix, a first electrode and a second electrode. The first electrode is in electrical contact with the memristive matrix and the second electrode is in electrical contact with the memristive matrix and an underlying layer. At least one of the first and second electrodes is a bimetallic electrode which includes a conducting layer and a metallic layer. | 10-21-2010 |
| 20100264398 | CHEMICAL VAPOR DEPOSITION METHOD FOR THE INCORPORATION OF NITROGEN INTO MATERIALS INCLUDING GERMANIUM AND ANTIMONY - A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge), antimony (Sb) and nitrogen (N) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of nitrogen-doped GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In some embodiments, the inventive method is a non-selective CVD process, which means that the nitrogen-doped GeSb materials are deposited equally well on insulating and non-insulating materials. In other embodiments, a selective CVD process is provided in which the nitrogen-doped GeSb materials are deposited only on regions of a substrate in a metal which is capable of forming an eutectic alloy with germanium. | 10-21-2010 |
| 20100270529 | INTEGRATED CIRCUIT 3D PHASE CHANGE MEMORY ARRAY AND MANUFACTURING METHOD - A 3D phase change memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a threshold switching element. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension. | 10-28-2010 |
| 20100276657 | MULTILAYER STRUCTURE COMPRISING A PHASE CHANGE MATERIAL LAYER AND METHOD OF PRODUCING THE SAME - A method of producing a multilayer structure is provided, wherein the method comprises forming a phase change material layer onto a substrate, forming a protective layer, forming a further layer on the protective layer, patterning the further layer in an first 5 patterning step, patterning the protective layer and the phase change material layer by a second patterning step. In particular, the first patterning step may be an etching step using chemical etchants. Moreover, electrodes may be formed on the substrate before the phase change material layer is formed, e.g. the electrodes may be formed on one level, e.g. may forma planar structure and may not form a vertically structure. | 11-04-2010 |
| 20100276658 | Resistive Memory Structure with Buffer Layer - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 11-04-2010 |
| 20100283030 | MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed. | 11-11-2010 |
| 20100288995 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes: a lower electrode including a plurality of projections formed on a top surface thereof; an oxide film covering the top surface and made of an oxide of a same metal as a metal contained in the lower electrode; and a resistance variable film provided on the oxide film and being in contact with the oxide film, the projections being buried in the oxide film, and a lower layer portion of the resistance variable film having an oxygen concentration lower than an oxygen concentration of a portion other than the lower layer portion of the resistance variable film. | 11-18-2010 |
| 20100295012 | NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE - A nonvolatile memory element comprises a resistance variable element | 11-25-2010 |
| 20100301303 | Forming Phase-Change Memory Using Self-Aligned Contact/Via Scheme - An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights. | 12-02-2010 |
| 20100308295 | Deletable nanotube circuit - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 12-09-2010 |
| 20100314601 | PHASE CHANGE MEMORY HAVING STABILIZED MICROSTRUCTURE AND MANUFACTURING METHOD - A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region. | 12-16-2010 |
| 20100314602 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer | 12-16-2010 |
| 20100320435 | PHASE-CHANGE MEMORY AND METHOD OF MAKING SAME - A phase-change memory cell structure includes a bottom diode on a substrate; a heating stem on the bottom diode; a first dielectric layer surrounding the heating stem, wherein the first dielectric layer forms a recess around the heating stem; a phase-change storage cap capping the heating stem and the first dielectric layer; and a second dielectric layer covering the first dielectric layer and the phase-change storage cap wherein the second dielectric layer defines an air gap in the recess. | 12-23-2010 |
| 20100327253 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G | 12-30-2010 |
| 20110001114 | PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER AND LOW RESISTIVITY INTERFACE - A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension. | 01-06-2011 |
| 20110001115 | RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 01-06-2011 |
| 20110001116 | BACK TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 01-06-2011 |
| 20110006278 | VARIABLE RESISTANCE NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A variable resistance non-volatile memory device of the laminated structure of an upper electrode a variable resistance material a lower electrode includes an insulating film formed for being contacted with the variable resistance material and a reset electrode formed for being contacted with the insulating film without being contacted with the upper electrode or the lower electrode. The device is reset by applying a voltage to the reset electrode. A low resistance value for the set state and a high resistance value for the reset state may be obtained as the current during the reset operation of the device is reduced. A low reset current and a high resistance ratio between the resistance value for the set state and that for the reset state are simultaneously achieved. | 01-13-2011 |
| 20110012083 | PHASE CHANGE MEMORY CELL STRUCTURE - A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface. | 01-20-2011 |
| 20110024714 | Nanoscale Three-Terminal Switching Device - A nanoscale three-terminal switching device has a bottom electrode, a top electrode, and a side electrode, each of which may be a nanowire. The top electrode extends at an angle with respect to the bottom electrode and has an end section going over and overlapping the bottom electrode. An active region is disposed between the top electrode and bottom electrode and contains a switching material. The side electrode is disposed opposite from the top electrode and in electrical contact with the active region. A self-aligned fabrication process may be used to automatically align the formation of the top and side electrodes with respect to the bottom electrode. | 02-03-2011 |
| 20110024715 | METHOD OF FABRICATING AG-DOPED TE-BASED NANO-MATERIAL AND MEMORY DEVICE USING THE SAME - A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer. | 02-03-2011 |
| 20110031462 | Electronic Component, And A Method of Manufacturing An Electronic Component - Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack. | 02-10-2011 |
| 20110031463 | RESISTANCE-CHANGE MEMORY - According to one embodiment, a resistance-change memory includes a variable resistance element having a laminated structure in which a first electrode, a resistance-change film and a second electrode are laminated, and set to a low-resistance state and a high-resistance state according to stored data, an insulating film provided on a side surface of the variable resistance element, and a fixed resistance element provided on a side surface of the insulating film, and includes a conductive film, the fixed resistance element being connected in parallel with the variable resistance element. | 02-10-2011 |
| 20110031464 | PHASE CHANGE MEMORY DEVICES AND METHODS OF FORMING A PHASE CHANGE MATERIAL - A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed. | 02-10-2011 |
| 20110031465 | RESISTANCE VARIABLE ELEMENT AND MANUFACTURING METHOD THEREOF - A resistance variable element of the present invention comprises a first electrode ( | 02-10-2011 |
| 20110037046 | RESISTANCE-CHANGE MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a resistance-change memory includes a laminated structure in which a lower electrode, an insulating film and an upper electrode are stacked, and a resistance-change film provided on a side surface of the laminated structure, and configured to store data in accordance with an electric resistance change. | 02-17-2011 |
| 20110037047 | PROGRAMMABLE METALLIZATION CELLS AND METHODS OF FORMING THE SAME - A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed. | 02-17-2011 |
| 20110042640 | METHOD OF FABRICATING PHASE CHANGE MEMORY CELL - A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. | 02-24-2011 |
| 20110049462 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 03-03-2011 |
| 20110049463 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes: a substrate; a first electrode formed on the substrate; a resistance change layer formed on the first electrode, the resistance change layer containing conductive nano-material; a second electrode formed on the resistance change layer; and an insulating buffer layer disposed between the first electrode and the resistance change layer, the insulating buffer layer containing conductive material dispersed therein for assuring the electric conductivity between the first electrode and the resistance change layer. | 03-03-2011 |
| 20110049464 | Resistive random access memory device and memory array including the same - A resistive random access memory (RRAM) includes a resistive memory layer of a transition metal oxide, such as Ni oxide, and is doped with a metal material. The RRAM may include at least one first electrode, a resistive memory layer on the at least one first electrode, the resistive memory layer including a Ni oxide layer doped with at least one element selected from a group consisting of Fe, Co, and Sn, and at least one second electrode on the resistive memory layer. The RRAM device may include a plurality of first electrodes and a plurality of second electrodes, and the resistive memory layer may be between the plurality of first electrodes and the plurality of second electrodes. | 03-03-2011 |
| 20110062407 | INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a recording layer which includes a typical element and a transition element, and stores a state of a first electric resistivity and a state of a second electric resistivity different from the first electric resistivity by a movement of the typical element, and an electrode layer which is disposed at one end of the recording layer to apply a voltage or a current to the recording layer. The recording layer includes a first region which is in contact with the electrode layer and the electrode layer includes a second region which is in contact with the recording layer. The first and second regions are opposite to each other. And the first and second regions include the typical element, and a concentration of the typical element in the first region is higher than that in the second region. | 03-17-2011 |
| 20110062408 | PROGRAMMABLE METALLIZATION CELL STRUCTURE INCLUDING AN INTEGRATED DIODE, DEVICE INCLUDING THE STRUCTURE, AND METHOD OF FORMING SAME - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 03-17-2011 |
| 20110068313 | MEMORY DEVICES WITH ENHANCED ISOLATION OF MEMORY CELLS, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device. | 03-24-2011 |
| 20110068314 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of an embodiment includes: a cathode electrode formed of a p-type semiconductor material; a resistance change film being in contact with the cathode electrode; and an anode electrode being contact with the resistance change film. | 03-24-2011 |
| 20110068315 | SEMICONDUCTOR MEMORY DEVICE INCLUDING RESISTANCE-CHANGE MEMORY - A semiconductor memory device includes first lines and second lines and a memory cell array. The first lines and second lines are formed to intersect each other. The memory cell array includes memory cells arranged at intersections of the first lines and the second lines and each formed by connecting a rectification element and a variable-resistance element in series. The rectification element includes a first semiconductor region having an n-type and a second semiconductor region having a p-type. At least a portion of the first semiconductor region is made of a silicon-carbide mixture (Si | 03-24-2011 |
| 20110068316 | NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide. | 03-24-2011 |
| 20110068317 | Phase change memory devices, methods of manufacturing and methods of operating the same - A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer. | 03-24-2011 |
| 20110073828 | MEMRISTOR AMORPHOUS METAL ALLOY ELECTRODES - A nanoscale switching device comprises at least two electrodes, each of a nanoscale width; and an active region disposed between and in electrical contact with the electrodes, the active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field, wherein at least one of the electrodes comprises an amorphous conductive material. | 03-31-2011 |
| 20110073829 | PHASE CHANGE MEMORY DEVICE HAVING A HEATER WITH A TEMPERATURE DEPENDENT RESISTIVITY, METHOD OF MANUFACTURING THE SAME, AND CIRCUIT OF THE SAME - A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity. | 03-31-2011 |
| 20110073830 | PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change random access memory includes a semiconductor substrate, a switching device pattern formed on the semiconductor substrate, a bottom electrode contact pattern formed on the switching device pattern, a phase change layer pattern formed on the bottom electrode contact pattern, and an insulating layer disposed at a portion of an contact surface between the bottom electrode contact pattern and the phase change layer pattern. | 03-31-2011 |
| 20110073831 | FERROELECTRIC POLYMER MEMORY DEVICE INCLUDING POLYMER ELECTRODES AND METHOD OF FABRICATING SAME - A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first conductive polymer layer disposed on the first electrode layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer. The module further includes a second set of layers including: an ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the ILD layer of the second set of layers; and a second electrode layer disposed on the second conductive polymer layer. The first conductive polymer layer and the second conductive polymer layer cover the electrode layers to provide a reaction and/or diffusion barrier between the electrode layers and the ferroelectric polymer layer. | 03-31-2011 |
| 20110073832 | PHASE-CHANGE MEMORY DEVICE - A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon. | 03-31-2011 |
| 20110073833 | RESISTANCE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes. | 03-31-2011 |
| 20110084248 | CROSS POINT MEMORY ARRAY DEVICES - Cross point memory arrays with CBRAM and RRAM stacks are presented. A cross point memory array includes a first group of substantially parallel conductive lines and a second group of substantially parallel conductive lines, oriented substantially perpendicular to the first group of substantially parallel conductive lines. An array of memory stack is located at the intersections of the first group of substantially parallel conductive lines and the second group of substantially parallel conductive lines, wherein each memory stack comprises a conductive bridge memory element in series with a resistive-switching memory element. | 04-14-2011 |
| 20110089393 | Memory and Method of Fabricating the Same - A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal element, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance. | 04-21-2011 |
| 20110089394 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film over a semiconductor substrate. The first insulating film includes a first opening, a first electrode in the first opening, and a second insulating film over the first insulating film. The second insulating film includes a second opening that is positioned over the first electrode. The second opening includes a first conductive film. The first conductive film is electrically coupled to the first electrode. The first conductive film includes a top surface that is lower than a top surface of the second opening. The second opening includes a phase change material film. The phase change material film includes first and second portions. The first portion is surrounded by the first electrode and the first conductive film. | 04-21-2011 |
| 20110089395 | STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode. | 04-21-2011 |
| 20110095259 | RESISTANCE CHANGING DEVICE AND METHOD FOR FABRICATING THE SAME - A resistance changing device includes a resistive layer of a hetero structure interposed between a lower electrode and an upper electrode, and including a plurality of resistive material layers, each having a different resistivity, stacked therein, wherein resistivities of the resistive material layers decrease from the lower electrode toward the upper electrode. Since the resistive layer has a hetero structure in which a plurality of resistive material layers, each having a different resistivity, are stacked in such a manner that the resistivity decreases as it goes from the lower electrode to the upper electrode, it is possible to improve the distributions of the set/reset voltage and the set/reset current, while reducing a reset current of a resistance changing device at the same time. | 04-28-2011 |
| 20110108793 | JUNCTIONS COMPRISING MOLECULAR BILAYERS FOR THE USE IN ELECTRONIC DEVICES - The present invention relates to asymmetric molecular bilayers for the use in the junctions of electronic devices, such as crossbar junctions, comprising the general structure E | 05-12-2011 |
| 20110108794 | Phase Changeable Memory Devices - Phase changeable memory devices are provided. A phase changeable memory device may include two first electrodes spaced apart from each other. The phase changeable memory device may also include a common phase changeable material contacting a sidewall of each of the two first electrodes. The phase changeable memory device may further include a second electrode overlying the common phase changeable material. A top surface of each of the two first electrodes may not physically contact the phase changeable material. | 05-12-2011 |
| 20110114912 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device ( | 05-19-2011 |
| 20110121251 | SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material. | 05-26-2011 |
| 20110121252 | SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material. | 05-26-2011 |
| 20110121253 | MEMORY DEVICE - A memory device is described. The memory device comprises a bottom electrode, a first pair of spacers, a second pair of spacers and a phase-change element. The bottom electrode has a lower horizontal portion and a vertical portion, and the vertical portion has a top surface and a side. The first pair of spacers covers the side of the vertical portion. The second pair of spacers covers a first portion of the top surface of the vertical portion. The phase-change element is contacted a second portion of the top surface of the vertical portion. | 05-26-2011 |
| 20110121254 | MEMORY DEVICE AND CBRAM MEMORY WITH IMPROVED RELIABILITY - A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m | 05-26-2011 |
| 20110127486 | Phase-change memory device, phase-change channel transistor and memory cell array - A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory layer with an insulating film interposed therebetween, wherein the memory layer includes at least a first layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature and a second layer formed from a resistive material, and wherein the resistance value of the second layer is smaller than the resistance value of the first layer in the amorphous phase, but is larger than the resistance value of the first layer in the crystalline phase. | 06-02-2011 |
| 20110133151 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided. | 06-09-2011 |
| 20110133152 | RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer. | 06-09-2011 |
| 20110140067 | RESISTANCE SWITCHING MEMORY - A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode. | 06-16-2011 |
| 20110140068 | RESISTANCE-CHANGE MEMORY CELL ARRAY - According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resitstance films. | 06-16-2011 |
| 20110147695 | FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS - In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed. | 06-23-2011 |
| 20110147696 | Resistive random access memory devices and resistive random access memory arrays having the same - A resistive random access memory (RRAM) devices and resistive random access memory (RRAM) arrays are provided, the RRAM devices include a first electrode layer, a variable resistance material layer formed of an oxide of a metallic material having a plurality of oxidation states, an intermediate electrode layer on the variable resistance material layer and formed of a conductive material having a lower reactivity with oxygen than the metallic material, and a second electrode layer on the intermediate electrode layer. The RRAM arrays include at least one of the aforementioned RRAM devices. | 06-23-2011 |
| 20110155991 | RESISTIVE MEMORY DEVICE AND FABRICATING METHOD THEREOF - A resistive memory device and a fabricating method thereof are introduced herein. In resistive memory device, a plurality of bottom electrodes is disposed in active region of a substrate. Each of the bottom electrodes is disposed to correspond to each of the conductive channels; a patterned resistance switching material layer and the patterned top electrode layer are sequentially stacked on the bottom electrodes. An air dielectric layer exists between the patterned resistance switching material layer and the bottom electrodes. A plurality of patterned interconnections is disposed on the patterned top electrode. | 06-30-2011 |
| 20110155992 | PHASE-SEPARATION TYPE PHASE-CHANGE MEMORY - A eutectic memory includes a eutectic memory material layer, a top and a bottom electrodes, or a left and a right electrodes. Materials of the eutectic memory layer are represented by M | 06-30-2011 |
| 20110155993 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof are presented. A phase change memory device includes a substrate structure. A first electrode is disposed on the substrate structure. A hollowed-cone hydrogen silsesquioxane (HSQ) structure is formed on the first electrode. A multi-level cell phase change memory structure is disposed on the hollowed-cone HSQ structure. A second electrode is disposed on the multi-level cell phase change memory structure. | 06-30-2011 |
| 20110168967 | ELECTRONIC ELEMENT AND ELECTROCONDUCTIVITY CONTROL METHOD - An electronic device | 07-14-2011 |
| 20110175050 | Metal Oxide Resistance Based Semiconductor Memory Device With High Work Function Electrode - Various aspect are directed to a memory device or memory cell with a metal-oxide memory element arranged in electrical series along a current path between at least a first electrode, a metal-oxide memory element adjacent to the first electrode, and a second electrode. The first electrode comprises an electrode material having a first work function. The metal-oxide memory element comprises a metal-oxide material having a second work function. The first work function is greater than the second work function. Thermionic emission characterizes the current through this memory. | 07-21-2011 |
| 20110175051 | RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode. | 07-21-2011 |
| 20110175052 | RESISTANCE-VARIABLE MEMORY DEVICE INCLUDING CARBIDE-BASED SOLID ELECTROLYTE MEMBRANE AND MANUFACTURING METHOD THEREOF - Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane. | 07-21-2011 |
| 20110180775 | PROGRAMMABLE METALLIZATION CELL WITH ION BUFFER LAYER - A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer. | 07-28-2011 |
| 20110186801 | Nanoscale Switching Device - A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical held. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes. | 08-04-2011 |
| 20110186802 | MEMORY DEVICE AND A SEMICONDUCTOR DEVICE - The present invention provides a memory device and a semiconductor device which have high reliability for writing at low cost. Furthermore, the present invention provides a memory device and a semiconductor device having a non-volatile memory element in which data can be additionally written and which can prevent forgery due to rewriting and the like. The memory element includes a first conductive layer, a second conductive layer, and an organic compound layer, which is formed between the first conductive layer and the second conductive layer, and which has a photosensitized oxidation reduction agent which can be an excited state by recombination energy of electrons and holes and a substance which can react with the photosensitized oxidation reduction agent. | 08-04-2011 |
| 20110193049 | MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen. | 08-11-2011 |
| 20110193050 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film. | 08-11-2011 |
| 20110193051 | RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are resistance memory devices and methods of forming the same. The resistance memory devices include a first electrode and a second electrode on a substrate, a transition metal oxide layer interposed between the first electrode and the second electrode, an electrolyte layer interposed between the second electrode and the transition metal oxide layer, and conductive bridges having one end that is electrically connected to the second electrode on the electrolyte. | 08-11-2011 |
| 20110198556 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device in accordance with an embodiment comprises a lower electrode layer, a variable resistance layer, and an upper electrode layer. The lower electrode layer is provided over a substrate. The variable resistance layer is provided on the lower electrode layer and is configured such that an electrical resistance of the variable resistance layer can be changed. The upper electrode layer is provided on the variable resistance layer. The variable resistance layer comprises a carbon nanostructure and metal atoms. The carbon nanostructure is stacked to have a plurality of gaps. The metal atoms are diffused into the gaps. | 08-18-2011 |
| 20110198557 | METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si. | 08-18-2011 |
| 20110204311 | NON-VOLATILE RESISTIVE-SWITCHING MEMORIES FORMED USING ANODIZATION - Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element. | 08-25-2011 |
| 20110204312 | CONFINEMENT TECHNIQUES FOR NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Confirment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode. | 08-25-2011 |
| 20110204313 | Electrode Diffusions in Two-Terminal Non-Volatile Memory Devices - A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded. | 08-25-2011 |
| 20110204314 | RESISTIVE MEMORY CELLS AND DEVICES HAVING ASYMMETRICAL CONTACTS - A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide. | 08-25-2011 |
| 20110204315 | Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes, and Related Methods and Processing Systems - A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes. | 08-25-2011 |
| 20110220860 | Bipolar memory cells, memory devices including the same and methods of manufacturing and operating the same - Bipolar memory cells and a memory device including the same are provided, the bipolar memory cells include two bipolar memory layers having opposite programming directions. The two bipolar memory layers may be connected to each other via an intermediate electrode interposed therebetween. The two bipolar memory layers may have the same structure or opposite structures. | 09-15-2011 |
| 20110220861 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires ( | 09-15-2011 |
| 20110220862 | RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE - A resistance variable element ( | 09-15-2011 |
| 20110220863 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage. | 09-15-2011 |
| 20110227023 | BACKEND OF LINE (BEOL) COMPATIBLE HIGH CURRENT DENSITY ACCESS DEVICE FOR HIGH DENSITY ARRAYS OF ELECTRONIC COMPONENTS - A device is disclosed having a M | 09-22-2011 |
| 20110227024 | RESISTANCE-SWITCHING MEMORY CELL WITH HEAVILY DOPED METAL OXIDE LAYER - A non-volatile resistance-switching memory element includes a resistance-switching element formed from a metal oxide layer having a dopant which is provided at a relatively high concentration such as 10% or greater. Further, the dopant is a cation having a relatively large ionic radius such as 70 picometers or greater, such as Magnesium, Chromium, Calcium, Scandium or Yttrium. A cubic fluorite phase lattice may be formed in the metal oxide even at room temperature so that switching power may be reduced. The memory element may be pillar-shaped, extending between first and second electrodes and being in series with a steering element such as a diode. The metal oxide layer may be deposited at the same time as the dopant. Or, using atomic layer deposition, an oxide of a first metal can be deposited, followed by an oxide of a second metal, followed by annealing to cause intermixing, in repeated cycles. | 09-22-2011 |
| 20110227025 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other. | 09-22-2011 |
| 20110227026 | NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME - Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air brake. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide. Sub-plantation may be used to create a titanium region between two metal oxide regions. | 09-22-2011 |
| 20110227027 | Memory Device and Method of Making Same - A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area. | 09-22-2011 |
| 20110227028 | BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS - In a first aspect, an MIM stack is provided that includes (1) a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided. | 09-22-2011 |
| 20110227029 | MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME - A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer. | 09-22-2011 |
| 20110227030 | Memristor Having a Triangular Shaped Electrode - A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode. | 09-22-2011 |
| 20110233506 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a resistance change portion and a select element. The resistance change portion is provided between the first electrode and the second electrode and configured to transition between a first resistance state and a second resistance state. The select element is provided between the resistance change portion and the first electrode and has a p-layer including a p-type semiconductor, an i-layer including an intrinsic semiconductor, and an n-layer including an n-type semiconductor. The select element contains an impurity having a smaller bandgap energy than the intrinsic semiconductor, and a concentration peak of the impurity in the i-layer is placed in a center portion of layer thickness of the i-layer. | 09-29-2011 |
| 20110233507 | RESISTANCE CHANGE MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer. | 09-29-2011 |
| 20110233508 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes an electrode and a memory layer. The memory layer is connected to the electrode, and the memory layer has a resistance configured to change due to a current flowing from the electrode. The electrode includes a first layer and a second layer. The first layer includes a metallic element and a first non-metallic element, and the first non-metallic element has a first valence n. The second layer is provided between the first layer and the memory layer, and the second layer includes the metallic element and a second non-metallic element. The second non-metallic element has a second valence (n+1) greater than the first valence n by 1. | 09-29-2011 |
| 20110233509 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device including a nonvolatile memory layer is provided. The nonvolatile memory layer is formed of a metal oxide film that includes an element with a higher electronegativity compared with a metal element forming the metal oxide film in the metal oxide film at a concentration of 25 at % or less. | 09-29-2011 |
| 20110233510 | NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element of the present invention comprises a first electrode ( | 09-29-2011 |
| 20110233511 | NONVOLATILE MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A nonvolatile memory element ( | 09-29-2011 |
| 20110240948 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element. | 10-06-2011 |
| 20110240949 | INFORMATION RECORDING DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles. | 10-06-2011 |
| 20110240950 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 10-06-2011 |
| 20110248236 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a lower electrode, a variable resistance layer disposed over the lower electrode, the variable resistance layer is included a reactive metal layer being interposed between a plurality of oxide resistive layers and an upper electrode disposed over the variable resistance layer. | 10-13-2011 |
| 20110253966 | IONIC-MODULATED DOPANT PROFILE CONTROL IN NANOSCALE SWITCHING DEVICES - A nanoscale switching device is provided, comprising: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having at least one non-conducting layer comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field; and a source layer interposed between the first electrode and the second electrode and comprising a highly reactive and highly mobile ionic species that reacts with a component in the switching material to create dopants that are capable of drifting through the non-conducting layer under an electric field, thereby controlling dopant profile by ionic modulation. A crossbar array comprising a plurality of the nanoscale switching devices is also provided, along with a process for making at least one nanoscale switching device. | 10-20-2011 |
| 20110253967 | SWITCHING DEVICE, DRIVE AND MANUFACTURING METHODS FOR THE SAME, INTEGRATED CIRCUIT DEVICE AND MEMORY DEVICE - Provided is a switching device including ion conducting part | 10-20-2011 |
| 20110260134 | Thermally Stable Nanoscale Switching Device - A nanoscale switching device provides enhanced thermal stability and endurance to switching cycles. The switching device has an active region disposed between electrodes and containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field. At least one of the electrodes is formed of conductive material having a melting point greater than 1800° C. | 10-27-2011 |
| 20110266512 | NON-VOLATILE RESISTANCE-SWITCHING THIN FILM DEVICES - Disclosed herein is a resistive switching device having an amorphous layer comprised of an insulating silicon-containing material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating silicon-containing material and a conducting material comprising between 5 and 40 percent by molar percentage of the composition is disclosed herein as well. Also disclosed herein are methods for switching the resistance of an amorphous material. | 11-03-2011 |
| 20110266513 | Superconductor Memristor Devices - Various embodiments of the present invention are directed to electronic devices, which combine reconfigurable diode rectifying states with nonvolatile memristive switching. In one aspect, an electronic device ( | 11-03-2011 |
| 20110266514 | MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided. | 11-03-2011 |
| 20110272660 | RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material. | 11-10-2011 |
| 20110272661 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a resistive memory device and a method of fabricating the same. The resistive memory device comprises an electron channel layer formed by means of a swelling process and an annealing process. Thus, conductive nanoparticles are uniformly dispersed in the electron channel layer to improve reliability of the resistive memory device. According to the method, an electron channel layer is formed by means of a printing process, a swelling process, and an annealing process. Thus, fabrication time is reduced. | 11-10-2011 |
| 20110272662 | Forced Ion Migration for Chalcogenide Phase Change Memory Device - Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge | 11-10-2011 |
| 20110272663 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions. | 11-10-2011 |
| 20110272664 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a semiconductor substrate; a multilevel wiring layer structure on the semiconductor substrate; and a variable resistance element in the multilevel wiring layer structure, wherein the variable resistance element comprises a variable resistance element film whose resistance changes between a top electrode and a bottom electrode, wherein the multilevel wiring layer structure comprises at least a wiring electrically connected to the bottom electrode and a plug electrically connected to the top electrode, and wherein the wiring also serves as the bottom electrode. | 11-10-2011 |
| 20110278531 | Forming Electrodes for Chalcogenide Containing Devices - The electrode of a phase change memory may be formed with a mixture of metal and a non-metal, the electrode having less nitrogen atoms than metal atoms. Thus, in some embodiments, at least a portion of the electrode has less nitrogen than would be the case in a metal nitride. The mixture can include metal and nitrogen or metal and silicon, as two examples. Such material may have good adherence to chalcogenide with lower reactivity than may be the case with metal nitrides. | 11-17-2011 |
| 20110284815 | PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS - A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region. | 11-24-2011 |
| 20110284816 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, NONVOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element comprises a first electrode ( | 11-24-2011 |
| 20110291064 | RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode. | 12-01-2011 |
| 20110291065 | PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS - Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode, wherein forming the dielectric stack structure includes creating a second region between a first region and a third region of the dielectric stack structure, the second region having a thermal conductivity different than a thermal conductivity of the first region and different than a thermal conductivity of the third region of the dielectric stack. One or more embodiments include forming a via through the first, second, and third regions of the dielectric stack structure, depositing a phase change material in the via, and forming a second electrode on the phase change material. | 12-01-2011 |
| 20110291066 | Nonvolatile Memory Devices Having Cells with Oxygen Diffusion Barrier Layers Therein and Methods of Manufacturing the Same - A nonvolatile memory cell includes first and second electrodes and a data storage layer extending between the first and second electrodes. An oxygen diffusion barrier layer is provided, which extends between the data storage layer and the first electrode. An oxygen gettering layer is also provided, which extends between the oxygen diffusion barrier layer and the data storage layer. The oxygen diffusion barrier layer includes aluminum oxide, the oxygen gettering layer includes titanium, the data storage layer includes a metal oxide, such as magnesium oxide, and at least one of the first and second electrodes includes a material selected from a group consisting of tungsten, polysilicon, aluminum, titanium nitride silicide and conductive nitrides. | 12-01-2011 |
| 20110291067 | Threshold Device For A Memory Array - A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations. | 12-01-2011 |
| 20110297911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser. | 12-08-2011 |
| 20110303889 | VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit. | 12-15-2011 |
| 20110309319 | HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS - Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material. | 12-22-2011 |
| 20110309320 | METHOD FOR ACTIVE PINCH OFF OF AN OVONIC UNIFIED MEMORY ELEMENT - A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly. | 12-22-2011 |
| 20110315945 | Method of manufacturing semiconductor memory device - A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode. | 12-29-2011 |
| 20110315946 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen. | 12-29-2011 |
| 20110315947 | PROGRAMMABLE METALLIZATION CELL STRUCTURE INCLUDING AN INTEGRATED DIODE, DEVICE INCLUDING THE STRUCTURE, AND METHOD OF FORMING SAME - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 12-29-2011 |
| 20120001144 | RESISTIVE RAM DEVICES AND METHODS - The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element. | 01-05-2012 |
| 20120001145 | AVOIDING DEGRADATION OF CHALCOGENIDE MATERIAL DURING DEFINITION OF MULTILAYER STACK STRUCTURE - A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer ( | 01-05-2012 |
| 20120001146 | NANOSCALE METAL OXIDE RESISTIVE SWITCHING ELEMENT - A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device. | 01-05-2012 |
| 20120001147 | Non-Volatile Resistive Oxide Memory Cells, Non-Volatile Resistive Oxide Memory Arrays, And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells And Memory Arrays - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated. | 01-05-2012 |
| 20120001148 | STRESS-ENGINEERED RESISTANCE-CHANGE MEMORY DEVICE - A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode | 01-05-2012 |
| 20120007035 | Intrinsic Programming Current Control for a RRAM - A resistive switching device. The device includes a substrate and a first dielectric material overlying a surface region of the substrate. The device includes a first electrode overlying the first dielectric material and an optional buffer layer overlying the first electrode. The device includes a second electrode structure. The second electrode includes at least a silver material. In a specific embodiment, a switching material overlies the optional buffer layer and disposed between the first electrode and the second electrode. The switching material comprises an amorphous silicon material in a specific embodiment. The amorphous silicon material is characterized by a plurality of defect sites and a defect density. The defect density is configured to intrinsically control programming current for the device. | 01-12-2012 |
| 20120007036 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. | 01-12-2012 |
| 20120012806 | IMPROVED ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD - This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying at lease the top surface region of the switching element such that the conductive material is in direct contact with the switching element. The side wall spacer reduces a contact area for the switching element and the conductive material and thus a reduced active device area for the switching device. In a specific embodiment, the reduced area provides for an increase in device ON/OFF current ratio. | 01-19-2012 |
| 20120012807 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line. | 01-19-2012 |
| 20120012808 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb | 01-19-2012 |
| 20120012809 | Switchable Junction with Intrinsic Diodes with Different Switching Threshold - A switchable junction ( | 01-19-2012 |
| 20120012810 | OPTOELECTRONIC LIGHT EXPOSURE MEMORY - An optoelectronic memory cell has a transparent top electrode, a photoactive layer, a latching layer, and a bottom electrode. The photoactive layer absorbs photons transmitted through the top electrode and generates charge carriers. During light exposure, the latching layer changes its resistance under an applied electric field in response to the generation of charge carriers in the photoactive layer. | 01-19-2012 |
| 20120018695 | Non-Volatile Memory Element And Memory Device Including The Same - Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level. | 01-26-2012 |
| 20120025163 | NON-VOLATILE SEMICONDUCTOR DEVICE - A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer. | 02-02-2012 |
| 20120032132 | Nonvolatile Memory Elements And Memory Devices Including The Same - Nonvolatile memory elements may include a first electrode, a second electrode, a first buffer layer, a second buffer layer and a memory layer. The memory layer may be between the first and second electrodes. The first butter layer may be between the memory layer and the first electrode. The second buffer layer may be between the memory layer and the second electrode. The memory layer may be a multi-layer structure including a first material layer and a second material layer. The first material layer may include a first metal oxide which is of the same group as, or a different group from, a second metal oxide included in the second material layer. | 02-09-2012 |
| 20120032133 | SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS - This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution. | 02-09-2012 |
| 20120032134 | Memristive Junction with Intrinsic Rectifier - A memristive junction ( | 02-09-2012 |
| 20120032135 | Phase-Change Memory Units and Phase-Change Memory Devices Using the Same - A phase-change material layer is formed on the lower electrode using a chalcogenide compound doped with carbon, or carbon and nitrogen. A phase-change material layer is obtained by doping a stabilizing metal into the preliminary phase-change material layer. An upper electrode is formed on the phase-change material layer. Since the phase-change material layer may have improved electrical characteristics, stability of phase transition and thermal stability, the phase-change memory unit may have reduced set resistance, enhanced durability, improved reliability, increased sensing margin, reduced driving current, etc. | 02-09-2012 |
| 20120037878 | ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure. | 02-16-2012 |
| 20120043518 | VARIABLE RESISTANCE MEMORY ELEMENT AND FABRICATION METHODS - An electronic device comprises a variable resistance memory element on a substrate. The variable resistance memory element comprises (i) an amorphous carbon layer comprising a hydrogen content of at least about 30 atomic percent, and a maximum leakage current of less than about 1×10 | 02-23-2012 |
| 20120043519 | DEVICE SWITCHING USING LAYERED DEVICE STRUCTURE - A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode. | 02-23-2012 |
| 20120043520 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction. | 02-23-2012 |
| 20120043521 | Conductive Metal Oxide Structures In Non Volatile Re Writable Memory Devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 02-23-2012 |
| 20120056148 | Semiconductor device - A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film. | 03-08-2012 |
| 20120068143 | Memory Arrays And Methods Of Forming Memory Cells - Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide. | 03-22-2012 |
| 20120068144 | RESISTANCE RANDOM ACCESS MEMORY - According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other. | 03-22-2012 |
| 20120068145 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first interconnect, an insulating layer, a needle-like metal oxide, and a second interconnect. The insulating layer is provided on the first interconnect. The needle-like metal oxide pierces the insulating layer in a vertical direction. The second interconnect is provided on the insulating layer. | 03-22-2012 |
| 20120068146 | MEMORY ELEMENT AND MEMORY DEVICE - There are provided a memory element and a memory device with a smaller range of element-to-element variation of electrical characteristics. The memory element includes a first electrode, a memory layer, and a second layer in this order. The memory layer includes a resistance change layer including a plurality of layers varying in diffusion coefficient of mobile atoms, and an ion source layer disposed between the resistance change layer and the second electrode. | 03-22-2012 |
| 20120068147 | PHASE CHANGE MEMORY DEVICE AND FABRICATION THEREOF - A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer. | 03-22-2012 |
| 20120068148 | NONVOLATILE MEMORY ELEMENT AND FABRICATION METHOD FOR NONVOLATILE MEMORY ELEMENT - A variable resistance nonvolatile memory element capable of suppressing a variation in resistance values is provided. A nonvolatile memory element according to the present invention includes: a silicon substrate ( | 03-22-2012 |
| 20120074372 | MEMRISTORS WITH AN ELECTRODE METAL RESERVOIR FOR DOPANTS - A memristor includes a first electrode of a nanoscale width; a second electrode of a nanoscale width; and an active region disposed between the first and second electrodes. The active region has a both a non-conducting portion and a source of dopants portion induced by electric field. The non-conducting portion comprises an electronically semiconducting or nominally insulating material and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field. The non-conducting portion is in contact with the first electrode and the source of dopants portion is in contact with the second electrode. The second electrode comprises a metal reservoir for the dopants. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided. | 03-29-2012 |
| 20120074373 | Electronic Devices, Memory Devices and Memory Arrays - Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells. | 03-29-2012 |
| 20120074374 | CONDUCTIVE PATH IN SWITCHING MATERIAL IN A RESISTIVE RANDOM ACCESS MEMORY DEVICE AND CONTROL - A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material. | 03-29-2012 |
| 20120074375 | VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE - The variable resistance nonvolatile storage device includes a memory cell ( | 03-29-2012 |
| 20120074376 | NONVOLATILE MEMORY ELEMENTS WITH METAL DEFICIENT RESISTIVE SWITCHING METAL OXIDES - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal. | 03-29-2012 |
| 20120074377 | SEMICONDUCTOR MEMORY - Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer. | 03-29-2012 |
| 20120091418 | BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes (1) a bipolar storage element formed from a metal-insulator-metal (MIM) stack including (a) a first conductive layer; (b) a reversible resistivity switching (RRS) layer formed above the first conductive layer; (c) a metal/metal oxide layer stack formed above the first conductive layer; and (d) a second conductive layer formed above the RRS layer and the metal/metal oxide layer stack; and (2) a steering element coupled to the storage element. Numerous other aspects are provided. | 04-19-2012 |
| 20120091419 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided. | 04-19-2012 |
| 20120091420 | NONVOLATILE RESISTANCE CHANGE DEVICE - According to one embodiment a first variable resistance layer which is arranged between a second electrode and a first electrode and in which a first conductive filament is capable of growing based on metal supplied from the second electrode, and an n-th variable resistance layer which is arranged between an n-th electrode and an (n+1)-th electrode and in which an n-th conductive filament whose growth rate is different from the first conductive filament is capable of growing based on metal supplied from the (n+1)-th electrode are included, a configuration in which a plurality of conductive filaments is electrically connected in series between the first electrode layer and the (n+1)-th electrode layer is included, and a resistance is changed in a stepwise manner. | 04-19-2012 |
| 20120091421 | Nanostructure quick-switch memristor and method of manufacturing the same - A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost. | 04-19-2012 |
| 20120091422 | Semiconductor Memory Devices Having Variable Resistor And Methods Of Fabricating The Same - According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening foamed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer. | 04-19-2012 |
| 20120091423 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device is disclosed, in which a first electrode, a first material layer having a positive Peltier coefficient, an information storage layer, a second material layer having a negative Peltier coefficient, and a second electrode are laminated. | 04-19-2012 |
| 20120091424 | NON-VOLATILE MEMORY DEVICE AND METHODS FOR MANUFACTURING THE SAME - A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification. | 04-19-2012 |
| 20120091425 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device ( | 04-19-2012 |
| 20120091426 | RESISTANCE-VARIABLE ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order. | 04-19-2012 |
| 20120097915 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate ( | 04-26-2012 |
| 20120097916 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property. | 04-26-2012 |
| 20120104345 | MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes. | 05-03-2012 |
| 20120104346 | SEMICONDUCTOR DEVICE FOR PROVIDING HEAT MANAGEMENT - A semiconductor device for providing heat management may include a first electrode with low metal thermal conductivity and a second electrode with low metal thermal conductivity. A metal oxide structure which includes a transition metal oxide (TMO) may be electrically coupled to the first electrode and second electrode and the metal oxide structure may be disposed between the first electrode and second electrode. An electrically insulating sheath with low thermal conductivity may surround the metal oxide structure. | 05-03-2012 |
| 20120104347 | METHOD OF FORMING A CHALCOGENIDE MATERIAL, METHODS OF FORMING A RESISTIVE RANDOM ACCESS MEMORY DEVICE INCLUDING A CHALCOGENIDE MATERIAL, AND RANDOM ACCESS MEMORY DEVICES INCLUDING A CHALCOGENIDE MATERIAL - A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method of forming a resistive random access memory device is also disclosed. The method comprises forming a plurality of memory cells wherein each cell of the plurality of memory cells is formed by forming a metal on a first electrode, forming a chalcogenide material on the metal by a gas cluster ion beam process, and forming a second electrode on the chalcogenide material. A method of forming another resistive random access memory device and a random access memory device including the chalcogenide material are also disclosed. | 05-03-2012 |
| 20120104348 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 05-03-2012 |
| 20120104349 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal. | 05-03-2012 |
| 20120104350 | VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A step of forming, on a substrate ( | 05-03-2012 |
| 20120104351 | NON-VOLATILE MEMORY CELL, NON-VOLATILE MEMORY CELL ARRAY, AND METHOD OF MANUFACTURING THE SAME - A stacking structure in which a stacked body ( | 05-03-2012 |
| 20120112154 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 05-10-2012 |
| 20120119181 | SEMICONDUCTOR DEVICE INCLUDING BUFFER ELECTRODE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern. | 05-17-2012 |
| 20120126196 | Upwardly Tapering Heaters for Phase Change Memories - A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments. | 05-24-2012 |
| 20120132881 | CROSS-POINT MEMORY WITH SELF-DEFINED MEMORY ELEMENTS - Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described. | 05-31-2012 |
| 20120132882 | Transparent Memory for Transparent Electronic Device - The present invention relates to a transparent memory for a transparent electronic device. The transparent memory includes: a lower transparent electrode layer that is sequentially formed on a transparent substrate, and a data storage region and an upper transparent layer which are made of at least one transparent resistance-variable material layer. The transparent resistance-variable material layer has switching characteristics as a result of the resistance variance caused by the application of a certain voltage between the lower and upper transparent electrode layers. An optical band gap of the transparent resistance-variable material layer is 3 eV or more, and transmittivity of the material layer for visible rays is 80% or more. The invention provides transparent and resistance-variable memory that: has very high transparency and switching characteristics depending on resistance variation at a low switching voltage, and can maintain the switching characteristics thereof after a long time elapses. | 05-31-2012 |
| 20120132883 | Resistive Switching Memory Device - A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes. | 05-31-2012 |
| 20120132884 | SELF-ALIGNED, PLANAR PHASE CHANGE MEMORY ELEMENTS AND DEVICES, SYSTEMS EMPLOYING THE SAME AND METHODS OF FORMING THE SAME - Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane. | 05-31-2012 |
| 20120138884 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH PLANARIZED SILVER ELECTRODE - Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact. | 06-07-2012 |
| 20120145985 | Variable Resistance Memory Devices And Methods Of Fabricating The Same - Variable resistance memory devices may include a semiconductor layer including first, second, third doped regions, a variable resistance pattern on the semiconductor layer, a lower electrode between the semiconductor layer and the variable resistance pattern, and a first metal silicide pattern in contact with the semiconductor layer. The third doped region may be spaced apart from the first metal silicide pattern, the first doped region may be spaced apart from the third doped region, and a second doped region may be interposed between the first and third doped regions and be in contact with the first metal silicide pattern. The first doped region may have the same conductivity type as the third doped region and a different conductivity type from the second doped region. | 06-14-2012 |
| 20120145986 | SEMICONDUCTOR MEMORY DEVICE - A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio. | 06-14-2012 |
| 20120153249 | Composition of Memory Cell With Resistance-Switching Layers - A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride. | 06-21-2012 |
| 20120161094 | 3D SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density. | 06-28-2012 |
| 20120161095 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug ( | 06-28-2012 |
| 20120168705 | Bipolar Switching Memory Cell With Built-in "On" State Rectifying Current-Voltage Characteristics - A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed. | 07-05-2012 |
| 20120168706 | RESISTANCE RANDOM ACCESS MEMORY - The present disclosure relates to a resistance random access memory comprising a first electrode, a thin film layer formed on the first electrode and including a resistance switching layer and a switching layer bonded to each other, and a second electrode formed on the thin film layer, and relates to a method of manufacturing the same. | 07-05-2012 |
| 20120168707 | CARBON NANO-FILM REVERSIBLE RESISTANCE-SWITCHABLE ELEMENTS AND METHODS OF FORMING THE SAME - Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided. | 07-05-2012 |
| 20120168708 | Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods - Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. | 07-05-2012 |
| 20120168709 | SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material. | 07-05-2012 |
| 20120181500 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor memory device comprises a plurality of memory cell holes ( | 07-19-2012 |
| 20120187362 | Phase Change Memory Cell Structure - A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface. | 07-26-2012 |
| 20120193599 | PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings. | 08-02-2012 |
| 20120193600 | VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, METHOD OF MANUFACTURING THE SAME, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - A variable resistance nonvolatile memory element ( | 08-02-2012 |
| 20120199806 | POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM - A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region. | 08-09-2012 |
| 20120205608 | NONVOLATILE VARIABLE RESISTANCE DEVICE AND METHOD OF MANUFACTURING THE NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer. | 08-16-2012 |
| 20120205609 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer. | 08-16-2012 |
| 20120205610 | RESISTIVE SWITCHING MEMORY ELEMENT INCLUDING DOPED SILICON ELECTRODE - A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa. | 08-16-2012 |
| 20120205611 | HETEROJUNCTION OXIDE NON-VOLATILE MEMORY DEVICE - A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer | 08-16-2012 |
| 20120211719 | NONVOLATILE VARIABLE RESISTIVE DEVICE - According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode. | 08-23-2012 |
| 20120211720 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. | 08-23-2012 |
| 20120211721 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a stopper film on the memory cell layer. The method of manufacturing a semiconductor storage device also includes: etching the stopper film, the memory cell layer, and the first wiring layer; polishing an interlayer insulating film to the stopper film after burying the stopper film, the memory cell layer, and the first wiring layer with the interlayer insulating film; performing a nitridation process to the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film, respectively; and forming a second wiring layer on the adjustment film, the second wiring layer being electrically connected to the adjustment film. | 08-23-2012 |
| 20120211722 | THREE-DIMENSIONAL MEMORY ARRAY STACKING STRUCTURE - A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column. | 08-23-2012 |
| 20120217463 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - A method of forming a semiconductor memory device comprises a step of forming an electrode pattern extending in a first direction on a substrate, a step of forming a pair of mask patterns on the electrode pattern, the mask patterns extending a second direction perpendicular to the first direction, a step of partially etching the electrode pattern using the pair of mask patterns as etch masks to form a first recessed region in the electrode pattern, a step of forming a pair of sidewall spacers on either inner sidewalls of the first recessed region, a step of etching the electrode pattern of the first recessed region using the pair of sidewall spacers as etch masks to form a heating electrode contacting the pair of sidewall spacers, and a step of forming a variable resistive pattern on the heating electrode. | 08-30-2012 |
| 20120217464 | NONVOLATILE STORAGE DEVICE - A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode. | 08-30-2012 |
| 20120217465 | NON-VOLATILE PROGRAMMABLE DEVICE INCLUDING PHASE CHANGE LAYER AND FABRICATING METHOD THEREOF - Provided is a non-volatile programmable device including a first terminal, a first threshold switching layer connected to part of the first terminal, a phase change layer connected to the first threshold switching layer, a second threshold switching layer connected to the phase change layer, a second terminal connected to the second threshold switching layer, and third and fourth terminals respectively connected to a side portion of the phase change layer and the other side portion opposite to the side portion of the phase change layer. | 08-30-2012 |
| 20120223284 | VARIABLE RESISTIVE ELEMENT, METHOD FOR PRODUCING THE SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING THE VARIABLE RESISTIVE ELEMENT - A variable resistive element configured to reduce a forming voltage while reducing a variation in forming voltage among elements, a method for producing it, and a highly integrated nonvolatile semiconductor memory device provided with the variable resistive element are provided. The variable resistive element includes a resistance change layer (first metal oxide film) and a control layer (second metal oxide film) having contact with a first electrode sandwiched between the first electrode and a second electrode. The control layer includes a metal oxide film having a low work function (4.5 eV or less) and capable of extracting oxygen from the resistance change layer. The first electrode includes a metal having a low work function similar to the above metal, and a material having oxide formation free energy higher than that of an element included in the control layer, to prevent oxygen from being thermally diffused from the control layer. | 09-06-2012 |
| 20120223285 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 09-06-2012 |
| 20120228575 | NANOSCALE ELECTRONIC DEVICE WITH BARRIER LAYERS - On example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and a device layer. The device layer comprises a first dielectric material, between the first and second conductive electrodes, that includes an effective device layer, a first barrier layer near a first interface between the first conductive electrode and the device layer, and a second barrier layer near a second interface between the second conductive electrode and the device layer. A second example of the present invention is an integrated circuit that incorporates nanoscale electronic devices of the first example. | 09-13-2012 |
| 20120228576 | STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A storage device includes: a plurality of first electrode wirings; a plurality of second electrode wirings which cross the first electrode wirings; a via plug which is formed between the second electrode wiring and the two adjacent first electrode wirings, and in which a maximum diameter of a bottom surface opposing the first electrode wirings in a direction vertical to a direction in which the first electrode wirings stretch is smaller than a length corresponding to a pitch of the first electrode wiring plus a width of the first electrode wirings; a first storage element which is formed between the via plug and one of the two first electrode wirings; and a second storage element which is formed between the via plug and the other one of the two first electrode wirings. | 09-13-2012 |
| 20120228577 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device includes a mold oxide layer on a substrate, a lower electrode on the mold oxide layer and connected to the substrate, a blocking structure covering a part of the lower electrode and including an etch-stop layer and a blocking structure insulating layer, and a phase change layer covering a remaining part of the lower electrode not covered by the blocking structure, The etch-stop layer includes a material having a higher etching selectivity than that of the lower electrode. | 09-13-2012 |
| 20120228578 | Resistive Memory Element and Related Control Method - Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane. | 09-13-2012 |
| 20120235109 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film. | 09-20-2012 |
| 20120235110 | PHASE-CHANGE MATERIAL AND PHASE-CHANGE TYPE MEMORY DEVICE - A phase-change material, which has a high crystallization temperature and is superior in thermal stability of the amorphous phase, which has a composition of the general chemical formula Ge | 09-20-2012 |
| 20120235111 | NONVOLATILE MEMORY ELEMENT HAVING A TANTALUM OXIDE VARIABLE RESISTANCE LAYER - A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 0| 09-20-2012 | |
| 20120235112 | RESISTIVE SWITCHING MEMORY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to the microelectronics field, and particularly, to a resistive switching memory and a method for manufacturing the same. The memory may comprise a lower electrode, a resistive switching layer, and an upper electrode. The resistive switching layer may have carbon nano-tubes embedded therein. Growth of a conductive filament in the resistive switching layer can be facilitated and controlled under an externally applied bias by a local electric field enhancement effect of the carbon nano-tubes, so as to improve performances and stability of the device. The resistive switching memory according to the present disclosure can have a good resistive switching capability. Further, the operating voltage and the resistance value of the device can be well controlled by controlling the length and position of the carbon nano-tubes in the resistive switching layer. | 09-20-2012 |
| 20120241710 | Fabrication of RRAM Cell Using CMOS Compatible Processes - Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. | 09-27-2012 |
| 20120241711 | MULTI-LEVEL MEMORY CELL - Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described. | 09-27-2012 |
| 20120241712 | Resistive-Switching Memory and Fabrication Method Thereof - The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved. | 09-27-2012 |
| 20120241713 | ORGANIC MOLECULAR MEMORY - An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including charge-storage molecular chains or variable-resistance molecular chains, the charge-storage molecular chains or the variable-resistance molecular chains including fused polycyclic groups. | 09-27-2012 |
| 20120241714 | Non-Volatile Resistive Oxide Memory Cells And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section. | 09-27-2012 |
| 20120241715 | SEMICONDUCTOR MEMORY - Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer. | 09-27-2012 |
| 20120248396 | RESISTIVE SWITCHING IN MEMORY CELLS - Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell. | 10-04-2012 |
| 20120248397 | NONVOLATILE STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF - In a variable resistance nonvolatile storage element, an electrode suitable for a variable resistance operation and formed of a metallic nitride layer containing Ti and N is provided. In a nonvolatile storage device including: a first electrode; a second electrode; and a variable resistance layer which is sandwiched between the first electrode and the second electrode and in which a resistance value changes to two different resistance states, at least one of the first electrode and the second electrode is an electrode including a metallic nitride layer containing at least Ti and N, and a mole ratio (N/Ti ratio) between Ti and N in at least a part of the metallic nitride layer, the part being in contact with the variable resistance layer is 1.15 or more and a film density is 4.7 g/cc or more. | 10-04-2012 |
| 20120248398 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 10-04-2012 |
| 20120248399 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line ( | 10-04-2012 |
| 20120256155 | Closed loop sputtering controlled to enhance electrical characteristics in deposited layer - This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (I | 10-11-2012 |
| 20120256156 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a memory device provided with a plurality of memory cells and a lead-out line ( | 10-11-2012 |
| 20120261636 | RESISTIVE RANDOM ACCESS MEMORY (RAM) CELL AND METHOD FOR FORMING - A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer. | 10-18-2012 |
| 20120261637 | OXIDE BASED MEMORY WITH A CONTROLLED OXYGEN VACANCY CONDUCTION PATH - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide. | 10-18-2012 |
| 20120267596 | NON-VOLATILE MEMORY - An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer. | 10-25-2012 |
| 20120267597 | SIDEWALL THIN FILM ELECTRODE WITH SELF-ALIGNED TOP ELECTRODE AND PROGRAMMABLE RESISTANCE MEMORY - A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces. | 10-25-2012 |
| 20120267598 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side. | 10-25-2012 |
| 20120267599 | RESISTIVE RAM DEVICES AND METHODS - The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element. | 10-25-2012 |
| 20120273746 | SYSTEM AND METHOD FOR THE RELAXATION OF STRESS IN PHASE MEMORY DEVICES - A phase change memory device that utilizes a nanowire structure. Usage of the nanowire structure permits the phase change memory device to release its stress upon amorphization via the minimization of reset resistance and threshold resistance. | 11-01-2012 |
| 20120280200 | RESISTANCE CHANGING ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING RESISTANCE CHANGE ELEMENT - A resistance changing element according to the present invention comprises a first electrode ( | 11-08-2012 |
| 20120280201 | OPTIMIZED ELECTRODES FOR RE-RAM - Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element. | 11-08-2012 |
| 20120286227 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an isolation layer formed in a substrate and defining an active region, a trench formed in the substrate and defining a part of the active region as an active pillar; a word line formed inside the trench, a sub-source line formed under the trench and crossing the word line, a main source line formed over the substrate, coupled to the sub-source line, and crossing the word line, a variable resistor pattern formed over the active pillar, and a bit line contacting the variable resistor pattern and crossing the word line. | 11-15-2012 |
| 20120286228 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change random access memory device includes a bottom electrode contact formed within a bottom electrode contact hole, a phase-change material pattern formed to surround a side of an upper portion of the bottom electrode contact, and an insulating layer buried within the phase-change material pattern and formed on an upper surface of the bottom electrode contact. | 11-15-2012 |
| 20120286229 | Memory Cells - Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials. | 11-15-2012 |
| 20120286230 | CONFINEMENT TECHNIQUES FOR NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode. | 11-15-2012 |
| 20120286231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof. | 11-15-2012 |
| 20120292586 | NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element. | 11-22-2012 |
| 20120292587 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film. | 11-22-2012 |
| 20120292588 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device including: a strip-shaped first electrode line ( | 11-22-2012 |
| 20120292589 | NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70Ω to 1000Ω inclusive. | 11-22-2012 |
| 20120305878 | RESISTIVE SWITCHING MEMORY DEVICE - A nonvolatile memory element may include, but is not limited to: a first electrode; a second electrode; and a resistive switching material disposed between the first electrode and the second electrode, wherein at least one of the first electrode or the second electrode includes at least one of a metal cation or metalloid cation having a valence state, oxidation state or oxidation number and wherein the resistive switching material includes at least one of a metal cation or a metalloid cation having the same valence state oxidation state or oxidation number as the at least one of a metal cation or metalloid cation of the at least one of the first electrode or the second electrode. | 12-06-2012 |
| 20120305879 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 12-06-2012 |
| 20120305880 | RESISTIVE RANDOM ACCESS MEMORY WITH ELECTRIC-FIELD STRENGTHENED LAYER AND MANUFACTURING METHOD THEREOF - This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable. | 12-06-2012 |
| 20120305881 | Nitrogen Doped Aluminum Oxide Resistive Random Access Memory - A resistive random access memory (RRAM) device is provided that includes a first electrode, a second electrode, and a resistance-change film disposed between the first electrode and the second electrode, where the resistance-change film includes an atomic ratio of aluminum, oxygen and nitrogen. | 12-06-2012 |
| 20120305882 | NiO-based Resistive Random Access Memory and the Preparation Method Thereof - The present invention belongs to the technical field of memory storage and specially relates to a NiO-based resistive random access memory system (RRAM) and a preparation method thereof. The RRAM is comprised of a substrate and a metal-insulator-metal (MIM) structure, wherein the electrodes are metal films, such as copper, aluminum, etc., capable of being applied to the interconnection process, and the resistive switching insulator is an Al | 12-06-2012 |
| 20120305883 | METAL OXIDE RESISTIVE SWITCHING MEMORY AND METHOD FOR MANUFACTURING SAME - The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory. According to the present disclosure, the manufacture process can be simplified, without incorporating additional exposure steps in the standard process, resulting in advantages such as reduced cost. | 12-06-2012 |
| 20120305884 | VARIABLE RESISTANCE MEMORY DEVICE AND METHODS OF FORMING THE SAME - A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern. | 12-06-2012 |
| 20120305885 | VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material. | 12-06-2012 |
| 20120313069 | WORK FUNCTION TAILORING FOR NONVOLATILE MEMORY APPLICATIONS - Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another. | 12-13-2012 |
| 20120313070 | CONTROLLED SWITCHING MEMRISTOR - A controlled switching memristor includes a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode. The switching layer includes a material to switch between an ON state and an OFF state, in which at least one of the first electrode, the second electrode, and the switching layer is to generate a permanent field within the memristor to enable a speed and an energy of switching from the ON state to the OFF state to be substantially symmetric to a speed and energy of switching from the OFF state to the ON state. | 12-13-2012 |
| 20120313071 | CONTACT STRUCTURE AND METHOD FOR VARIABLE IMPEDANCE MEMORY ELEMENT - A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed. | 12-13-2012 |
| 20120313072 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES HAVING DOUBLE CROSS POINT ARRAY AND METHODS OF FABRICATING THE SAME - Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines. | 12-13-2012 |
| 20120319070 | RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS - Nonvolatile memory elements are provided comprising switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 12-20-2012 |
| 20120319071 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a variable resistive element that can perform a stable switching operation at low voltage and low current, and also provides a low-power consumption large-capacity non-volatile semiconductor memory device including the variable resistive element. The non-volatile semiconductor memory device is a device using a variable resistive element, which includes a variable resistor between a first electrode and a second electrode, for storing information, wherein an oxygen concentration of a hafnium oxide (HfO | 12-20-2012 |
| 20120319072 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY ELEMENT, AND NON-VOLATILE MEMORY DEVICE - A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers. | 12-20-2012 |
| 20120319073 | VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit. | 12-20-2012 |
| 20120319074 | RESISTANCE CHANGE DEVICE AND MEMORY CELL ARRAY - According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode. | 12-20-2012 |
| 20120319075 | SEMICONDUCTOR DEVICE INCLUDING STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials. | 12-20-2012 |
| 20120326113 | NON-VOLATILE MEMORY ELEMENT AND NON-VOLATILE MEMORY DEVICE EQUIPPED WITH SAME - Provided are a non-volatile memory element which can reduce a voltage of an electric pulse required for initial breakdown, and can lessen non-uniformity of a resistance value of the non-volatile memory element, and a non-volatile memory device including the non-volatile memory element. A non-volatile memory element comprises a first electrode ( | 12-27-2012 |
| 20130001501 | MEMORY CELL STRUCTURES - The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. | 01-03-2013 |
| 20130001502 | PHASE-CHANGE MEMORY DEVICE, FLEXIBLE PHASE-CHANGE MEMORY DEVICE USING INSULATING NANO-DOT AND MANUFACTURING METHOD FOR THE SAME - Provided are a phase-change memory device using insulating nanoparticles, a flexible phase-change memory device and a method for manufacturing the same. The phase-change memory device includes an electrode, and a phase-change layer in which a phase change occurs depending on heat generated from the electrode, wherein insulating nanoparticles formed from a self-assembled block copolymer are provided between the electrode and the phase-change layer undergoing crystallization and amorphization. | 01-03-2013 |
| 20130001503 | CONDUCTIVE FILAMENT BASED MEMORY ELEMENTS AND METHODS WITH IMPROVED DATA RETENTION AND/OR ENDURANCE - A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed. | 01-03-2013 |
| 20130001504 | NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME - Provided is a nonvolatile memory element which inhibits deterioration of a oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element. A nonvolatile memory element ( | 01-03-2013 |
| 20130001505 | MULTILAYER STRUCTURE COMPRISING A PHASE CHANGE MATERIAL LAYER AND METHOD OF PRODUCING THE SAME - A method of producing a multilayer structure is provided, wherein the method comprises forming a phase change material layer onto a substrate, forming a protective layer, forming a further layer on the protective layer, patterning the further layer in an first patterning step, patterning the protective layer and the phase change material layer by a second patterning step. In particular, the first patterning step may be an etching step using chemical etchants. Moreover, electrodes may be formed on the substrate before the phase change material layer is formed, e.g. the electrodes may be formed on one level, e.g. may form a planar structure and may not form a vertically structure. | 01-03-2013 |
| 20130009124 | RESISTIVE RAM HAVING THE FUNCTION OF DIODE RECTIFICATION - A type of resistance random access memory structure having the function of diode rectification includes a first electrode, a second electrode and a resistance conversion layer. The resistance conversion layer is disposed between the first electrode and the second electrode; and it includes a first oxidized insulating layer which is adjacently connected to the first electrode; a second oxidized insulating layer which is adjacently connected to the second electrode; as well as an energy barrier turning layer disposing between the first oxidized insulating layer and the second oxidized insulating layer. An energy barrier high can be adjusted and controlled to change the resistance by voltage between the energy barrier turning layer and the first oxidized insulating layer. A fixed energy barrier is formed between the second oxidized insulating layer and the energy barrier turning layer, so that the resistance random access memory element features the function of diode rectification. | 01-10-2013 |
| 20130009125 | LOW RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation layer including a cell contact hole, and a switching device in the cell contact hole, at least a part of a top surface of the switching device being inclined with respect to an axial direction of the cell contact hole. | 01-10-2013 |
| 20130009126 | PROGRAMMABLE METALLIZATION CELLS AND METHODS OF FORMING THE SAME - A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed. | 01-10-2013 |
| 20130009127 | RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material. | 01-10-2013 |
| 20130015422 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide. | 01-17-2013 |
| 20130015423 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, AND NONVOLATILE SEMICONDUCTOR MEMORY ELEMENTAANM Mikawa; TakumiAACI ShigaAACO JPAAGP Mikawa; Takumi Shiga JPAANM Hayakawa; YukioAACI KyotoAACO JPAAGP Hayakawa; Yukio Kyoto JPAANM Kawashima; YoshioAACI OsakaAACO JPAAGP Kawashima; Yoshio Osaka JPAANM Ninomiya; TakekiAACI OsakaAACO JPAAGP Ninomiya; Takeki Osaka JP - Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer. | 01-17-2013 |
| 20130026436 | PHASE CHANGE MEMORY ELECTRODE WITH SHEATH FOR REDUCED PROGRAMMING CURRENT - An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode. | 01-31-2013 |
| 20130026437 | RESISTANCE VARIABLE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a resistance variable memory device, includes: providing a substrate having first contacts and second contacts, where the second contacts do not overlap the first contacts; forming a line pattern over the substrate, the line pattern overlapping a first line and including a stacked structure of a first electrode, a resistor, and a second electrode; forming a first contact hole to expose the second contact; forming an insulating spacer on a sidewall of the first contact hole; forming a third contact to fill the first contact hole having the insulating spacer formed therein; and forming a third electrode over the third contact such that the third electrode overlaps a second line extending in a second direction and is cut open over the first contact, where the first and second contacts are alternately arranged on the second line. | 01-31-2013 |
| 20130026438 | CURRENT-LIMITING LAYER AND A CURRENT-REDUCING LAYER IN A MEMORY DEVICE - A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime. | 01-31-2013 |
| 20130026439 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other. | 01-31-2013 |
| 20130026440 | NANOSCALE SWITCHING DEVICES WITH PARTIALLY OXIDIZED ELECTRODES - A nanoscale switching device is provided. The device comprises: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having a non-conducting portion comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field and a source portion that acts as a source or sink for the dopants; and an oxide layer either formed on the first electrode, between the first electrode and the active region or formed on the second electrode, between the second electrode and the active region. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided. | 01-31-2013 |
| 20130037777 | NON-VOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line. | 02-14-2013 |
| 20130043452 | Structures And Methods For Facilitating Enhanced Cycling Endurance Of Memory Accesses To Re-Writable Non Volatile Two Terminal Memory Elements - Structures and methods to enhance cycling endurance of BEOL memory elements are disclosed. In some embodiments, a memory element can include a support layer having a smooth and planar upper surface as deposited or as created by additional processing. A first electrode is formed the smooth and planar upper surface. The support layer can be configured to influence the formation of the first electrode to determine a substantially smooth surface of the first electrode. The memory element is formed over the first electrode having the substantially smooth surface, the memory element including one or more layers of an insulating metal oxide (IMO) operative to exchange ions to store a plurality of resistive states. The substantially smooth surface of the first electrode provides for uniform current densities through unit cross-sectional areas of the IMO. The memory element can include one or more layers of a conductive metal oxide (CMO). | 02-21-2013 |
| 20130043453 | Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes - A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes. | 02-21-2013 |
| 20130043454 | Non-volatile resistive switching memories formed using anodization - Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element. | 02-21-2013 |
| 20130056700 | DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE - Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. The addition of the getter or defect portions in a formed memory device generally improves the reliability of the resistive switching memory device, improves the switching characteristics of the formed memory device and can eliminate or reduce the need for the time consuming additional post fabrication “burn-in” or pre-programming steps. | 03-07-2013 |
| 20130056701 | NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE - A nonvolatile memory element including a resistance variable element configured to reversibly change between a low-resistance state and a high-resistance state in response to electric signals with different polarities; and a current controlling element configured such that when a current flowing when a voltage whose absolute value is a first value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is a first polarity is applied is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is a second polarity is applied is a second current, the first current is higher than the second current, and the resistance variable element is connected with the current controlling element such that the first polarity voltage is applied to the current controlling element when the resistance variable element changes from the low-resistance to the high-resistance state. | 03-07-2013 |
| 20130056702 | ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS - Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells. | 03-07-2013 |
| 20130062586 | Semiconductor Device and Manufacturing Method Thereof - This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode. | 03-14-2013 |
| 20130062587 | Resistive Switching Devices Having Alloyed Electrodes And Methods of Formation Thereof - In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer. | 03-14-2013 |
| 20130062588 | NONVOLATILE SEMICOCDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device has a first wire, a second wire, and a memory cell electrically coupled to the first wire at one end and to the second wire at the other end. The memory cell has a resistance change layer to store information by changing a resistance value and a first electrode and a second electrode coupled to both ends of the resistance change layer and not containing a precious metal. The first electrode includes an outside electrode and an interface electrode formed between the outside electrode and the resistance change layer. The thickness of the interface electrode is less than the thickness of the outside electrode. The resistivity of the interface electrode is higher than the resistivity of the outside electrode. The resistance value of the first electrode is lower than the resistance value of the resistance change layer in a low resistance state. | 03-14-2013 |
| 20130062589 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectification connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a value of voltage which is applied to the memory element to change a resistance of the memory element reversibly between first and second values. The rectification includes a p-type semiconductor layer, an n-type semiconductor layer and an intrinsic semiconductor layer therebetween. The rectification has a first diffusion prevention area in the intrinsic semiconductor layer. | 03-14-2013 |
| 20130069030 | RESISTIVE MEMORY CELL INCLUDING INTEGRATED SELECT DEVICE AND STORAGE ELEMENT - Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode. | 03-21-2013 |
| 20130069031 | MULTILEVEL RESISTIVE MEMORY HAVING LARGE STORAGE CAPACITY - The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta | 03-21-2013 |
| 20130075686 | VARIABLE RESISTANCE MEMORY - A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode. | 03-28-2013 |
| 20130075687 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film. | 03-28-2013 |
| 20130075688 | Semiconductor Memory Device and Manufacturing Method Thereof - A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element. | 03-28-2013 |
| 20130082228 | Memory Device Using Multiple Tunnel Oxide Layers - A memory element (ME) including at least one layer of conductive metal oxide (CMO) that includes mobile oxygen ions and including at least two layers of insulating metal oxide (IMO) is disclosed. In one configuration a layer of IMO that is directly in contact with a CMO layer is specifically selected so that a material of the IMO layer is non-reactive with a material of the CMO. In another configuration, at least one pair of adjacent IMO layers are made from materials having different band gaps operative to an generate an internal electric field positioned in the layers and present in the at least two adjacent IMO layers in the absence of electrical power. The internal electric field can be a static electric field. The IMO and/or CMO layers can be deposited in part or in whole using ALD, PEALD, or nano-deposition. The ME can be formed BEOL. | 04-04-2013 |
| 20130082229 | MIXED IONIC-ELECTRONIC CONDUCTION MEMORY CELL - A mixed ionic-electronic conduction (MIEC) memory cell including a mixed ionic-electronic conductor containing dopants therein, a heater disposed adjacent to the mixed ionic-electronic conductor, a pair of first electrodes electrically connected to the mixed ionic-electronic conductor, and at least one pair of second electrodes electrically connected to the mixed ionic-electronic conductor is provided. The pair of first electrodes drive the dopants in the mixed ionic-electronic conductor to drift along a first direction when the mixed ionic-electronic conductor is heated by the heater. The pair of second electrodes locally modify a distribution of the dopants along a second direction when the mixed ionic-electronic conductor is heated by the heater, and the first direction is different from the second direction. | 04-04-2013 |
| 20130082230 | METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY ELEMENT - A variable resistance nonvolatile memory element manufacturing method includes: forming a first electrode on a substrate; forming a first metal oxide layer having a predetermined oxygen content atomic percentage on the first electrode; forming, in at least one part of the first metal oxide layer, a modified layer higher in resistance than the first metal oxide layer, by oxygen deficiency reduction; forming a second metal oxide layer lower in oxygen content atomic percentage than the first metal oxide layer, on the modified layer; and forming a second electrode on the second metal oxide layer. A variable resistance layer includes the first metal oxide layer having the modified layer and the second metal oxide layer, connects to the first electrode and the second electrode, and changes between high and low resistance states according to electrical pulse polarity. | 04-04-2013 |
| 20130082231 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes multilayer interconnects and two variable resistance elements ( | 04-04-2013 |
| 20130087756 | HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner. | 04-11-2013 |
| 20130087757 | RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a resistive memory device is provided. A bottom electrode and a cup-shaped electrode connected to the bottom electrode are formed in an insulating layer. A cover layer extends along a first direction is formed and covers a first area surrounded by the cup-shaped electrode and exposes a second area and a third area surrounded by the cup-shaped electrode. A sacrificial layer is formed above the insulating layer. A stacked layer extends along a second direction and covers the second area surrounded by the cup-shaped electrode and a portion of the corresponding cover layer is formed. A conductive spacer material layer is formed on the stacked layer and the sacrificial layer. By using the sacrificial layer as an etch stop layer, the conductive spacer material layer is etched to form a conductive spacer at the sidewall of the stacked layer. | 04-11-2013 |
| 20130092894 | MEMORY CELLS AND MEMORY CELL ARRAYS - Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures. | 04-18-2013 |
| 20130099190 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A diode may be foamed within a molding layer on a substrate. A conductive buffer pattern having a greater planar area than the diode may be on the diode and molding layer. An electrode structure may be on the conductive buffer pattern. A data storage pattern may be on the electrode structure. One lateral surface of the conductive buffer pattern may be vertically aligned with one lateral surface of the electrode structure. | 04-25-2013 |
| 20130099191 | Resistive switching memory elements having improved switching characteristics - Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness. | 04-25-2013 |
| 20130099192 | Electronic Devices, Memory Devices and Memory Arrays - Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells. | 04-25-2013 |
| 20130105757 | PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
| 20130105758 | MEMORY CELL OF RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
| 20130112934 | NANOSCALE SWITCHING DEVICE - A nanoscale switching device has an active region disposed between two electrodes of nanoscale widths. The active region contains a switching material that carries mobile ionic dopants capable of being transported over the active region under an electric field to change a resistive state of the device. The switching material further carries immobile ionic dopants for inhibiting clustering of the mobile ionic dopants caused by switching cycles of the device. The immobile ionic dopants have a charge opposite in polarity to the charge of the mobile ionic dopants, and are less mobile under the electric field than the mobile ion dopants. | 05-09-2013 |
| 20130112935 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND MANUFACTURING METHOD FOR THE SAME - A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure. | 05-09-2013 |
| 20130112936 | RESISTANCE CHANGE ELEMENT AND MANUFACTURING METHOD THEREFOR - A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, the second electrode has a single needle-shaped part at the interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the needle-shaped part. | 05-09-2013 |
| 20130119340 | MULTI-BIT RESISTIVE-SWITCHING MEMORY CELL AND ARRAY - This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal. | 05-16-2013 |
| 20130119341 | RESISTIVE RANDOM ACCESS MEMORY CELL AND MEMORY - A Resistive Random Access Memory (RRAM) cell and a memory are disclosed. In one embodiment, the RRAM cell comprises a two-state resistor and a resistive switching memory cell connected in series. The two-state resistor can supply relatively large currents under both positive and negative voltage polarities. As a result, it is possible to reduce leakage paths in a crossbar array of memory cells, and thus to suppress reading crosstalk. | 05-16-2013 |
| 20130119342 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method can include introducing halogen in a contact layer with a resistance variation film including a metal oxide. The method can include diffusing the halogen from the contact layer to the resistance variation film by a thermal treatment. | 05-16-2013 |
| 20130119343 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME - A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer. | 05-16-2013 |
| 20130119344 | NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING SAME - A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MO | 05-16-2013 |
| 20130126817 | E-FUSES CONTAINING AT LEAST ONE UNDERLYING TUNGSTEN CONTACT FOR PROGRAMMING - Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts. | 05-23-2013 |
| 20130126818 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) USING STACKED DIELECTRICS AND METHOD FOR MANUFACTURING THE SAME - Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 μW, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5×10 | 05-23-2013 |
| 20130126819 | MEMORY DEVICE HAVING VERTICAL SELECTION TRANSISTORS WITH SHARED CHANNEL STRUCTURE AND METHOD FOR MAKING THE SAME - The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines. | 05-23-2013 |
| 20130126820 | VARIABLE AND REVERSIBLE RESISTIVE MEMORY STORAGE ELEMENT AND MEMORY STORAGE MODULE HAVING THE SAME - A variable and reversible resistive memory storage element and a memory storage module having the same are provided. The memory storage module comprises a select gate element and the resistive memory storage element. The select gate element comprises two source/drain regions. The resistive memory storage module comprises a first electrode, a first high-k dielectric layer and a second electrode. The first electrode is a semiconductor doping area, which is one of the two source/drain regions of the select gate element. The first high-k dielectric layer is formed on the first electrode to provide a variable resistance. The second electrode is a first metal gate formed on the first high-k dielectric layer. | 05-23-2013 |
| 20130126821 | BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS - In a first aspect, a metal-insulator-metal (“MIM”) stack is provided that includes a first conductive layer, a resistivity-switching layer having a metal oxide layer formed above the first conductive layer, a material layer between the first conductive layer and the resistivity-switching layer, and a second conductive layer above the resistivity-switching layer. The first conductive layer includes a multi-layer metal-silicide stack, and the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV. A memory cell may be formed from the MIM stack. Numerous other aspects are provided. | 05-23-2013 |
| 20130134376 | ATOMIC LAYER DEPOSITION OF ZIRCONIUM OXIDE FOR FORMING RESISTIVE-SWITCHING MATERIALS - Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium oxide for use in a variety of electronic devices. Forming the dielectric layer includes depositing zirconium oxide using atomic layer deposition. A method of atomic layer deposition to produce a metal-rich metal oxide comprises the steps of providing a silicon substrate in a reaction chamber, pulsing a zirconium precursor for a predetermined time to deposit a first layer, and oxidizing the first layer with water vapor to produce the metal-rich metal oxide. The metal-rich metal oxide has superior properties for non-volatile resistive-switching memories. | 05-30-2013 |
| 20130134377 | SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED RESISTIVE MEMORY CELLS - Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other. | 05-30-2013 |
| 20130134378 | VARIABLE-RESISTANCE MATERIAL MEMORIES AND METHODS - Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells. | 05-30-2013 |
| 20130134379 | RESISTIVE MEMORY USING SIGE MATERIAL - A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell. | 05-30-2013 |
| 20130134380 | UPWARDLY TAPERING HEATERS FOR PHASE CHANGE MEMORIES - A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments. | 05-30-2013 |
| 20130140512 | NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A PASSIVATED SWITCHING LAYER - A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties. | 06-06-2013 |
| 20130140513 | THERMALLY CONFINED ELECTRODE FOR PROGRAMMABLE RESISTANCE MEMORY - A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition Ta | 06-06-2013 |
| 20130140514 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes a substrate, a lower electrode formed above said substrate, a second variable resistance layer formed above said lower electrode and comprising a second transitional metal oxide, a first variable resistance layer formed above said second variable resistance layer and comprising a first transitional metal oxide having an oxygen content that is lower than an oxygen content of the second transitional metal oxide, and an upper electrode formed above said first variable resistance layer. A step is formed in an interface between said lower electrode and said second variable resistance layer. The second variable resistance layer is formed covering the step and has a bend above the step. | 06-06-2013 |
| 20130140515 | NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nonvolatile memory element, the method including: forming a first lower electrode layer, a current steering layer, and a first upper electrode layer; forming a second lower electrode layer, a variable resistance layer, and a second upper electrode layer on the first upper electrode layer; patterning the second upper electrode layer, the variable resistance layer, and the lower electrode layer; patterning the first upper electrode layer, the current steering layer, and first lower electrode layer to form a current steering element, using the second lower electrode layer as a mask by use of etching which is performed on the second lower electrode layer at an etching rate lower than at least etching rates at which the second upper electrode layer and the variable resistance layer are etched; and forming a variable resistance element which has an area smaller than the area of the current steering element. | 06-06-2013 |
| 20130153851 | STACK TYPE SEMICONDUCTOR MEMORY DEVICE - A stack type memory device includes a semiconductor substrate; a plurality of bit lines arranged and stacked on the semiconductor substrate; a plurality of word lines formed on the plurality of bit lines; a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines; and a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively. | 06-20-2013 |
| 20130153852 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A variable resistance memory device comprises a bit line extended in a first direction, a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line in the third direction, a variable resistance layer disposed on a part of the vertical electrode, multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction, and a selection transistor including a first dopant injection region electrically connected to the vertical electrode, and a second dopant injection region electrically connected to the bit line. | 06-20-2013 |
| 20130153853 | HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS - Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material. | 06-20-2013 |
| 20130153854 | DIAMOND TYPE QUAD-RESISTOR CELLS OF PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material. | 06-20-2013 |
| 20130161582 | CONDUCTIVE BRIDGING MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a conductive bridging memory device includes a first wiring layer having a plurality of first wiring portions extending in a first direction, a second wiring layer having a plurality of second wiring portions extending in a second direction crossing the first direction, and a resistance change layer provided continuously along a plane having the first direction and the second direction between the first wiring layer and the second wiring layer. Each of the first wiring portions includes a first wiring extending in the first direction. Each of the second wiring portions includes a second wiring extending in the second direction, and an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction. | 06-27-2013 |
| 20130168630 | Memory Structures and Arrays, and Methods of Forming Memory Structures and Arrays - Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures. | 07-04-2013 |
| 20130168631 | NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR FABRICATING THE SAME - The disclosure provides a non-volatile memory structure and a method for fabricating the same. The non-volatile memory structure includes a first contact connected to a first transistor. A second contact is connected to a second transistor. A resistance-changing memory material pattern covers and contacts the second contact but not the first contact. A top electrode contacts both the resistance-changing memory material pattern and the first contact. An area of the resistance-changing memory material pattern is substantially larger than an area of its interface with the second contact. | 07-04-2013 |
| 20130168632 | RESISTANCE VARIABLE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer. | 07-04-2013 |
| 20130168633 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device that may be used for a phase change random access memory in a semiconductor device and a manufacturing method thereof are provided. The device includes a phase change unit and two sidewall electrodes respectively located on two opposite sidewalls of the phase change unit. The phase change unit includes a three layer structure, in which a phase change material layer is positioned between a top insulating material layer and a bottom insulating material layer. The first sidewall electrode and the second sidewall electrode are in contact with two opposite end faces of the phase change material layer. The contact area between electrode and phase change material is reduced, thereby obtaining a relatively small drive current and meeting a demand that the integrated level of such a device is increasingly enhanced. | 07-04-2013 |
| 20130168634 | RESISTIVE RANDOM ACCESS MEMORY DEVICE - A resistive memory device includes a lower electrode disposed on a substrate, first and second resistance layers respectively disposed on opposite sides of the lower electrode and exhibiting resistance variation at different voltages, respectively, and an upper electrode disposed on and the first and second resistance layers. | 07-04-2013 |
| 20130175494 | MEMORY CELLS INCLUDING TOP ELECTRODES COMPRISING METAL SILICIDE, APPARATUSES INCLUDING SUCH CELLS, AND RELATED METHODS - Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials. | 07-11-2013 |
| 20130175495 | Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material - Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide. | 07-11-2013 |
| 20130181182 | PHASE-CHANGE MEMORY CELL - The memory cell includes a memory area which is formed in a phase-change material pattern based on chalcogenide. An electric pin-type junction is series-connected between electrodes. The pin junction is formed in a crystalline area by the interface between first and second doped areas of the phase-change material pattern. The memory area is formed in one of the two doped areas, at a distance from the junction. | 07-18-2013 |
| 20130187116 | RRAM Device With Free-Forming Conductive Filament(s), and Methods of Making Same - Disclosed herein is an RRAM device with free-forming conductive filament(s), and various methods of making such an RRAM device. In one example, a device disclosed herein includes a first electrode, a second electrode positioned above the first electrode and a variable resistance material positioned between the first and second electrodes, wherein the variable resistance material is a metal oxide with a plurality of metal nano-crystals embedded therein. | 07-25-2013 |
| 20130187117 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another. | 07-25-2013 |
| 20130187118 | MEMORY DEVICE - According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects. | 07-25-2013 |
| 20130187119 | Semiconductor Memory Devices Having Strapping Contacts - Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions. | 07-25-2013 |
| 20130193394 | INCORPORATION OF OXYGEN INTO MEMORY CELLS - Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the resistive random access memory cell and methods of forming the resistive random access memory cell. Oxygen can be incorporated into the resistive random access memory cell by ion implantation. Additional apparatus, systems, and methods are disclosed. | 08-01-2013 |
| 20130193395 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FORMING THE SAME - According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate. | 08-01-2013 |
| 20130193396 | VARIABLE RESISTIVE ELEMENT, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A variable resistive element that performs a forming action at small current and a stable switching operation at low voltage and small current, and a low-power consumption large-capacity non-volatile semiconductor memory device including the element are realized. The element includes a variable resistor between first and second electrodes. The variable resistor includes at least two layers, which are a resistance change layer and high-oxygen layer, made of metal oxide or metal oxynitride. The high-oxygen layer is inserted between the first electrode having a work function smaller than the second electrode and the resistance change layer. The oxygen concentration of the metal oxide of the high-oxygen layer is adjusted such that the ratio of the oxygen composition ratio to the metal element to stoichiometric composition becomes larger than the ratio of the oxygen composition ratio to the metal element of the metal oxide forming the resistance change layer to stoichiometric composition. | 08-01-2013 |
| 20130193397 | High Consistency Resistive Memory and Manufacturing Method Thereof - The present invention relates to the technical field of memories, and in particular to a highly-consistent resistive memory and method of fabricating the same. The resistive memory comprises: a lower electrode which is formed in a first dielectric layer by patterning; a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for exposing the lower electrode to perform patterning; an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed; a storage medium layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; and an upper electrode. The resistive memory exhibits good consistency and high reliability; moreover, unit size is mall, which is advantageous for improving storage characteristic. When an array of memories is formed by the resistive memories, a good consistency is obtained among multiple resistive memories. | 08-01-2013 |
| 20130200322 | MEMORY ARRAYS AND METHODS OF FORMING THE SAME - Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry. | 08-08-2013 |
| 20130200323 | MULTIFUNCTIONAL ELECTRODE - A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ω cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed. | 08-08-2013 |
| 20130200324 | Transition Metal Oxide Bilayers - Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen. | 08-08-2013 |
| 20130200325 | Nonvolatile Memory Device Using A Tunnel Nitride As A Current Limiter Element - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises a resistive material that is configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel nitride that is a current limiting material that is disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. | 08-08-2013 |
| 20130200326 | NONVOLATILE MEMORY CELL AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film. | 08-08-2013 |
| 20130200327 | Resistive Memory Arrangement and a Method of Forming the Same - According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided. | 08-08-2013 |
| 20130200328 | PHASE CHANGE MEMORY DEVICES - A phase change memory device is provided, including: a substrate; a first dielectric layer disposed over the substrate; a first electrode disposed in the first dielectric layer; a second dielectric layer formed over the first dielectric layer, covering the first electrode; a heating electrode disposed in the second dielectric layer, contacting the first electrode; a phase change material layer disposed over the second dielectric layer, contacting the heating electrode; and a second electrode disposed over the phase change material layer, wherein the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides, and the first portion of the heating electrode includes no metal silicides, and includes refractory metal materials or noble metal materials. | 08-08-2013 |
| 20130200329 | MEMORY CELL DEVICE AND METHOD OF MANUFACTURE - According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material. | 08-08-2013 |
| 20130207067 | VERTICAL SELECTION TRANSISTOR, MEMORY CELL, AND THREE-DIMENSIONAL MEMORY ARRAY STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively. | 08-15-2013 |
| 20130214236 | USING TiON AS ELECTRODES AND SWITCHING LAYERS IN ReRAM DEVICES - A single TiON film is used to form a ReRAM device by varying the oxygen and nitrogen content throughout the device to form the electrodes and switching layer. A ReRAM device that can be formed in a single deposition chamber is also disclosed. The ReRAM device can be formed by forming a first titanium nitride layer, forming atitanium oxynitride-titanium oxide-titanium oxynitride layer, and then forming a second titanium nitride. | 08-22-2013 |
| 20130214237 | NONVOLATILE MEMORY DEVICE USING A TUNNEL OXIDE LAYER AND OXYGEN BLOCKING LAYER AS A CURRENT LIMITER ELEMENT - Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, due to the addition of a current limiting component. In one embodiment, the current limiting component comprises a resistive material configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide layer that is a current limiting material and an oxygen barrier layer that is an oxygen deficient material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. | 08-22-2013 |
| 20130214238 | Method for Forming Metal Oxides and Silicides in a Memory Device - Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process. | 08-22-2013 |
| 20130214239 | METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT - A method for manufacturing a resistive memory element includes providing a storage layer comprising a resistance changeable material, said resistance changeable material comprising carbon; providing contact layers for contacting the storage layer, wherein the storage layer is disposed between a bottom contact layer and a top contact layer; and doping the resistance changeable material with a dopant material. | 08-22-2013 |
| 20130214240 | Memory Device with a Textured Lowered Electrode - Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack. | 08-22-2013 |
| 20130221313 | ULTRA HIGH DENSITY RESISTIVE MEMORY STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses an ultra high density resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area. | 08-29-2013 |
| 20130221314 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
| 20130221315 | Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
| 20130221316 | FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 08-29-2013 |
| 20130228735 | INTERFACIAL OXIDE USED AS SWITCHING LAYER IN A NONVOLATILE RESISTIVE MEMORY ELEMENT - A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments. The switching performance of a resistive memory device based on such an interfacial oxide layer is equivalent or superior to the performance of a conventional resistive memory element. | 09-05-2013 |
| 20130228736 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction. | 09-05-2013 |
| 20130228737 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises memory cells in each of which are series-connected: a variable resistance element including a metal oxide; an electrode including a polysilicon layer and a SiGe layer formed between the polysilicon layer and the metal oxide; and a bipolar type current rectifying element. | 09-05-2013 |
| 20130228738 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided. | 09-05-2013 |
| 20130228739 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film. | 09-05-2013 |
| 20130234094 | Methods and Apparatus for Resistive Random Access Memory (RRAM) - Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers. | 09-12-2013 |
| 20130234095 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a word line, a first electrode, a high resistance ion diffusion layer, a second electrode, and a bit line. The word line is made of a conductive material extending in a first direction. The first electrode is provided on the word line. The high resistance ion diffusion layer is provided on the first electrode. The second electrode is provided on the ion diffusion layer and configured to supply a metal into the ion diffusion layer upon application of a positive voltage relative to the first electrode. The bit line is provided on the second electrode and made of a conductive material extending in a second direction orthogonal to the first direction. The ion diffusion layer contains oxygen at a higher concentration on the word line side than on the bit line side. | 09-12-2013 |
| 20130234096 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THE SAME - A diode layer includes a first impurity semiconductor layer that includes a first impurity acting as an acceptor and a second impurity semiconductor layer that includes a second impurity acting as a donor. One end of a first electrode layer contacts the diode layer. One end of a polysilicon layer contacts the other end of the first electrode layer. One end of a variable resistance layer contacts the other end of the polysilicon layer and is able to change a resistance value. A second electrode layer contacts the other end of the variable resistance layer. At least one of a first area and a second area contains a third impurity. The first area includes one end of the polysilicon layer, the second area includes the other end of the polysilicon layer. The third impurity differs from the first impurity and the second impurity. | 09-12-2013 |
| 20130234097 | NONVOLATILE RESISTANCE CHANGE ELEMENT - According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a first layer and a second layer. The second electrode contains at least one metal element selected from Ag, Cu, Ni, Co, Al, and Ti. The first layer is arranged between the first electrode and the second electrode. The second layer is arranged between the first electrode and the first layer. A diffusion coefficient of the metal element in the second layer is larger than a diffusion coefficient of the metal element in the first layer. | 09-12-2013 |
| 20130234098 | Memory Diodes - A memory cell ( | 09-12-2013 |
| 20130234099 | NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME - Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide. | 09-12-2013 |
| 20130234100 | NONVOLATILE MEMORY CELLS HAVING PHASE CHANGEABLE PATTERNS THEREIN FOR DATA STORAGE - Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction. | 09-12-2013 |
| 20130234101 | NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF - A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced. | 09-12-2013 |
| 20130240821 | THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME - Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line. | 09-19-2013 |
| 20130240822 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile memory device includes a first film layer formed on a substrate, and a second film layer formed on the first film layer. The second film layer comprises a first oxide material having a first oxygen content, and a second oxide material disposed laterally of the first oxide material and having a second oxygen content that is greater than the first oxygen content. The memory device also includes a third film layer formed on the second film layer, and the third film layer is disposed on the first oxide material and exposes portions of the second oxide material. | 09-19-2013 |
| 20130240823 | NON-VOLATILE MEMORY INCLUDING MULTILAYER MEMORY CELLS AND METHOD OF FABRICATING THE SAME - A non-volatile memory and a method of fabricating the same, more particularly, a non-volatile memory in which memory cells each includes an anti-fuse and a diode or a variable resistor and a diode are stacked in a multilayer laminate structure without increasing a horizontal area, to effectively utilize a vertical space and thereby significantly increase a degree of integration so that the memory cells are able to be highly integrated and perform high-speed operation, and a method of fabricating the non-volatile memory. | 09-19-2013 |
| 20130240824 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device capable of implementing a multi-level cell (MLC) and a fabrication method thereof are provided. The resistive memory device includes a lower electrode connected to a switching device and including a first node and a second node formed on a top thereof to be spaced at a fixed interval, a phase-change material pattern formed on the first node and the second node, an upper electrode formed on the phase-change material pattern, a conductive material layer formed on a top and outer sidewall of the upper electrode, a first contact plug formed on one edge of the upper electrode to be connected to the upper electrode and the conductive material layer, and a second contact plug formed on the other edge of the upper electrode to be connected to the upper electrode and the conductive material layer. | 09-19-2013 |
| 20130240825 | NONVOLATILE VARIABLE RESISTANCE ELEMENT AND METHOD OF MANUFACTURING THE NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, a first electrode, a second electrode, and a variable resistance layer are provided. The variable resistance layer is arranged between the first electrode and the second electrode and contains a polycrystalline semiconductor as a main component. | 09-19-2013 |
| 20130240826 | Resistive Memory Cells and Devices Having Asymmetrical Contacts - A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide. | 09-19-2013 |
| 20130240827 | Integrated Circuitry, Switches, and Methods of Selecting Memory Cells of a Memory Device - Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells. | 09-19-2013 |
| 20130248801 | SEMICONDUCTOR MEMORY DEVICE WITH RESISTANCE CHANGE FILM AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of insulating layers, a plurality of first interconnection layers, a plurality of second interconnection layers, a plurality of memory cells, and a resistance change film. The insulating layers and first interconnection layers are arranged in parallel with the semiconductor substrate. The second interconnection layers are arranged so as to intersect the first interconnection layers. The second interconnection layers are arranged perpendicular to the semiconductor substrate. The memory cells are arranged at intersections of the first and second interconnection layers. Each of the memory cells includes the resistance change film arranged between the first and second interconnection layers. The side of the first interconnection layer in contact with the resistance change film is retreated more in a direction to separate from the second interconnection layer than the side of the insulating layer. | 09-26-2013 |
| 20130248802 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistive memory device includes a bit line, a word line, first electrodes and second electrodes, which are respectively arrayed in different directions, wherein a unit cell including a variable resistive material layer interposed between the first electrode and the second electrode is located at every intersection between the first electrode and the second electrode. | 09-26-2013 |
| 20130248803 | MOLECULAR MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a molecular memory includes a first electrode, a second electrode, and a resistance-change molecular chain provided between the first electrode and the second electrode. The first electrode includes a core made of a first conductive material, and a side wall made of a second conductive material different from the first conductive material. The side wall is formed on a side surface of the core. The second electrode is made of a third conductive material different from the first conductive material. The resistance-change molecular chain is bonded to the first conductive material. | 09-26-2013 |
| 20130248804 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THE SAME - A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The variable resistance layer is provided above the first conductive layer. The electrode layer contacts an upper surface of the variable resistance layer. The first liner layer contacts the upper surface of the electrode layer. The stopper layer contacts the upper surface of the first liner layer. The second conductive layer is provided above the stopper layer. The first liner layer is made of a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. | 09-26-2013 |
| 20130248805 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE HAVING MULTI-LEVELS AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device and a method of manufacturing the same. The PCRAM includes a heating electrode having an upper surface protruding in a stepped shape and a phase-change material layer formed in a phase-change space on the heating electrode, the phase-change material layer having a plurality of portions having thicknesses corresponding to the stepped shape of the heating electrode. | 09-26-2013 |
| 20130248806 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device includes a first electrode, a second electrode, a first variable resistance layer formed over the first electrode and including at least two kinds of metal oxides, and a second variable resistance layer interposed between the first variable resistance layer and the second electrode and including a metal oxide. | 09-26-2013 |
| 20130248807 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes a first and second conductive unit and a memory layer. The memory layer is provided between the first conductive unit and the second conductive unit. The memory layer includes a material expressed by (M11−uM2u)xX+yα+zβ (M1 and M2 include at least one selected from the group consisting of Mg, Al, Sc, Y, Ga, Ti, Zr, Hf, Si, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Nb, Ta, Mo, W, Ru, Rh, Ca, Sr, Ba, and Ln (a lanthanoid element), X includes at least one of O and N, α includes at least one of Li, Na, K, Rb, Cs, and Fr, β includes at least one of F, Cl, Br, and I, 0.1≦x≦1.1, 0.0001≦y≦0.2, 0.9≦y/z≦1.1). | 09-26-2013 |
| 20130248808 | RESISTANCE CHANGE ELEMENT AND NONVOLATILE MEMORY DEVICE - A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer. | 09-26-2013 |
| 20130248809 | VARIABLE RESISTIVE ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - As for a variable resistive element including first and second electrodes, and a variable resistor containing a metal oxide between the first and second electrodes, in a case where a current path having a locally high current density of a current flowing between the both electrodes is formed in the metal oxide, and resistivity of at least one specific electrode having higher resistivity of the both electrodes is 100 μΩcm or more, a dimension of a contact region of the specific electrode with the variable resistor in a short side or short axis direction is set to be more than 1.4 times as long as a film thickness of the specific electrode, which reduces variation in parasitic resistance generated in an electrode part due to process variation of the electrode, and prevents variation in resistance change characteristics of the variable resistive element generated due to the variation in parasitic resistance. | 09-26-2013 |
| 20130248810 | MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME - A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer. | 09-26-2013 |
| 20130248811 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode. | 09-26-2013 |
| 20130248812 | SYSTEMS AND METHODS FOR FABRICATING SELF-ALIGNED MEMORY CELL - Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr | 09-26-2013 |
| 20130248813 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device including a variable resistance element in which a parasitic resistance between the lower electrode and the variable resistance layer included in the variable resistance element is reduced. The nonvolatile semiconductor memory device includes: a substrate; and a variable resistance element formed on the substrate, wherein the variable resistance element includes a lower electrode layer formed on the substrate, a variable resistance layer formed on the lower electrode layer, and an upper electrode layer formed on the variable resistance layer, the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer. | 09-26-2013 |
| 20130256622 | STORAGE DEVICE AND STORAGE UNIT - A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer includes a chalcogen element, oxygen, and one or more transition metal elements selected from the group of Groups 4, 5, and 6 elements of the Periodic Table. | 10-03-2013 |
| 20130256623 | NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - The present invention provides a nonvolatile memory element, in a nonvolatile memory element having a variable resistance layer possessing a stacked structure, in which the variable resistance layer has a high resistance change ratio, and a method of manufacturing the same. The nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, and a variable resistance layer which is interposed between the first electrode and second electrode and in which the resistance value changes into at least two different resistance states. The variable resistance layer possesses a stacked structure having a first metal oxide layer containing Hf and O, and a second metal oxide layer that is provided between the first metal oxide layer and at least one of the first electrode and the second electrode and contains Al and O. | 10-03-2013 |
| 20130256624 | ELECTRODES FOR RESISTANCE CHANGE MEMORY DEVICES - Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed. | 10-03-2013 |
| 20130264535 | RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion. | 10-10-2013 |
| 20130270505 | MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY, INCLUDING A LAYER OF DOPED CHALCOGENIDE THAT WITHSTANDS HIGH TEMPERATURES - A microelectronic device with programmable memory ( | 10-17-2013 |
| 20130270506 | NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory includes a word line extending in a first direction, a first electrode connected to the word line electrically, an ion diffusion layer with connected to the first electrode electrically, a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto, and a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically. The ion diffusion layer has a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, and the metal is more difficult to diffuse into the second region than into the first region. | 10-17-2013 |
| 20130270507 | VARIABLE RESISTANCE MEMORY DEVICES AND METHOD OF FORMING THE SAME - A variable resistance memory device includes a lower electrode on a substrate, a variable resistance pattern on the lower electrode, and an upper electrode on the variable resistance pattern. The upper electrode is in contact with at least a sidewall of the variable resistance pattern. | 10-17-2013 |
| 20130270508 | Non-Volatile Memory Device and Method of Forming the Same - According to embodiments of the present invention, a non-volatile memory device is provided. The non-volatile memory device includes a nanowire transistor including a nanowire channel, and a resistive memory cell arranged adjacent to the nanowire transistor and in alignment with a longitudinal axis of the nanowire channel. According to further embodiments of the present invention, a method of forming a non-volatile memory device is also provided. | 10-17-2013 |
| 20130270509 | RESISTANCE CHANGE MEMORY DEVICE HAVING THRESHOLD SWITCHING AND MEMORY SWITCHING CHARACTERISTICS, METHOD OF FABRICATING THE SAME, AND RESISTANCE CHANGE MEMORY DEVICE INCLUDING THE SAME - Disclosed are a resistance change memory device, a method of fabricating the same, and a resistance change memory array including the same. The resistance change memory device includes a first electrode and a second electrode. A hybrid switching layer is interposed between the first electrode and the second electrode. The hybrid switching layer is a metal oxide layer having both threshold switching characteristics and memory switching characteristics. | 10-17-2013 |
| 20130277637 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device has memory cells that are operated by Joule's heat and which are highly thermally efficient. Conductive patterns are formed on a substrate; sacrificial patterns exposing a portion of the top surface of each of the conductive patterns are formed on the conductive patterns, lower electrodes are formed by etching upper portions of the conductive patterns using the sacrificial patterns as an etching mask, then mold patterns are formed on the lower electrodes and cover exposed sidewall surfaces of the sacrificial patterns, and then the sacrificial patterns are replaced with variable resistance patterns. | 10-24-2013 |
| 20130277638 | Memristive Element and Electronic Memory Based on Such Elements - The invention relates to a memristive element (M) formed by: a first electrode ( | 10-24-2013 |
| 20130285001 | METHODS FOR FORMING A NANOWIRE AND APPARATUS THEREOF - A system that incorporates teachings of the subject disclosure may include, for example, a method for depositing a first material that substantially covers a nanoheater, applying a signal to the nanoheater to remove a first portion of the first material covering the nanoheater to form a trench aligned with the nanoheater, depositing a second material in the trench, and removing a second portion of the first material and a portion of the second material to form a nanowire comprising a remaining portion of the second material covering the nanoheater along the trench. Additional embodiments are disclosed. | 10-31-2013 |
| 20130285002 | Phase Change Memory Cells And Methods Of Forming Phase Change Memory Cells - A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed. | 10-31-2013 |
| 20130285003 | Phase Change Memory Cells And Methods Of Forming Phase Change Memory Cells - A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between. | 10-31-2013 |
| 20130285004 | SOLID ELECTROLYTE MEMORY ELEMENTS WITH ELECTRODE INTERFACE FOR IMPROVED PERFORMANCE - A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element. | 10-31-2013 |
| 20130285005 | VARIABLE RESISTIVE ELEMENT, METHOD FOR PRODUCING THE SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING THE VARIABLE RESISTIVE ELEMENT - A variable resistive element configured to reduce a forming voltage while reducing a variation in forming voltage among elements, a method for producing it, and a highly integrated nonvolatile semiconductor memory device provided with the variable resistive element are provided. The variable resistive element includes a resistance change layer (first metal oxide film) and a control layer (second metal oxide film) having contact with a first electrode sandwiched between the first electrode and a second electrode. The control layer includes a metal oxide film having a low work function (4.5 eV or less) and capable of extracting oxygen from the resistance change layer. The first electrode includes a metal having a low work function similar to the above metal, and a material having oxide formation free energy higher than that of an element included in the control layer, to prevent oxygen from being thermally diffused from the control layer. | 10-31-2013 |
| 20130292629 | PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF - The present invention provides a phase change memory cell and fabrication method thereof, wherein said phase change memory cell comprises a semiconductor substrate, a first electrode layer, a phase change material layer, a second electrode layer and an extraction electrode, as well as a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process, and wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer and can be used to prevent phase change material layer from over-corrosion during the chemical mechanical polishing process and thus enhance the memory performance and the yield of phase change memory cell. | 11-07-2013 |
| 20130292630 | SEMICONDUCTOR MEMORY DEVICE - The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. | 11-07-2013 |
| 20130292631 | Multi-Layered Phase-Change Memory Device - The invention discloses a phase-change memory device structure and the materials used. The structure includes a substrate; a single or multiple sandwich-memory-unit(s); a first and a second electrode electrically connecting to the first and the second sides of the sandwich-memory-units and a dielectric layer used as the insulator required by the memory device. The sandwich-memory-unit composes of a memory-layer, thinner than 30 nm, sandwiched between an upper and a lower barrier-layers. The barrier-layer is either an electrical conductor in case of vertical memory-cells or an electrical insulator in case of parallel memory-cells. The sandwich-memory-unit is characteristic of increased crystallization temperature of at least 50° C. as the thickness of the memory-layer is reduced from 15 to 5 nm; and the volume change of the memory-layer is less than 3% during phase change. The thickness and memory-material in each sandwich-memory-unit can be different in the multiple sandwich-memory-units. | 11-07-2013 |
| 20130292632 | Resistive Switching Memory Element Including Doped Silicon Electrode - A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa. | 11-07-2013 |
| 20130299769 | LINE AND SPACE ARCHITECTURE FOR A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region. | 11-14-2013 |
| 20130299770 | RESISTIVE MEMORY DEVICE - A resistive memory device includes: a memory cell comprising first and second electrodes and a resistive layer formed therebetween, wherein the resistive layer is formed of a resistance change material; and a strained film formed adjacent to the resistive layer and configured to apply a strain to the resistive layer. | 11-14-2013 |
| 20130306928 | ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION - Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation. | 11-21-2013 |
| 20130306929 | Multilayer-Stacked Phase Change Memory Cell - A multilayer-stacked phase change memory (PCM) device is provided that includes a substrate that is electrically insulative and thermally conductive, a number (n) of PCM layers deposited on the substrate, where each PCM layer is thicker than a previous PCM layer, a number (n−1) layers of passivation layer deposited between the PCM layers, where the (n) PCM layers, and the (n−1) passivation layers form a stacked multi-layer PCM on the substrate, a first electrode deposited on a first side of the multi-layer PCM stack, and a second electrode deposited on a second side of the multi-layer PCM stack, where the first side is opposite the second side, where charge transport is decoupled by stacking the PCM layers with the pasivation layers. | 11-21-2013 |
| 20130306930 | Memory Cells - Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell. | 11-21-2013 |
| 20130306931 | Sidewall Thin Film Electrode with Self-Aligned Top Electrode and Programmable Resistance Memory - A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces. | 11-21-2013 |
| 20130306932 | NONVOLATILE RESISTANCE CHANGE ELEMENT - According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co. | 11-21-2013 |
| 20130313504 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device capable of suppressing disturbance between cells and a fabrication method thereof are provided. The resistive memory device includes a word line formed, in a first direction, on a semiconductor substrate, lower access structures, each having a pillar shape, formed on the word line, a first insulating layer formed around an outer circumference of each of the lower access structures, a heat-absorption layer formed on a surface of each of the to heat-absorption layers, a variable resistive material formed on the lower access structures, and an upper electrode formed on each variable resistive material. | 11-28-2013 |
| 20130313505 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A memory cell is provided that includes a semiconductor pillar and a reversible resistance-switching element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region includes a first proportion of germanium greater than a proportion of germanium in the top region and/or the bottom region. The reversible resistivity-switching element includes a material selected from the group consisting of NiO, Nb | 11-28-2013 |
| 20130313506 | MAGNETORESISTIVE ELEMENT AND MANUFACTURING METHOD OF THE SAME - A magnetoresistive element has a magnetic layer, an insulating layer and a magnetic layer, which are laminated on a base electrode, and side walls of the magnetic layers that are formed when the magnetic layers are processed. At least one element selected from the group of consisting He, C, N, O, F, Ne, Ti, V, Cu, Al, Si, P, S, Cl, Ar, Ge, As, Kr, Zr, In, Sn, Sb, Pb and Bi is injected into the side walls and edge portions of the magnetic layers to improve the magnetic characteristics of the first and second magnetic layers. | 11-28-2013 |
| 20130313507 | RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode. | 11-28-2013 |
| 20130313508 | VARIABLE RESISTANCE MEMORY AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory according to an embodiment includes: a first wiring; a second wiring provided above the first wiring and intersecting with the first wiring; a third wiring provided above the second wiring and intersecting with the second wiring; a first variable resistance element provided in an intersection region between the first wiring and the second wiring, the first variable resistance element including a first variable resistance layer formed on the first wiring, and an ion source electrode provided on the first variable resistance layer and penetrating through the second wiring, the ion source electrode being connected to the second wiring and including a metal atoms; and a second variable resistance element provided in an intersection region between the second wiring and the third wiring, the second variable resistance element including a second variable resistance layer formed on the ion source electrode. | 11-28-2013 |
| 20130313509 | Bipolar Multistate Nonvolatile Memory - Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 11-28-2013 |
| 20130313510 | MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE - Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess. | 11-28-2013 |
| 20130320288 | Semiconductor Constructions and Memory Arrays - Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays. | 12-05-2013 |
| 20130320289 | RESISTANCE RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME - A resistance random access memory including a first electrode layer, a second electrode layer, and a stacked structure is provided. The stacked structure includes a HfZrON layer and a ZrON layer and is located between the first electrode layer and the second electrode layer. In addition, the disclosure further provides a method of fabricating a resistance random access memory. | 12-05-2013 |
| 20130320290 | PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit. | 12-05-2013 |
| 20130320291 | SEMICONDUCTOR STRUCTURES AND MEMORY CELLS INCLUDING CONDUCTIVE MATERIAL AND METHODS OF FABRICATION - Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed. | 12-05-2013 |
| 20130328007 | NON-VOLATILE SOLID STATE RESISTIVE SWITCHING DEVICES - Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer. | 12-12-2013 |
| 20130328008 | NONVOLATILE RESISTANCE CHANGE ELEMENT - According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart. | 12-12-2013 |
| 20130328009 | NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer. | 12-12-2013 |
| 20130334486 | STRUCTURE AND METHOD FOR A COMPLIMENTARY RESISTIVE SWITCHING RANDOM ACCESS MEMORY FOR HIGH DENSITY APPLICATION - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer including a defect engineering film; and a top electrode on the resistive material layer. | 12-19-2013 |
| 20130334487 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, second conductive layers disposed on sidewalls of the resistance change elements, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction, a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space, and a third conductive layer functioning as a second bit line extending in the first direction by filling the second space. | 12-19-2013 |
| 20130334488 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed its on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions. | 12-19-2013 |
| 20130334489 | STORAGE DEVICE AND STORAGE UNIT - A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive. | 12-19-2013 |
| 20130334490 | Transition Metal Oxide Bilayers - Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen. | 12-19-2013 |
| 20130334491 | Methods for Forming Nickel Oxide Films for Use With Resistive Switching Memory Devices - Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH) | 12-19-2013 |
| 20130341583 | RESISTIVE MEMORY AND FABRICATING METHOD THEREOF - A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode. | 12-26-2013 |
| 20130341584 | Resistive-Switching Memory Elements Having Improved Switching Characteristics - Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness. | 12-26-2013 |
| 20130341585 | VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR STORAGE DEVICE - A variable resistance element is formed by sandwiching a metal oxide layer whose resistance changes between a pair of electrodes and the metal oxide layer includes a pair of variable resistance layers whose resistances change by formation of a current path and a branching suppression layer which is sandwiched between the variable resistance layers and suppresses branching of the current path. | 12-26-2013 |
| 20130341586 | Memory Structures, Memory Arrays, Methods of Forming Memory Structures and Methods of Forming Memory Arrays - Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays. | 12-26-2013 |
| 20140001431 | Reduction of forming voltage in semiconductor devices | 01-02-2014 |
| 20140008602 | THERMAL ISOLATION IN MEMORY CELLS - Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm). | 01-09-2014 |
| 20140008603 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device has a memory cell including a resistance change layer, a first electrode, and a second electrode. The resistance change layer switches between high and low resistance states due to the transfer of metal ions from the first electrode in response to voltages applied between the electrodes. The first electrode is formed on a first side of the resistance change layer, and provides metal ions. The second electrode is formed on a second side of the resistance change layer. A memory cell region is formed between the first electrode and the second electrode with the resistance change layer. The memory device also includes a high permittivity layer with a higher dielectric constant than the resistance change layer. | 01-09-2014 |
| 20140014893 | ARRAY OPERATION USING A SCHOTTKY DIODE AS A NON-OHMIC SELECTION DEVICE - A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 01-16-2014 |
| 20140021431 | Semiconductor Constructions, Memory Cells, Memory Arrays and Methods of Forming Memory Cells - Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells. | 01-23-2014 |
| 20140021432 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a variable resistance memory device includes forming an insulating layer having a trench extending in a first direction over a substrate, forming first electrode conductive layers on both sidewalls of the trench, forming island-shaped first electrodes by patterning the conductive layers in a second direction crossing the first direction, forming variable resistance patterns over the first electrodes, and forming second electrodes over the variable resistance patterns. | 01-23-2014 |
| 20140021433 | MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY - A microelectronic device with programmable memory is provided having at least: a first electrode ( | 01-23-2014 |
| 20140021434 | MEMORY ELEMENT AND MEMORY DEVICE - A memory element and a memory device, the memory element including a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer provided on the second electrode side and is higher in resistance value than the resistance change layer. A resistance value of the resistance change layer is changeable in response to a composition change by applied voltage to the first and second electrodes | 01-23-2014 |
| 20140021435 | PHASE CHANGE CURRENT DENSITY CONTROL STRUCTURE - A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers. | 01-23-2014 |
| 20140021436 | SEMICONDUCTOR MEMORY DEVICE - A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio. | 01-23-2014 |
| 20140021437 | RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode. | 01-23-2014 |
| 20140021438 | ORGANIC MOLECULAR MEMORY AND METHOD OF MANUFACTURING THE SAME - An organic molecular memory for controlling a current flowing through a memory cell and achieving stable operation and high degree of reliability is provided. The organic molecular memory includes a first electrode, a second electrode made of a material different from the first electrode, and an organic molecule layer provided between the first electrode and the second electrode, wherein one end of a resistance change-type molecular chain constituting the organic molecule layer is chemically bonded with the first electrode, and an air gap exists between the other end of the resistance change-type molecular chain and the second electrode. | 01-23-2014 |
| 20140027701 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively. | 01-30-2014 |
| 20140027702 | MULTIFUNCTIONAL ZINC OXIDE NANO-STRUCTURE-BASED CIRCUIT BUILDING BLOCKS FOR RE-CONFIGURABLE ELECTRONICS AND OPTOELECTRONICS - A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed. | 01-30-2014 |
| 20140027703 | VARIABLE RESISTIVE ELEMENT, AND ITS MANUFACTURING METHOD - A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element. | 01-30-2014 |
| 20140027704 | METHODS OF FORMING PHASE-CHANGE MEMORY DEVICES AND DEVICES SO FORMED - Phase-change memory devices are provided. A phase-change memory device may include a substrate and a conductive region on the substrate. Moreover, the phase-change memory device may include a lower electrode on the conductive region. The lower electrode may include a metal silicide layer on the conductive region, and a metal silicon nitride layer including a resistivity of about 10 to about 100 times that of the metal silicide layer. Moreover, the lower electrode may include a metal oxide layer between the metal silicon nitride layer and the metal silicide layer. The metal oxide layer may include a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. The phase-change memory device may also include a phase-change layer and an upper electrode on the lower electrode. | 01-30-2014 |
| 20140034897 | METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT - Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion. | 02-06-2014 |
| 20140034898 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 02-06-2014 |
| 20140042382 | SIDEWALL DIODE DRIVING DEVICE AND MEMORY USING SAME - A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element. | 02-13-2014 |
| 20140042383 | MANUFACTURING METHOD OF NON-VOLATILE STORAGE DEVICE, AND NON-VOLATILE STORAGE DEVICE - A manufacturing method includes forming a laminated body on a substrate. A mask layer is formed on the laminated body, and then a portion of the mask layer is removed to form an opening. Then, using the mask layer as a template, a first portion of the laminated body is removed to expose a portion of the substrate beneath the laminated body. The substrate is processed to alter the ratio between the size of mask opening and the removed first portion. A variable resistance layer is then deposited on exposed portions of the mask layer, the laminated body, and the substrate. Then the variable resistance layer is processed to remove at least a portion covering the substrate to permit contact with the underlying substrate. A second electrode layer is deposited to fill the removed portions of the laminated body. | 02-13-2014 |
| 20140042384 | Resistive-Switching Nonvolatile Memory Elements - Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 02-13-2014 |
| 20140048762 | PHASE CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 02-20-2014 |
| 20140054534 | SELF-ALIGNED INTERCONNECTION FOR INTEGRATED CIRCUITS - Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device. | 02-27-2014 |
| 20140054535 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE - A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate. | 02-27-2014 |
| 20140054536 | RESISTIVE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer. | 02-27-2014 |
| 20140054537 | RESISTIVE MEMORY DEVICE CAPABLE OF PREVENTING DISTURBANCE AND METHOD FOR MANUFACTURING THE SAME - A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof. | 02-27-2014 |
| 20140061568 | RESISTIVE MEMORY DEVICES - Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed. | 03-06-2014 |
| 20140061569 | FLEXIBLE NON-VOLATILE MEMORY - A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells. | 03-06-2014 |
| 20140061570 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a first electrode, a first resistance change layer, a first insulating section, a second electrode and an intermediate layer. The first resistance change layer is provided on the first electrode. The first insulating section is provided on the first resistance change layer. The second electrode is provided on the first resistance change layer. The second electrode is in contact with the first resistance change layer. The intermediate layer is provided between the second electrode and the first insulating section. The intermediate layer is in contact with the second electrode and the first insulating section. | 03-06-2014 |
| 20140061571 | RESISTIVE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode. | 03-06-2014 |
| 20140061572 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This technology relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include a line layer formed over a substrate, and connection structures each configured to include a first metal layer pattern, a barrier layer pattern, and a second metal layer pattern sequentially stacked over the line layer, for bonding another substrate to the substrate. In accordance with this technology, abnormal silicidation may be prevented because the barrier layer is formed at the bonding interface of the substrates, and the bonding energy of the substrates may be improved by titanium (Ti)-silicon (Si) bonding. | 03-06-2014 |
| 20140061573 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING THE SAME - A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer. The second variable resistance layer is formed to cover the step and have, above the step, a bend covering the step. The bend, seen from above, has only one corner in a surface of the second variable resistance layer. | 03-06-2014 |
| 20140070159 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 03-13-2014 |
| 20140070160 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I. | 03-13-2014 |
| 20140070161 | MEMORY DEVICE - According to one embodiment, a memory device includes a first interconnect, a second interconnect and a pillar connected between the first interconnect and the second interconnect. The pillar includes a first high-resistance layer, a second high-resistance layer, and a metal layer. The first high-resistance layer is connected to the first interconnect. A resistivity of the first high-resistance layer is higher than a resistivity of the first interconnect and a resistivity of the second interconnect. The second high-resistance layer is connected to the second interconnect. A resistivity of the second high-resistance layer is higher than the resistivity of the first high-resistance layer. A thickness of the second high-resistance layer is not more than a thickness of the first high-resistance layer. The metal layer is disposed between the first high-resistance layer and the second high-resistance layer. The metal layer includes a metal. | 03-13-2014 |
| 20140070162 | RESISTANCE CHANGE TYPE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a memory includes a resistance change element on an interlayer insulating film and including a lower electrode and an upper electrode, a sidewall insulating film on a side surface of the element, a plug in the interlayer insulating film and connected to the lower electrode, an interconnect on the interlayer insulating film and connected to the upper electrode. The element is provided immediately above the plug, the interconnect covers the side surface of the element via the sidewall insulating film, an upper surface of the first plug is covered with the lower electrode and the sidewall insulating film. | 03-13-2014 |
| 20140070163 | PHASE-CHANGE MEMORY CELL - A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical. | 03-13-2014 |
| 20140077147 | Methods For Selective Etching Of A Multi-Layer Substrate - A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO | 03-20-2014 |
| 20140077148 | RRAM CELL WITH BOTTOM ELECTRODE(S) POSITIONED IN A SEMICONDUCTOR SUBSTRATE - Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. | 03-20-2014 |
| 20140084237 | DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE - Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. | 03-27-2014 |
| 20140091270 | LOW ENERGY MEMRISTORS WITH ENGINEERED SWITCHING CHANNEL MATERIALS - Low energy memristors with engineered switching channel materials include: a first electrode; a second electrode; and a switching layer positioned between the first electrode and the second electrode, wherein the switching layer includes a first phase comprising an insulating matrix in which is dispersed a second phase comprising an electrically conducting compound material for forming a switching channel. | 04-03-2014 |
| 20140091271 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. A portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer. | 04-03-2014 |
| 20140091272 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material. | 04-03-2014 |
| 20140091273 | RESISTIVE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line. | 04-03-2014 |
| 20140091274 | MEMORY DEVICES HAVING UNIT CELL AS SINGLE DEVICE AND METHODS OF MANUFACTURING THE SAME - In one embodiment, a memory device includes a first electrode layer on a substrate; a data storing layer on the first electrode layer; and a second electrode layer on the data storing layer. At least one of the first and second electrode layers may be formed of a material having a conduction band offset that varies with an applied voltage. One of the first and second electrode layers may be connected to a bit line and the other may be connected to a word line. The first electrode layer may include one of graphene and metastable oxide. The second electrode layer may include one of graphene and metastable oxide. | 04-03-2014 |
| 20140097397 | RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device includes a first electrode layer, a second electrode layer, and a first variable resistive layer and a second variable resistive layer stacked at least once between the first electrode layer and the second electrode layer. The first variable resistive material layer may include a metal nitride layer having a resistivity higher than that of the first electrode layer or the second electrode layer and less than or equal to that of an insulating material. | 04-10-2014 |
| 20140097398 | MEMRISTIVE DEVICES AND MEMRISTORS WITH RIBBON-LIKE JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area. | 04-10-2014 |
| 20140097399 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions. | 04-10-2014 |
| 20140097400 | VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION - A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 04-10-2014 |
| 20140103281 | Resistive Memory Based on TaOx Containing Ru Doping and Method of Preparing the Same - The present invention pertains to the technical field of semi-conductor memory. More particularly, the invention relates to a resistive memory based on TaO | 04-17-2014 |
| 20140103282 | Diffusion Barrier Layer for Resistive Random Access Memory Cells - Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers. | 04-17-2014 |
| 20140103283 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a variable resistance memory device and a method of fabricating the same. The variable resistance memory device may include a first electrode; a second electrode; and a variable resistance layer configured to be interposed between the first electrode and the second electrode, wherein the variable resistance layer includes a Si-added metal oxide. | 04-17-2014 |
| 20140103284 | ReRAM Cells Including TaXSiYN Embedded Resistors - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer. | 04-17-2014 |
| 20140103285 | Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material - Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide. | 04-17-2014 |
| 20140110657 | MEMORY CONSTRUCTIONS - Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors. | 04-24-2014 |
| 20140110658 | MEMORY CONSTRUCTIONS COMPRISING THIN FILMS OF PHASE CHANGE MATERIAL - Some embodiments include memory constructions having a film of phase change material between first and second materials; with the entirety of film having a thickness of less than or equal to about 10 nanometers. The memory constructions are configured to transit from one memory state having a first phase of the phase change material to a second memory state having a second phase of the phase change material, and are configured so that an entirety of the phase change material film changes from the first phase to the second phase in transitioning from the first memory state to the second memory state. In some embodiments, at least one of the first and second materials may be carbon, W, TiN, TaN or TiAlN. In some embodiments, at least one of the first and second materials may be part of a structure having bands of two or more different compositions. | 04-24-2014 |
| 20140110659 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer. | 04-24-2014 |
| 20140110660 | NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES - A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another. | 04-24-2014 |
| 20140117301 | WRAP AROUND PHASE CHANGE MEMORY - A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element. | 05-01-2014 |
| 20140117302 | Phase Change Memory Cells, Methods Of Forming Phase Change Memory Cells, And Methods Of Forming Heater Material For Phase Change Memory Cells - A phase change memory cell includes a pair of electrodes having phase change material and heater material there-between. An electrically conductive thermal barrier material is between one of the electrodes and the heater material. Methods are disclosed. | 05-01-2014 |
| 20140117303 | Resistive Random Access Memory Cells Having METAL ALLOY Current Limiting layers - Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance. | 05-01-2014 |
| 20140117304 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element. | 05-01-2014 |
| 20140117305 | NON-VOLATILE MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A non-volatile memory element including a first electrode; a second electrode; and a variable resistance layer. The variable resistance layer including, when a first metal is M and a second metal is N, a third metal oxide layer NO | 05-01-2014 |
| 20140124725 | Resistive Random Access Memory Cells Having Doped Current Limiting layers - Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance. | 05-08-2014 |
| 20140124726 | PHASE-CHANGE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Provided are a phase-change memory device and a method of fabricating the same. The device may include memory cells provided at intersections of word lines and bit lines that extend along first and second directions crossing each other, and a mold layer including thermal insulating regions, such as air gaps, that may be provided between the memory cells to separate the memory cells from each other. Each of the memory cells may include a lower electrode electrically connected to the word line to have a first width in the first direction, an upper electrode electrically connected to the bit line to have a second width greater than the first width in the first direction, and a phase-change layer provided between the lower and upper electrodes to have the first width in the first direction. | 05-08-2014 |
| 20140124727 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. | 05-08-2014 |
| 20140131650 | RESISTANCE VARIABLE MEMORY STRUCTURE - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 05-15-2014 |
| 20140131651 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
| 20140131652 | MAGNETORESISTIVE TUNNEL JUNCTION - A Magnetoresistive Tunnel Junction (MTJ) includes a magnetic reference layer disposed between a first electrode and a resistive layer. The junction also includes a magnetic free layer disposed between the resistive layer and a second electrode. The surface area of the free layer is less than the surface area of the reference layer. | 05-15-2014 |
| 20140131653 | UNIPOLAR PROGRAMMABLE METALLIZATION CELL - A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates. | 05-15-2014 |
| 20140131654 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
| 20140138603 | COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL - A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines. | 05-22-2014 |
| 20140138604 | METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME - In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material. | 05-22-2014 |
| 20140138605 | COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY - An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. | 05-22-2014 |
| 20140138606 | RESISTANCE VARIABLE MEMORY DEVICE - Embodiments relate to a resistance variable memory device and a method for forming the same. The resistance variable memory device may include a first electrode, a second electrode spaced apart from the first electrode, a first resistance variable pattern provided over the first electrode and surrounding a lower portion of the second electrode, and a spacer surrounding a sidewall of the first resistance variable pattern. According to embodiments, the resistance variable pattern can be prevented from being damaged in an etching process and an air gap surrounding a portion of the electrode may contribute to improve reliability and an operational speed of the resistance variable memory device. | 05-22-2014 |
| 20140138607 | NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile memory device comprises first wires on and above a first plane; second wires extending in a direction crossing the first wires, on and above a second plane, third wires extending in parallel with the second wires on and above a fourth plane, and memory cells provided to correspond to three-dimensional cross-points of the first wires and the third wires, respectively, each of the memory cells including a transistor and a variable resistance element, the transistor including a first main electrode, a second main electrode, and a control electrode, the variable resistance element being placed on and above a third plane and including a lower electrode, an upper electrode and a variable resistance layer, wherein the upper electrode is connected to corresponding one of the third wires; and further comprises a first contact plug extending from the first main electrode to the second plane and connected to corresponding one of the second wires; a second contact plug extending from the second main electrode to the second plane; and a third contact plug extending from the second contact plug and connected to the lower electrode; wherein the second main electrode and the lower electrode are connected to each other via the second contact plug and the third contact plug. | 05-22-2014 |
| 20140138608 | MEMORY CELL STRUCTURES - The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. | 05-22-2014 |
| 20140145139 | TRANSPARENT FLEXIBLE RESISTIVE MEMORY AND FABRICATION METHOD THEREOF - The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained. | 05-29-2014 |
| 20140145140 | VARIABLE RESISTANCE MEMORY DEVICE - The present invention relates to a variable resistance memory device and a method for forming the same. A variable resistance memory device according to the present invention includes a first electrode; a second electrode spaced apart from the first electrode; a resistance variable layer and a metal-insulator transition layer provided between the first electrode and the second electrode; and a heat barrier layer provided (i) between the first electrode and the metal-insulator transition layer, (ii) between the metal-insulator transition layer and the resistance variable layer, or (iii) between the second electrode and the metal-insulator transition layer. The present invention prevents dissipation of heat generated in the metal-insulator transition layer using a thermal boundary resistance (TBR) phenomenon, and thus current and voltage to operate the variable resistance memory device can be reduced. | 05-29-2014 |
| 20140145141 | ELECTRONIC MEMORY DEVICE - An electronic device includes a first electrode made of an inert material; a second electrode made of a soluble material; a solid electrolyte made of an ion-conductive material, wherein the first and second electrodes are in contact respectively with one of the faces of the electrolyte, either side of the electrolyte, wherein the second electrode supplies mobile ions flowing in the electrolyte towards the first electrode, to form a conductive filament when a voltage is applied between the first and second electrodes. The second electrode is a confinement electrode that includes an end surface in contact with the electrolyte which is less than the available surface of the electrolyte, such that confinement of the contact area of the confinement electrode on the solid electrolyte is obtained. | 05-29-2014 |
| 20140145142 | MEMRISTOR STRUCTURE WITH A DOPANT SOURCE - A memristor including a dopant source is disclosed. The structure includes an electrode, a conductive alloy including a conducting material, a dopant source material, and a dopant, and a switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material. A method for fabricating the memristor including a dopant source is also disclosed. | 05-29-2014 |
| 20140151626 | Selector Device Using Low Leakage Dielectric Mimcap Diode - MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes. | 06-05-2014 |
| 20140151627 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench. | 06-05-2014 |
| 20140151628 | PHASE CHANGE MEMORIES AND FABRICATION METHOD - A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode. | 06-05-2014 |
| 20140151629 | CONFINED RESISTANCE VARIABLE MEMORY CELLS AND METHODS - Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode. | 06-05-2014 |
| 20140158966 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a variable resistance memory device includes: forming a first metal oxide layer over a first electrode; performing a first implantation process using a first element to a first depth of the first metal oxide layer so as to reduce at least a portion of the first metal oxide layer and form a first oxygen-deficient metal oxide layer; forming a second electrode over the first metal oxide layer; forming a second metal oxide layer over the second electrode; performing a second implantation process using a second element to a second depth of the second metal oxide layer so as to reduce at least a portion of the second metal oxide layer and form a second oxygen-deficient metal oxide layer; and forming a third electrode over the second metal oxide layer. | 06-12-2014 |
| 20140158967 | SELF-RECTIFYING RRAM CELL STRUCTURE AND 3D CROSSBAR ARRAY ARCHITECTURE THEREOF - The present disclosure provides a self-rectifying RRAM, including: a first electrode layer formed of a first metal element; a second electrode layer formed of a second metal element different from the first metal element; and a first resistive-switching layer and a second resistive-switching layer sandwiched between the first electrode layer and the second electrode layer, wherein the first resistive-switching layer and the second switching layer form an ohmic contact, and the first resistive-switching layer has a first bandgap lower than a second bandgap of the second resistive-switching layer. Furthermore, an RRAM 3D crossbar array architecture is also provided. | 06-12-2014 |
| 20140158968 | NOBLE METAL / NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS - A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer. | 06-12-2014 |
| 20140158969 | METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE - A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes. | 06-12-2014 |
| 20140158970 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 06-12-2014 |
| 20140158971 | PHASE CHANGE MEMORY CELLS WITH SURFACTANT LAYERS - An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. | 06-12-2014 |
| 20140158972 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials. | 06-12-2014 |
| 20140158973 | NITRIDE-BASED MEMRISTORS - A nitride-based memristor memristor includes: a first electrode comprising a first nitride material; a second electrode comprising a second nitride material; and active region positioned between the first electrode and the second electrode. The active region includes an electrically semiconducting or nominally insulating and weak ionic switching nitride phase. A method for fabricating the nitride-based memristor is also provided. | 06-12-2014 |
| 20140166960 | IL-Free MIM stack for clean RRAM Devices - A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance. | 06-19-2014 |
| 20140166961 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND METHOD OF MAKING - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer. | 06-19-2014 |
| 20140166962 | PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA - A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. | 06-19-2014 |
| 20140166963 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate. | 06-19-2014 |
| 20140166964 | PHASE-CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. The diode line and the projection are formed of a single layer to be in continuity with each other. | 06-19-2014 |
| 20140166965 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure. | 06-19-2014 |
| 20140166966 | Resistance Change Element and Method for Producing the Same - To provide a resistance change element which does not require a forming process and enables reduction of power consumption and miniaturization of the element, and to provide a method for producing it. A resistance change element | 06-19-2014 |
| 20140166967 | SMALL FOOTPRINT PHASE CHANGE MEMORY CELL - An example embodiment disclosed is a phase change memory cell in a semiconductor wafer. The semiconductor wafer includes a first metalization layer (Metal 1). The phase change memory cell includes an insulating substrate defining a non-sublithographic via. The non-sublithographic via is located on the first metalization layer and includes a bottom and a sidewall. Intermediate insulating material is positioned below the insulating substrate. The intermediate insulating material defines a sublithographic aperture passing through the bottom of the non-sublithographic via. A bottom electrode is positioned within the sublithographic aperture, and is composed of conductive non-phase change material. The non-sublithographic via includes phase change material positioned within. The phase change material is electrically coupled to the bottom electrode. A liner is positioned along the sidewall of the non-sublithographic via. The liner is electrically coupled to the phase change material and is composed of the conductive non-phase change material. | 06-19-2014 |
| 20140166968 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided. | 06-19-2014 |
| 20140166969 | NONVOLATILE MEMORY DEVICE USING A TUNNEL OXIDE AS A PASSIVE CURRENT STEERING ELEMENT - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 06-19-2014 |
| 20140166970 | PHASE CHANGE MEMORY CELL - A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface. | 06-19-2014 |
| 20140175360 | Bilayered Oxide Structures for ReRAM Cells - Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells. | 06-26-2014 |
| 20140175361 | Resistive Switching Layers Including Hf-Al-O - Provided are resistive random access memory (ReRAM) cells having switching layers that include hafnium, aluminum, oxygen, and nitrogen. The composition of such layers is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. In some embodiments, the concentration of nitrogen in a switching layer is between about 1 and 20 atomic percent or, more specifically, between about 2 and 5 atomic percent. Addition of nitrogen helps to control concentration and distribution of defects in the switching layer. Also, nitrogen as well as a combination of two metals helps with maintaining this layer in an amorphous state. Excessive amounts of nitrogen reduce defects in the layer such that switching characteristics may be completely lost. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD). | 06-26-2014 |
| 20140175362 | Limited Maximum Fields of Electrode-Switching Layer Interfaces in Re-RAM Cells - Provided are ReRAM cells, each having at least one interface between an electrode and a resistive switching layers with a maximum field value of less than 0.25. The electrode materials forming such interfaces include tantalum nitrides doped with lanthanum, aluminum, erbium yttrium, or terbium (e.g., Ta | 06-26-2014 |
| 20140175363 | Forming Nonvolatile Memory Elements By Diffusing Oxygen Into Electrodes - Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing. At least one electrode in a memory element is reactive, while another may be inert. The precursor layer is converted into a resistance switching layer as a result of this diffusion. The precursor layer may initially include a stoichiometric oxide that generally does not exhibit resistance switching characteristics until oxygen vacancies are created. Metals forming such oxides may be more electronegative than metals forming a reactive electrode. The reactive electrode may have substantially no oxygen at least prior to annealing. Annealing may be performed at 250-400° C. in the presence of hydrogen. These methods simplify process control and may be used to form nonvolatile memory elements including resistance switching layers less than 20 Angstroms thick. | 06-26-2014 |
| 20140175364 | RADIATION ENHANCED RESISTIVE SWITCHING LAYERS - Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers. | 06-26-2014 |
| 20140175365 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND METHOD OF MAKING THE RRAM STRUCTURE - The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region. | 06-26-2014 |
| 20140175366 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 06-26-2014 |
| 20140175367 | Materials for Thin Resisive Switching Layers of Re-RAM Cells - Provided are resistive random access memory (ReRAM) cells that include thin resistive switching layers. In some embodiments, the resistive switching layers have a thickness of less than about 50 Angstroms and even less than about 30 Angstroms. The resistive switching characteristics of such thin layers are maintained by controlling their compositions and using particular fabrication techniques. Specifically, low oxygen vacancy metal oxides, such as tantalum oxide, may be used. The concentration of oxygen vacancies may be less than 5 atomic percent. In some embodiments, the resistive switching layers also include nitrogen and. For example, compositions of some specific resistive switching layers may be represented by Ta | 06-26-2014 |
| 20140175368 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PRAM) device and a method of manufacturing the same are provided. The PRAM device includes a semiconductor substrate in which a switching device is formed, a lower electrode configured to be formed on the switching device and having a void formed in a portion of an upper surface thereof, and a phase-change layer configured to be formed on the lower electrode having the void. | 06-26-2014 |
| 20140175369 | MANUFACTURING METHOD OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE - A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask. | 06-26-2014 |
| 20140175370 | PHASE-CHANGE MEMORY - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 06-26-2014 |
| 20140183434 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices, and methods of fabricating the same, include a metal-containing layer on a semiconductor layer, and a barrier-lowering portion between the metal-containing layer and the semiconductor layer. The barrier-lowering portion lowers a Schottky barrier height between the metal-containing layer and the semiconductor layer below a Schottky barrier height between a metal silicide layer and the semiconductor layer. | 07-03-2014 |
| 20140183435 | SEMICONDUCTOR DEVICE HAVING DIODE AND METHOD OF FORMING THE SAME - A semiconductor device includes a conductive line, a diode on the conductive line, one or more insulating patterns adjacent to diode, and a data storage region coupled to the diode. An upper surface of the diode is between the one or more insulating patterns and the data storage region. The data storage region may include a phase-change region, and the diode may taper in width between two insulating patterns in one arrangement. | 07-03-2014 |
| 20140183436 | Nonvolatile Memory Device Having a Current Limiting Element - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 07-03-2014 |
| 20140183437 | MEMORY ELEMENT AND MEMORY DEVICE - A memory element with a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer. | 07-03-2014 |
| 20140183438 | MEMORY COMPONENT, MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICE - A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide. | 07-03-2014 |
| 20140191181 | METHOD TO MAKE RF-PCM SWITCHES AND CIRCUITS WITH PHASE-CHANGE MATERIALS - A radio frequency switch includes a first transmission line, a second transmission line, a first electrode electrically coupled to the first transmission line, a second electrode electrically coupled to the second transmission line, and a phase change material, the first transmission line coupled to a first area of the phase change material and the second transmission line coupled to a second area of the phase change material. When a direct current is sent from the first electrode to the second electrode through the phase change material, the phase change material changes state from a high resistance state to a low resistance state allowing transmission from the first transmission line to the second transmission line. The radio frequency switch is integrated on a substrate. | 07-10-2014 |
| 20140191182 | Memory Cells - Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state. | 07-10-2014 |
| 20140191183 | RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory includes a first electrode, a second electrode and a first metal oxide composite layer. The second electrode is opposite to the first electrode. The first metal oxide composite layer is disposed between the first electrode and the second electrode. The first metal oxide composite layer has a film layer and a nanorod structure. | 07-10-2014 |
| 20140191184 | NONVOLATILE VARIABLE RESISTANCE DEVICE AND METHOD OF MANUFACTURING THE NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer. | 07-10-2014 |
| 20140197369 | NANOPARTICLE-BASED MEMRISTOR STRUCTURE - A memristor structure has two electrodes sandwiching an insulating region, and includes a nanoparticle providing a conducting path between the two electrodes, wherein either the insulating region comprises an inorganic material and nanoparticle comprises a solid nanoparticle or a core/shell nanoparticle or the insulating region comprises an inorganic or organic material and the nanoparticle comprises a core/shell nanoparticle. | 07-17-2014 |
| 20140203236 | ONE TRANSISTOR AND ONE RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH SPACER - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 07-24-2014 |
| 20140203237 | SELF-RECTIFIED DEVICE, METHOD FOR MANUFACTURING THE SAME, AND APPLICATIONS OF THE SAME - A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property. | 07-24-2014 |
| 20140209849 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, dry etching is performed so that an upper-layer wiring material layer, a memory-layer constituting layer, and an interlayer insulating film are processed to form a pattern including a line-and-space pattern extending in a second direction and a dummy pattern connecting line patterns constituting the line-and-space pattern in a memory cell formation region and an upper-layer wiring hookup region. Then, the dummy pattern is removed. | 07-31-2014 |
| 20140209850 | STRONGLY CORRELATED NONVOLATILE MEMORY ELEMENT - In aspects of the invention, a strongly correlated nonvolatile memory element is provided which exhibits phase transitions and nonvolatile switching functions through electrical means. In an aspect of the invention, a strongly correlated nonvolatile memory element is provided including, on a substrate, a channel layer, a gate electrode, a gate insulator, a source electrode, and a drain electrode. The channel layer includes a strongly correlated oxide thin film, and is formed of a perovskite type manganite which exhibits a charge-ordered phase or an orbital-ordered phase; the gate insulator is formed in contact with at least a portion of a surface or interface of the channel layer and is sandwiched between the channel layer and the gate electrode, and the source electrode and drain electrode are formed in contact with at least a portion of the channel layer. | 07-31-2014 |
| 20140209851 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 07-31-2014 |
| 20140217349 | Methods of Forming Memory and Methods of Forming Vertically-Stacked Structures - Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells. | 08-07-2014 |
| 20140217350 | Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells - An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed. | 08-07-2014 |
| 20140217351 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa. | 08-07-2014 |
| 20140217352 | Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays - Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines. | 08-07-2014 |
| 20140231743 | MEMORY CELLS AND METHODS OF FORMING MEMORY CELLS - Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour. | 08-21-2014 |
| 20140231744 | Methods for forming resistive switching memory elements - Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication. | 08-21-2014 |
| 20140239245 | APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME - Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions. | 08-28-2014 |
| 20140239246 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films. | 08-28-2014 |
| 20140239247 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function. | 08-28-2014 |
| 20140246640 | Doped Electrodes Used To Inhibit Oxygen Loss in ReRAM Device - A nonvolatile memory device and method for forming a resistive switching memory element, with improved lifetime and switching performance. A nonvolatile memory element includes resistive switching layer formed between a first and second electrode. The resistive switching layer comprises a metal oxide. One or more electrodes include a dopant material to provide the electrode with enhanced oxygen-blocking properties that maintain and control the oxygen ion content within the memory element contributing to increased device lifetime and performance. | 09-04-2014 |
| 20140246641 | Resistive Switching Devices Having a Switching Layer And An Intermediate Electrode Layer and Methods of Formation Thereof - In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node. | 09-04-2014 |
| 20140246642 | ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure. | 09-04-2014 |
| 20140246643 | MEMORY DEVICE AND APPARATUS INCLUDING THE SAME - A memory device may include a first electrode and a second electrode spaced apart from the first electrode. The memory device may further include a memory element disposed between the first electrode and the second electrode and a switching element disposed between the first electrode and the second electrode. The switching element may be configured to control signal access to the memory element. The memory device may further include a barrier layer disposed between the memory element and the switching element, the barrier layer including an insulation material. | 09-04-2014 |
| 20140246644 | Front to Back Resistive Random Access Memory Cells - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 09-04-2014 |
| 20140246645 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 09-04-2014 |
| 20140252297 | Resistive Memory Cell Array with Top Electrode Bit Line - A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell. | 09-11-2014 |
| 20140252298 | METHODS AND APPARATUS FOR METAL OXIDE REVERSIBLE RESISTANCE-SWITCHING MEMORY DEVICES - In some aspects, a memory cell is provided that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The reversible resistance switching element includes a first metal oxide material, and the liner includes the first metal oxide material. Numerous other aspects are provided. | 09-11-2014 |
| 20140252299 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND MICRO PROCESSOR, PROCESSOR, SYSTEM, DATA STORAGE SYSTEM AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction; and a plurality of resistance variable lines interposed between the first and the second conductive lines and extending in a third direction crossing the first and the second directions. | 09-11-2014 |
| 20140252300 | MEMORY ARRAYS AND METHODS OF FORMING THE SAME - Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry. | 09-11-2014 |
| 20140252301 | SWITCHING DEVICE STRUCTURES AND METHODS - Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state. | 09-11-2014 |
| 20140252302 | Phase Change Memory Cells And Methods Of Forming Phase Change Memory Cells - A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between. | 09-11-2014 |
| 20140252303 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells. | 09-11-2014 |
| 20140264228 | FIN SELECTOR WITH GATED RRAM - A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. | 09-18-2014 |
| 20140264229 | LOW FORM VOLTAGE RESISTIVE RANDOM ACCESS MEMORY (RRAM) - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion. | 09-18-2014 |
| 20140264230 | PHASE CHANGE MATERIAL SWITCH AND METHOD OF MAKING THE SAME - A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element | 09-18-2014 |
| 20140264231 | Confined Defect Profiling within Resistive Random Memory Access Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide. | 09-18-2014 |
| 20140264232 | LOW TEMPERATURE TRANSITION METAL OXIDE FOR MEMORY DEVICE - A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell. | 09-18-2014 |
| 20140264233 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
| 20140264234 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
| 20140264235 | NON-VOLATILE MEMORY DEVICE WITH TSI/TSV APPLICATION - Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface. | 09-18-2014 |
| 20140264236 | CONTROLLING ON-STATE CURRENT FOR TWO-TERMINAL MEMORY - Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range. | 09-18-2014 |
| 20140264237 | RESISTIVE RAM AND FABRICATION METHOD - A structure for a resistive memory device and a method to fabricate the same is disclosed. The method includes providing a bottom electrode comprising a metal and forming a memory layer on the bottom electrode. The memory layer includes a first layer of metal oxide, and a second layer including the nitrogen-containing metal oxide. A top electrode is formed over the memory layer. | 09-18-2014 |
| 20140264238 | SCALING OF FILAMENT BASED RRAM - A solid state memory comprises a top electrode, a bottom electrode and an insulating switching medium that is disposed at a thickness based on a predetermined function. The insulating switching medium generates a conduction path in response to an electric signal applied to the device. The thickness of the insulating switching medium is a function of a filament width of the conduction path and operates to prevent rupture of a semi-stable region. The semi-stable region maintains filament structure over time and does not degrade into retention failure. The solid state memory can comprise one or more conducting layers that can operate to control the conductance at an on-state of the memory and offer oxygen vacancies or metal ions to the switching medium. The function of the thickness of the insulating switching medium can vary depending upon the number of conduction layers disposed at the insulating switching medium. | 09-18-2014 |
| 20140264239 | Using multi-layer MIMCAPs in the tunneling regime as selector element for a cross-bar memory array - Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device. | 09-18-2014 |
| 20140264240 | METHOD FOR MAKING MEMORY CELL BY MELTING PHASE CHANGE MATERIAL IN CONFINED SPACE - To form a memory cell with a phase change element, a hole is formed through an insulator to a bottom electrode, and a phase change material is deposited on the insulator surface covering the hole. A confining structure is formed over the phase change material so the phase change material expands into the hole when heated to melting to become electrically connected to the bottom electrode. A top electrode is formed over and electrically connects to the phase change material. The bottom electrode can include a main portion and an extension having a reduced lateral dimension. The confining structure can include capping material having a higher melting temperature than the phase change material, and sufficient tensile strength to ensure the phase change material moves into the hole when the phase change material melts and expands. The hole can be a J shaped hole. | 09-18-2014 |
| 20140264241 | ZnTe on TiN or Pt Electrodes as a Resistive Switching Element for ReRAM Applications - Resistive random access memory (ReRAM) cells can include a ZnTe switching layer and TiN or Pt electrodes. The combination of the switching layer of ZnTe and the electrodes of TiN or Pt is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. High temperature anneal of the ZnTe switching layer can further improve the performance of the ReRAM cells. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD). | 09-18-2014 |
| 20140264242 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A disturb-resistant nonvolatile memory device includes a substrate, a dielectric material overlying the semiconductor substrate, a first cell comprising a first wiring structure extending in a first direction overlying the dielectric material, a first contact region, a first resistive switching media, and a second wiring structure extending in a second direction orthogonal to the first direction, a second cell comprising the first wiring structure, a second contact region, a second resistive switching media, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure, and a dielectric material disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region. | 09-18-2014 |
| 20140264243 | NONVOLATIVE MEMORY WITH FILAMENT - An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure. Therefore, by using ReRAM-related filament-forming materials to get sub-litho-dimension conductive path as heating electrode and using high on/off ratio phase changeable material as the storage media, it is possible to reduce the power consumption of phase changeable memory dramatically without the drawbacks of filament-forming materials that are shown in ReRAM. | 09-18-2014 |
| 20140264244 | NONVOLATIVE MEMORY - A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability. | 09-18-2014 |
| 20140264245 | Resistive Memory Cell with Trench-Shaped Bottom Electrode - A resistive memory cell, e.g., a CBRAM or ReRAM cell, may include a top electrode, a bottom electrode having an elongated trench shape defining a pair of spaced-apart bottom electrode sidewalls, and an electrolyte switching region arranged between the top electrode and at least one of the bottom electrode sidewalls to provide a path for the formation of a conductive filament or vacancy chain from the at least one bottom electrode sidewall to the top electrode when a voltage bias is applied to the cell. In addition, a memory may include an array of resistive memory cells including a top electrode structure, a plurality of trench-style bottom electrodes extending in first direction, and a plurality of inverted-trench-style electrolyte switching regions extending perpendicular to the trench-style bottom electrodes to define a two-dimensional array of spaced-apart contact areas between the electrolyte switching regions and the bottom electrodes. | 09-18-2014 |
| 20140264246 | Resistive Memory Cell with Trench-Shaped Bottom Electrode - A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell. | 09-18-2014 |
| 20140264247 | Resistive Memory Cell with Reduced Bottom Electrode - A resistive memory cell may include a ring-shaped bottom electrode, a top electrode, and an electrolyte layer arranged between the bottom and top electrodes. A ring-shaped bottom electrode may be formed by forming a dielectric layer over a bottom electrode contact, etching a via in the dielectric layer to expose at least a portion of the bottom electrode contact, depositing a conductive via liner over the dielectric layer and into the via, the via liner deposited in the via forming a ring-shaped structure in the via and a contact portion in contact with the exposed bottom electrode contact, the ring-shaped structure defining a radially inward cavity of the ring-shaped structure, and filling the cavity with a dielectric fill material, such that the ring-shaped structure of the via liner forms the ring-shaped bottom electrode, depositing an electrolyte layer over the bottom electrode, and depositing a top electrode over the electrolyte layer. | 09-18-2014 |
| 20140264248 | Sidewall-Type Memory Cell - A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall. | 09-18-2014 |
| 20140264249 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements. | 09-18-2014 |
| 20140284539 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes first and magnetic layers, first and second non-magnetic layers and a W layer. Each of the first and second magnetic layers includes an axis of easy magnetization in a direction perpendicular to a film plane. The first magnetic layer has a variable magnetization direction. The second magnetic layer has an invariable magnetization direction. The first non-magnetic layer is provided between the first and second magnetic layers. The second non-magnetic layer is arranged on a surface of the first magnetic layer opposite to a surface on which the first non-magnetic layer is arranged and contains MgO. The W layer is arranged on a surface of the second non-magnetic layer opposite to a surface on which the first magnetic layer is arranged, and is in contact with the surface of the second non-magnetic layer. | 09-25-2014 |
| 20140284540 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - According to one embodiment, a semiconductor device comprises a first electrode; a second electrode containing a metal element; and a variable resistance element formed between the first electrode and the second electrode. The variable resistance element comprises an insulating first film disposed on a side of the first electrode and containing oxygen; and a second film disposed on the side of the second electrode and containing an element having a diffusion coefficient larger than the diffusion coefficient of the metal element in the first film and an electronegativity higher than the electronegativity of the metal element. | 09-25-2014 |
| 20140284541 | RESISTANCE RANDOM ACCESS MEMORY DEVICE - A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration. | 09-25-2014 |
| 20140284542 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction crossing the first direction, and a memory element provided between the first interconnect and the second interconnect at a portion where the first interconnect crosses the second interconnect. The memory element includes a variable resistance film and a stress generating film stacked with the variable resistance film to apply stress to the variable resistance film in a surface direction. | 09-25-2014 |
| 20140284543 | RESISTANCE RANDOM ACCESS MEMORY DEVICE - A resistance random access memory device according to an embodiment includes a first electrode, a second electrode, and a variable resistance portion placed between the first electrode and the second electrode. The variable resistance portion includes a first insulating layer, a second insulating layer, and a crystal layer that is placed between the first insulating layer and the second insulating layer, has a higher resistivity than the first electrode, and is crystalline. | 09-25-2014 |
| 20140284544 | RESISTANCE RANDOM ACCESS MEMORY DEVICE - A resistance random access memory device according an embodiment includes a first electrode, a second electrode and a resistance change layer. The first electrode includes a metal. The resistance change layer is provided between the first electrode and the second electrode. One of the metal is able to reversibly move within the resistance change layer. The second electrode is formed of a material ionizing less easily than the metal. The resistance change layer contains silicon, oxygen, and nitrogen, a nitrogen concentration of the resistance change layer is less than 46 atomic % and not less than 20 atomic %. | 09-25-2014 |
| 20140284545 | In-Situ Nitride Initiation Layer For RRAM Metal Oxide Switching Material - A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber. | 09-25-2014 |
| 20140291600 | Resistive Random Access Memory Using amorphous metallic Glass Oxide as a storage medium - The present invention relates to a resistive random access memory using amorphous metallic glass oxide as a storage medium, comprising a substrate, an insulation layer, a first electrode layer, a resistive memory layer, and a second electrode layer. In the present invention, an amorphous metallic glass oxide layer is mainly used as the resistive memory layer of the resistive random access memory. Therefore, the resistive random access memory with storage medium of amorphous metallic glass oxide thin film having advantages of low operation voltage, low power consumption, and high set/reset resistance ratio are provided without using any thermal annealing processes or forming processes. | 10-02-2014 |
| 20140291601 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND MICROPROCESSOR, PROCESSOR, SYSTEM, DATA STORAGE SYSTEM AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction. | 10-02-2014 |
| 20140291602 | OXIDE MEMORY RESISTOR INCLUDING SEMICONDUCTOR NANOPARTICLES - This invention relates to memory resistors, arrays of memory resistors and a method of making memory resistors. In particular, this invention relates to memory resistors having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of semiconductor material, and wherein in the on state nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode. | 10-02-2014 |
| 20140291603 | PHASE CHANGE MEMORY AND METHOD OF FABRICATING THE PHASE CHANGE MEMORY - Provided is a phase change memory, including: at least one wiring layer each including a first conductive layer and a phase change layer horizontally disposed on the first conductive layer; a heater layer disposed to vertically contact with the at least one wiring layer; and a second conductive layer disposed to contact with the heater layer in parallel therewith, and through which current flows from at least one electrode into the at least one wiring layer. The phase change layer may be made of a phase change material and may have a thickness less than a thickness of the first conductive layer. | 10-02-2014 |
| 20140291604 | MEMORY ARRAYS AND METHODS OF FORMING SAME - Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material. | 10-02-2014 |
| 20140291605 | NONVOLATILE MEMORY CELL AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film. | 10-02-2014 |
| 20140299830 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an impurity layer over a first conductive layer; forming a first metal oxide layer over the impurity layer, wherein the first metal oxide layer includes oxygen at a lower ratio than a stoichiometric ratio; diffusing an impurity from the impurity layer into the first metal oxide layer to form a first doped metal oxide layer; forming a second metal oxide layer over the first doped metal oxide layer; and forming a second conductive layer over the second metal oxide layer. | 10-09-2014 |
| 20140299831 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D variable resistance memory device and a method of manufacturing the same are provided. A semiconductor substrate includes a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area. The peripheral circuit includes a driving transistor formed on a surface of the semiconductor substrate, wherein the semiconductor substrate forms the channel of the driving transistor. The semiconductor substrate includes a cell area, having a top surface, wherein a height of the top surface of the cell area is lower than a height of the top surface of the peripheral area, thereby defining a trench in the cell area. A plurality of memory cells, each include a switching transistor formed on the semiconductor substrate in the cell area, a channel extending in a direction substantially perpendicular to a surface of the semiconductor substrate, and a variable resistance layer that selectively stores data in response to the switching transistor. | 10-09-2014 |
| 20140299832 | NONVOLATILE MEMORY ELEMENTS HAVING CONDUCTIVE STRUCTURES WITH SEMIMETALS AND/OR SEMICONDUCTORS - A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields. | 10-09-2014 |
| 20140299833 | CHALCOGENIDE SWITCHING DEVICE USING GERMANIUM AND SELENIUM AND MANUFACTURING METHOD THEREOF - Disclosed is a method for manufacturing a chalcogenide switching device includes forming a first electrode on a SOI substrate, forming a chalcogenide material composed of Ge | 10-09-2014 |
| 20140299834 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 10-09-2014 |
| 20140306172 | INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die having an address switch; a bottom electrode contact, free of halogen constituents, characteristic of a chemical vapor deposition or an atomic layer deposition, and coupled to the address switch; a transition material layer directly on the bottom electrode contact; and a top electrode contact, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die. | 10-16-2014 |
| 20140306173 | RESISTIVE MEMORY AND METHOD FOR FABRICATING THE SAME - A resistive memory having a leakage inhibiting characteristic and a method for fabricating the same, which can suppress a sneak current in a large scaled crossing array of a RRAM. A memory cell forming the resistive memory comprises a lower electrode, a first semiconductor-type oxide layer, a resistive material layer, a second semiconductor-type oxide layer and an upper electrode which are sequentially stacked. Each of the semiconductor-type oxide layers may be a semiconductor-type metal oxide or a semiconductor-type non-metal oxide. The sneak current may be effectively reduced by means of a Schottky barrier formed between the semiconductor-type oxide layer and the metal electrode, the fabrication process is easy to be implemented, and a high device integration degree can be achieved. | 10-16-2014 |
| 20140312293 | VARIABLE RESISTANCE NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a variable resistance non-volatile memory device including non-volatile memory element layers stacked together by repeating the step (S | 10-23-2014 |
| 20140312294 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND MICROPROCESSOR, PROCESSOR, SYSTEM, DATA STORAGE SYSTEM AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first conductive pattern and a first pad over a substrate; forming a first and a second resistance variable elements over the first conductive pattern and the first pad, respectively; performing impurity doping into the second resistance variable element to produce a conductive contact; and forming a second conductive pattern over the first resistance variable element. | 10-23-2014 |
| 20140312295 | MEMORY DEVICE - According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects. | 10-23-2014 |
| 20140312296 | THREE-DIMENSIONAL OBLIQUE TWO-TERMINAL MEMORY WITH ENHANCED ELECTRIC FIELD - Providing for three-dimensional memory cells having enhanced electric field characteristics is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance. | 10-23-2014 |
| 20140312297 | DEVICE STRUCTURE FOR A RRAM AND METHOD - A method of forming a resistive device includes forming a first wiring layer overlying a first dielectric on top of a substrate, forming a junction material, patterning the first wiring layer and junction material to expose a portion of the first dielectric, forming a second dielectric over the patterned first wiring layer, forming an opening in the second dielectric to expose a portion of the junction material, forming a resistive switching material over the portion of the junction material in the opening, the resistive switching material having an intrinsic semiconductor characteristic, forming a conductive material over the resistive switching material, etching the conductive material and the resistive switching material to expose respective sidewalls of the resistive switching material and the conductive material, and the second dielectric, and forming a second wiring layer over the conductive material in contact with the respective sidewalls and the second dielectric. | 10-23-2014 |
| 20140319445 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials. | 10-30-2014 |
| 20140319446 | RESISTIVE RAM DEVICES AND METHODS - The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element. | 10-30-2014 |
| 20140319447 | Semiconductor Constructions and Memory Arrays - Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays. | 10-30-2014 |
| 20140319448 | METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT - Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion. | 10-30-2014 |
| 20140319449 | Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure - An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer. | 10-30-2014 |
| 20140326940 | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF - A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film. | 11-06-2014 |
| 20140326941 | RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material. | 11-06-2014 |
| 20140326942 | NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME - A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode. | 11-06-2014 |
| 20140332748 | THREE DIMENSIONAL RESISTIVE MEMORY - A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells. | 11-13-2014 |
| 20140332749 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening. | 11-13-2014 |
| 20140332750 | Transistors, Memory Cells and Semiconductor Constructions - Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate. | 11-13-2014 |
| 20140332751 | Memory Cells, Methods of Programming Memory Cells, and Methods of Forming Memory Cells - Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer. | 11-13-2014 |
| 20140339492 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes a first interconnection extending in a first direction, a plurality of second interconnections provided side by side on the first interconnection and extending in a second direction intersecting the first direction and a memory layer provided on a side surface of each second interconnection. The device also includes a control element provided between each of the second interconnections and the first interconnection, an element part extending in the second direction, and a control electrode facing a side surface of the element part via a first insulating film. An adjustment part is provided on the first interconnection and adjacent to a control element connected to a second interconnection disposed at an end position of the second interconnections arranged in the first direction, and a first outer electrode provided between the adjustment part and the control element disposed at the end position. | 11-20-2014 |
| 20140339493 | ETCH BIAS HOMOGENIZATION - Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned. | 11-20-2014 |
| 20140346428 | MEMORY CELL STRUCTURES - The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device. | 11-27-2014 |
| 20140346429 | Semiconductor Constructions and Methods of Forming Memory Cells - Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material. | 11-27-2014 |
| 20140346430 | MEMORY DEVICE - Microelectronic device, comprising a substrate, a first electrode arranged above the substrate, a first resistive switch and a resistivity structure coupled with each other, wherein the first resistive switch and the resistivity structure are arranged in a single layer of the device, and a second electrode arranged above the layer that includes the first resistive switch and the resistivity structure, wherein the first resistive switch and the resistivity structure are coupled with the first and the second electrode. | 11-27-2014 |
| 20140346431 | Memory Structures, Memory Arrays, Methods of Forming Memory Structures and Methods of Forming Memory Arrays - Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays. | 11-27-2014 |
| 20140346432 | ON/OFF RATIO FOR NONVOLATILE MEMORY DEVICE AND METHOD - A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element. | 11-27-2014 |
| 20140346433 | MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided. | 11-27-2014 |
| 20140346434 | NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer. | 11-27-2014 |
| 20140353568 | THERMALLY OPTIMIZED PHASE CHANGE MEMORY CELLS AND METHODS OF FABRICATING THE SAME - A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity. | 12-04-2014 |
| 20140353569 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer. | 12-04-2014 |
| 20140353570 | MEMRISTOR - A nanobridge or microbridge comprising a non-magnetic alloy of at least a first and second metal, the meals being selected from Group 8, 9, 10 and 11, wherein the first metal is present in a range of 50-95 wt. %, and memristors comprising one or more of same. | 12-04-2014 |
| 20140353571 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 12-04-2014 |
| 20140353572 | RESISTANCE RANDOM ACCESS MEMORY DEVICE - A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration. | 12-04-2014 |
| 20140361236 | ALD processing techniques for forming non-volatile resistive switching memories - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer. | 12-11-2014 |
| 20140361237 | MEMORY STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory storage device including: a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells. | 12-11-2014 |
| 20140367630 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a lower electrode, a heater electrode having a pillar shape erected on the lower electrode, a phase change material in contact with the upper portion of the heater electrode, an upper electrode disposed above a heater electrode via the phase change material, side wall portions enclosing the periphery of the heater electrode, a first insulating film configuring a bottom surface portion continuous between heater electrodes, and a second insulating film formed on a bottom surface portion of the first insulating film; wherein the first insulating film and the second insulating film are formed after the heater electrode is formed in a pillar shape by double patterning. | 12-18-2014 |
| 20140367631 | SELF-RECTIFYING RRAM ELEMENT - The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (k | 12-18-2014 |
| 20140374686 | THERMAL-DISTURB MITIGATION IN DUAL-DECK CROSS-POINT MEMORIES - A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives. | 12-25-2014 |
| 20140374687 | RESISTIVE MEMORY WITH A STABILIZER - A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element. | 12-25-2014 |
| 20140374688 | High Capacity Select Switches for Three-Dimensional Structures - A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line. | 12-25-2014 |
| 20140374689 | CONDUCTIVE OXIDE RANDOM ACCESS MEMORY (CORAM) CELL AND METHOD OF FABRICATING SAME - Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer. | 12-25-2014 |
| 20140374690 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element includes a first electrode having at least one convex feature, a second electrode having a concave feature opposed to the convex feature, and a variable resistance layer including an element whose absolute value of standard reaction Gibbs energy for forming oxide is larger than the corresponding value of an element included in the first electrode, and being disposed between the convex feature and the concave feature or on the outer circumference of the convex feature of the first electrode. | 12-25-2014 |
| 20140374691 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film. | 12-25-2014 |
| 20150008388 | VARIABLE RESISTANCE MEMORY - A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode. | 01-08-2015 |
| 20150014621 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole. | 01-15-2015 |
| 20150014622 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory. | 01-15-2015 |
| 20150014623 | Memory Constructions - Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors. | 01-15-2015 |
| 20150021539 | RESISTIVE MEMORY WITH SMALL ELECTRODE AND METHOD FOR FABRICATING THE SAME - Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO | 01-22-2015 |
| 20150021540 | METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE - The disclosed technology generally relates to the field of semiconductor processing and more particularly to resistive random access memory and methods for manufacturing such memory. In one aspect, a method of fabricating a memory cell includes providing a substrate and providing a first electrode on the substrate. The method additionally includes depositing, via atomic layer deposition, a resistive switching material on the first electrode, wherein the resistive switching material comprises an oxide comprising a pnictogen chosen from the group consisting of As, Bi, Sb, and P. The resistive switching material may be doped, e.g., with Sb or an antimony-metal alloy. A second electrode may be formed over and in contact with the resistive switching material. | 01-22-2015 |
| 20150021541 | RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION - Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening. | 01-22-2015 |
| 20150021542 | MEMORY CELL OF RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer. | 01-22-2015 |
| 20150028279 | RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONTACTS - A resistive switching device includes a first electrode and a transition metal oxide layer formed on the first electrode. An oxygen scavenging electrode is formed on the transition metal oxide wherein the oxygen scavenging electrode removes oxygen from the transition metal oxide layer to increase formation of oxygen vacancies in the transition metal oxide layer to enable a switching mode when a bias is applied between the first electrode and the oxygen scavenging electrode. | 01-29-2015 |
| 20150028280 | MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element. | 01-29-2015 |
| 20150028281 | RESISTIVE MEMORY STRUCTURE - A resistive memory structure including at least one reactive layer, at least one electrode, and at least one resistance-changing material is provided. The reactive layer extends along a first direction and a second direction. The electrode extends at least along a third direction, wherein the first direction, the second direction, and the third direction are different from each other. At least part of the resistance-changing material is disposed between the reactive layer and the electrode. When ions diffuse from the resistance-changing material to the reactive layer or from the reactive layer to the resistance-changing material, resistance of the resistance-changing material changes. | 01-29-2015 |
| 20150028282 | RESISTANCE SWITCHING DEVICE AND PROCESS FOR PRODUCING THEREOF - resistance switching device having a high resistance variation ratio, an excellent response characteristic, an excellent resistance memory characteristic (retention characteristics) and an excellent repeat resistance. The resistance switching device comprises an n-type oxide semiconductor and first and second electrodes which are disposed so as to interpose at least a part of the n-type oxide semiconductor therebetween wherein a Schottky junction which provides resistance variation/memory characteristics by the application of voltage having different polarities between the first and second electrodes is formed at an interface between the n-type oxide semiconductor and the first electrode; and the first electrode is positioned such that it is in contact with the n-type oxide semiconductor, and has a lower layer which is formed from Au oxide or a Pt oxide or Au or Pt containing oxygen having the thickness of 1-50 nm. | 01-29-2015 |
| 20150034896 | Resistive-Switching Nonvolatile Memory Elements - Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 02-05-2015 |
| 20150034897 | POST DEPOSITION ADJUSTMENT OF CHALCOGENIDE COMPOSITION IN CHALCOGENIDE CONTAINING SEMICONDUCTORS - The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. Upon the application of heat, the titanium may react with the tellurium to a controlled extent to reduce the concentration of tellurium in the chalcogenide film. | 02-05-2015 |
| 20150034898 | Confined Defect Profiling within Resistive Random Memory Access Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide. | 02-05-2015 |
| 20150041749 | Memory Cells and Methods of Forming Memory Cells - A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed. | 02-12-2015 |
| 20150041750 | Resistive Memory Device and Method for Fabricating the Same - An embodiment of the present invention provides a resistive memory device and a method for fabricating the same. The resistive memory device includes a substrate and a plurality of memory cells spaced with each other over the substrate, each memory cell including a lower electrode, a resistive layer and an upper electrode, wherein the lower electrode is disposed over the substrate, the resistive layer is disposed over the lower electrode and the upper electrode is disposed over the resistive layer, and the resistive layer includes a resistive material portion and at least one doped resistive portion doped with an element for adjusting a resistance state. In the resistive memory device and the method for fabricating the same according to the present invention, since the resistive layer is not formed of single resistive material, during a set operation of the resistive memory device, a plurality of stable resistance states are produced according to various applied voltages, so that a storage density of the resistive memory device is increased without increasing a volume of the resistive memory device. | 02-12-2015 |
| 20150041751 | CUSTOMIZABLE NONLINEAR ELECTRICAL DEVICES - In one example, a customizable nonlinear electrical device includes a first conductive layer, a second conductive layer, and a thin film metal-oxide layer sandwiched between the first conductive layer and the second conductive layer to form a first rectifying interface between the metal-oxide layer and the first conductive layer and a second rectifying interface between the metal-oxide layer and the second conductive layer. The metal-oxide layer includes an electrically conductive mixture of co-existing metal and metal oxides. A method forming a nonlinear electrical device is also provided. | 02-12-2015 |
| 20150041752 | PHASE CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 02-12-2015 |
| 20150041753 | NANO-SCALE ELECTRICAL CONTACTS, MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES - Electrical contacts may be formed by forming dielectric liners along sidewalk of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of as first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm | 02-12-2015 |
| 20150041754 | RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. | 02-12-2015 |
| 20150048297 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode. | 02-19-2015 |
| 20150048298 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film. | 02-19-2015 |
| 20150048299 | TWO TERMINAL SWITCHING DEVICE HAVING BIPOLAR SWITCHING PROPERTY, METHOD OF FABRICATING THE SAME, AND RESISTIVE MEMORY CROSS-POINT ARRAY HAVING THE SAME - Provided are a two-terminal switching device having a bidirectional switching property, and a resistive memory cross-point array including the same. The two-terminal switching device includes a first electrode. A first tunneling barrier layer is disposed on the first electrode. An oxide semiconductor layer is disposed on the first tunneling barrier layer. A second tunneling barrier layer is disposed on the oxide semiconductor layer. A second electrode is disposed on the second tunneling barrier layer. | 02-19-2015 |
| 20150053908 | MEMRISTIVE DEVICE AND METHOD OF MANUFACTURE - A device with programmable resistance comprising memristive material between conductive electrodes on a substrate or in a film stack on a substrate is provided. During fabrication of a memristive device, a memristive layer may be hydrated after deposition of the memristive layer. The hydration of the memristive layer may be performed utilizing thermal annealing in a reducing ambient, implant or plasma treatment in a reducing ambient, or a deionized water rinse. Additionally, plasma-assisted etching of an electrode may be performed with hydration or in place of hydration to electroform devices in a batch, in situ process. The memristive device may be electroformed at low voltage and passivated to allow for device operation in air. Further, the memristive device is suitable for high throughput manufacturing. | 02-26-2015 |
| 20150053909 | NONLINEAR MEMRISTORS - A nonlinear memristor includes a bottom electrode, a top electrode, and an insulator layer between the bottom electrode and the top electrode. The insulator layer comprises a metal oxide. The nonlinear memristor further includes a switching channel within the insulator layer, extending from the bottom electrode toward the top electrode, and a nano-cap layer of a metal-insulator-transition material between the switching channel and the top electrode. The top electrode comprises the same metal as the metal in the metal-insulator-transition material. | 02-26-2015 |
| 20150053910 | Multistate Nonvolatile Memory Elements - Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers. | 02-26-2015 |
| 20150060750 | Resistance Variable Memory Structure and Method of Forming the Same - A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. | 03-05-2015 |
| 20150060751 | MEMORY CELLS WITH RECESSED ELECTRODE CONTACTS - Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. An upper surface of the electrode contact is recessed a distance relative to an upper surface of the substrate. A first portion of a memory element is formed on an upper surface of the electrode contact and the upper surface of the substrate. | 03-05-2015 |
| 20150060752 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, a common source region formed on the semiconductor substrate and extending in a line shape, an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, and a gate formed in a space between the source region and the drain region. | 03-05-2015 |
| 20150060753 | CONTROLLING COMPOSITION OF MULTIPLE OXIDES IN RESISTIVE SWITCHING LAYERS USING ATOMIC LAYER DEPOSITION - A method of fabricating a resistive random access memory (ReRAM) cell may include forming a set of nanolaminate structures over an electrode, such that each structure includes at least one first element oxide layer and at least one second element oxide layer. The overall set is operable as a resistive switching layer in a ReRAM cell. In this set, an average atomic ratio of the first element to the second element is different in at least two nanolaminate structures. This ratio may be less in nanolaminate structures that are closer to electrodes than in the middle nanolaminate structures. Alternatively, this ratio may increase from one end of the set to another. The first element may be less electronegative than the second elements. The first element may be hafnium, while the second element may be one of zirconium, aluminum, titanium, tantalum, or silicon. | 03-05-2015 |
| 20150060754 | MEMORY DEVICES HAVING ELECTRODES COMPRISING NANOWIRES, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. | 03-05-2015 |
| 20150069315 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm. | 03-12-2015 |
| 20150069316 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer. | 03-12-2015 |
| 20150069317 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate with a groove for forming an embedded gate therein, and a gate electrode embedded via a gate insulator film in the groove. A portion of the semiconductor substrate near the gate electrode is doped with a chemical element which is inactive in the semiconductor substrate. | 03-12-2015 |
| 20150069318 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device according to an embodiment includes an ion metal layer, an opposing electrode, and a resistance change layer. The ion metal layer contains a first metal and a second metal. The resistance change layer is disposed between the ion metal layer and the opposing electrode. The first metal is able to move repeatedly through an interior of the resistance change layer. The concentration of the first metal in a central portion of the ion metal layer is higher than the concentration of the first metal in an end portion of the ion metal layer. | 03-12-2015 |
| 20150069319 | Method of forming anneal-resistant embedded resistor for non-volatile memory application - Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer. | 03-12-2015 |
| 20150076437 | METHODS OF FORMING A FERROELECTRIC MEMORY CELL AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material. | 03-19-2015 |
| 20150076438 | NON-VOLATILE RESISTIVE MEMORY CELLS - Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion. | 03-19-2015 |
| 20150076439 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode. | 03-19-2015 |
| 20150076440 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode and an insulating portion. The first electrode includes an ionizable metal. The second electrode includes a conductive material. The conductive material is more difficult to ionize than the metal. The insulating portion is provided between the first electrode and the second electrode. The insulating portion is made of an insulating material. A space is adjacent to a side surface of the insulating portion between the first electrode and the second electrode. | 03-19-2015 |
| 20150076441 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole. | 03-19-2015 |
| 20150083986 | METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES - Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells. | 03-26-2015 |
| 20150083987 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device with a high ON/OFF ratio can be provided. | 03-26-2015 |
| 20150083988 | ORGANIC MOLECULAR MEMORY - An organic molecular memory in an embodiment includes a first conducive layer, a second conductive layer, and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer having an organic molecule, the organic molecule having a linker group bonded to the first conductive layer, a π conjugated chain bonded to the linker group, and a phenyl group bonded to the π conjugated chain opposite to the linker group and facing the second conductive layer, the π conjugated chain including electron-accepting groups or electron-donating groups arranged in line asymmetry with respect to a bonding direction of the π conjugated chain, the phenyl group having substituents R0, R1, R2, R3, and R4 as shown in the following formula, the substituent R0 being an electron-accepting group or an electron-donating group. | 03-26-2015 |
| 20150083989 | RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaO | 03-26-2015 |
| 20150090949 | RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA - The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention. | 04-02-2015 |
| 20150090950 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer. | 04-02-2015 |
| 20150090951 | SEMICONDUCTOR APPARATUS HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns. | 04-02-2015 |
| 20150090952 | RESISTOR MEMORY BIT-CELL AND CIRCUITRY AND METHOD OF MAKING THE SAME - A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit. | 04-02-2015 |
| 20150090953 | Materials with Tunable Properties and Memory Devices and Methods of Making Same Using Random Nanowire or Nanotube Networks - A device comprising a first electrode; a second electrode; and an active material positioned between the first and second electrode, wherein the active material comprises a plurality of randomly positioned conducting wires coated with a nanoscale switchable dielectric layer, said conducting wires are adapted to provide a conducting path or paths when a voltage is applied by one of the electrodes or between said electrodes. | 04-02-2015 |
| 20150090954 | PHASE CHANGE MEMORY AND FABRICATION METHOD - A phase change memory and its fabrication method are provided. A bottom electrode structure is provided through a substrate. A mask layer is formed on the substrate and the bottom electrode structure. A first opening is formed in the mask layer to expose the bottom electrode structure. A spacer is formed on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode structure. The first opening including the spacer therein has a bottom width less than a top width. A heating layer is formed at least on the surface portion of the bottom electrode structure exposed by the spacer. A phase change layer is formed on the heating layer to completely fill the first opening. A top electrode is formed on the phase change layer and the mask layer. | 04-02-2015 |
| 20150097152 | MAGNETIC FIELD-PARTITIONED NON-VOLATILE MEMORY - A non-volatile memory cell and a magnetic field-partitioned non-volatile memory for multi-bit storage are provided. The non-volatile memory cell for multi-bit storage includes a bottom electrode. A resistance-changing memory material covers the bottom electrode. A top electrode including a high-mobility material is disposed on the resistance-changing memory material. The top electrode has two post portions supporting a bar-shaped portion. At least two bits are stored in portions of the resistance-changing memory material connecting to the top electrode when an external magnetic field is applied along different directions. | 04-09-2015 |
| 20150097153 | Non-volatile Resistive-Switching Memories - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 04-09-2015 |
| 20150102279 | RESISTANCE CHANGE DEVICE AND MEMORY CELL ARRAY - According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode. | 04-16-2015 |
| 20150102280 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. A variable resistive layer is formed in the opening and a second electrode is formed on the variable resistive layer. The variable resistive layer has a sidewall that is separated from an inner side surface of the opening to define a gap between the sidewall of the variable resistive layer and the inner side surface of the opening. | 04-16-2015 |
| 20150102281 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 04-16-2015 |
| 20150108420 | RESISTANCE CHANGE ELEMENT AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material. | 04-23-2015 |
| 20150108421 | ORGANIC MOLECULAR MEMORY AND METHOD OF MANUFACTURING THE SAME - An organic molecular memory for controlling a current flowing through a memory cell and achieving stable operation and high degree of reliability is provided. The organic molecular memory includes a first electrode, a second electrode made of a material different from the first electrode, and an organic molecule layer provided between the first electrode and the second electrode, wherein one end of a resistance change-type molecular chain constituting the organic molecule layer is chemically bonded with the first electrode, and an air gap exists between the other end of the resistance change-type molecular chain and the second electrode. | 04-23-2015 |
| 20150115215 | Phase Change Memory and Method of Fabricating Same - A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer. | 04-30-2015 |
| 20150123064 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a first metal and a second metal. The switching material is a second composition which includes the second metal. The second composition is directly against the first composition. Some embodiments include methods of forming memory cells. | 05-07-2015 |
| 20150123065 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells. | 05-07-2015 |
| 20150123066 | ELECTRODE MATERIALS AND INTERFACE LAYERS TO MINIMIZE CHALCOGENIDE INTERFACE RESISTANCE - A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm. | 05-07-2015 |
| 20150123067 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. | 05-07-2015 |
| 20150123068 | FIN-TYPE MEMORY - Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. | 05-07-2015 |
| 20150123069 | STORAGE ELEMENT - A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow. | 05-07-2015 |
| 20150123070 | Arrays Of Memory Cells And Methods Of Forming An Array Of Vertically Stacked Tiers Of Memory Cells - An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed. | 05-07-2015 |
| 20150123071 | Method for Forming Metal Oxides and Silicides in a Memory Device - Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process. | 05-07-2015 |
| 20150129826 | Flexible Non-Volatile Memory - A flexible and/or transparent nonvolatile memory device can be fabricated on flexible substrates, together with ductile materials or transparent conductive oxide materials, and layers with thicknesses that allow flexibility and transparency. The ductile materials can include Ti, Ni, Nb, or Zr. The transparent conductive materials can include indium tin oxide, zinc oxide or aluminum doped zinc oxide. The nonvolatile memory devices can include resistive switching memory, phase change memory, magnetoresistive random access memory, or spin-transfer torque random access memory. | 05-14-2015 |
| 20150129827 | VIA STRUCTURE, MEMORY ARRAY STRUCTURE, THREE-DIMENSIONAL RESISTANCE MEMORY AND METHOD OF FORMING THE SAME - Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening. | 05-14-2015 |
| 20150129828 | 3 DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes. | 05-14-2015 |
| 20150137059 | Resistive Random Access Memory (RRAM) with Improved Forming Voltage Characteristics and Method for Making - The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack. | 05-21-2015 |
| 20150137060 | HIGH RECTIFYING RATIO DIODE - Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode. | 05-21-2015 |
| 20150137061 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction. | 05-21-2015 |
| 20150137062 | Mimcaps with quantum wells as selector elements for crossbar memory arrays - Selector devices suitable for memory arrays have low leakage currents at low voltages, reducing sneak current paths for non-selected devices, and high leakage currents at high voltages, reducing voltage drops during switching. The selector device may include a non-conductive tri-layer between two electrodes. The non-conductive tri-layer may include a low-bandgap dielectric layer between two higher-bandgap dielectric layers. The high-bandgap dielectric layers may be doped to form traps at energy levels higher than the write voltage of the memory device. With a thin low-bandgap layer and a large bandgap difference from the high-bandgap layers, the selector may operate as a quantum well, conductive when the electrode Fermi level matches the lowest energy level of the quantum well and insulating at lower voltages. | 05-21-2015 |
| 20150137063 | RESISTIVE SWITCHING IN MEMORY CELLS - Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell. | 05-21-2015 |
| 20150137064 | Reduction of forming voltage in semiconductor devices - This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results. | 05-21-2015 |
| 20150137065 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another. | 05-21-2015 |
| 20150144859 | Top Electrode Blocking Layer for RRAM Device - An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode. | 05-28-2015 |
| 20150144860 | RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF - The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure. | 05-28-2015 |
| 20150144861 | RESISTIVE MEMORY AND METHOD FOR FABRICATING THE SAME - Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion. This significantly increases the possibility of generation of a conductive filament at the conductive protrusion, so that the conductive filament is not randomly formed. Thus, the stability of various parameters of the resistive memory is ensured, and thus the reliability and stability of the operation of the resistive memory are dramatically increased. | 05-28-2015 |
| 20150144862 | Variable Resistance Memory Device and a Method of Fabricating the Same - A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed. | 05-28-2015 |
| 20150144863 | RESISTIVE MEMORY DEVICE AND FABRICATION METHODS - A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer. | 05-28-2015 |
| 20150144864 | Memory Arrays and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction. | 05-28-2015 |
| 20150295012 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring. | 10-15-2015 |
| 20150295171 | MEMORY CELLS AND SEMICONDUCTOR STRUCTURES INCLUDING ELECTRODES COMPRISING A METAL, AND RELATED METHODS - Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials. | 10-15-2015 |
| 20150310917 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating - Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described. | 10-29-2015 |
| 20150311257 | Resistive Random Access Memory Cells Having Shared Electrodes with Transistor Devices - Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped. | 10-29-2015 |
| 20150311435 | Leakage Resistant RRAM/MIM Structure - An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents. | 10-29-2015 |
| 20150311436 | SWITCHING DEVICE STRUCTURES AND METHODS - Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state. | 10-29-2015 |
| 20150318332 | MULTIFUNCTIONAL ZINC OXIDE NANO-STRUCTURE-BASED CIRCUIT BUILDING BLOCKS FOR RE-CONFIGURABLE ELECTRONICS AND OPTOELECTRONICS - A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed. | 11-05-2015 |
| 20150318333 | INTEGRATIVE RESISTIVE MEMORY IN BACKEND METAL LAYERS - Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries. | 11-05-2015 |
| 20150318467 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 11-05-2015 |
| 20150318468 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner. | 11-05-2015 |
| 20150318469 | PHASE CHANGE MEMORY CELL AND PHASE CHANGE MEMORY - A phase change memory cell includes a carbon nanotube layer, a phase change layer, a first electrode, a second electrode, and a third electrode. At least part of the phase change layer is overlapped with the carbon nanotube layer. The first electrode and the second electrode are electrically connected with the carbon nanotube layer, wherein the first electrode and the second electrode are configured to apply a first voltage to the carbon nanotube layer. The third electrode is electrically connected with the phase change layer, wherein the third electrode and the first electrode are configured to apply a second voltage to the phase change layer. | 11-05-2015 |
| 20150318470 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa. | 11-05-2015 |
| 20150318473 | SEMICONDUCTOR DEVICE AND OPERATION METHOD FOR SAME - A semiconductor device, includes first, second, and third switching elements. The third switching element comprises first and second terminals. Each of the first and second switching elements comprise a unified ion conductor, a first electrode disposed to contact the ion conductor and supply metal ions thereto, and a second electrode disposed to contact the ion conductor and is less susceptible to ionization than the first electrode. The first electrodes of the first switching element and the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected, or the second electrode of the first switching element and the second electrode of the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the second electrodes which are electrically connected. | 11-05-2015 |
| 20150325695 | SEMICONDUCTOR APPARATUS, METHOD FOR FABRICATING THE SAME, AND VARIABLE RESISTIVE MEMORY DEVICE - A semiconductor apparatus that includes a semiconductor substrate and a plurality of pillars formed in the semiconductor substrate. Each of the plurality of pillars includes a first pillar, and a second pillar formed on the first pillar, wherein the second pillar has a smaller linewidth than the first pillar. | 11-12-2015 |
| 20150333105 | Resistance-Switching Memory Cell With Multiple Raised Structures In A Bottom Electrode - A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower. | 11-19-2015 |
| 20150333255 | PHASE-CHANGE DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member. | 11-19-2015 |
| 20150333256 | MEMORY ELEMENT WITH ION CONDUCTOR LAYER IN WHICH METAL IONS DIFFUSE AND MEMORY DEVICE INCORPORATING SAME - The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions. | 11-19-2015 |
| 20150333257 | RESISTIVE MEMORY ELEMENTS, RESISTIVE MEMORY CELLS, AND RESISTIVE MEMORY DEVICES - A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described. | 11-19-2015 |
| 20150340604 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode. | 11-26-2015 |
| 20150340605 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device according to an embodiment includes two electrodes and two semiconductor layers. The two electrodes extend in a first direction. The two semiconductor layers are placed between the two electrodes, are spaced from each other in the first direction, and extend in a second direction orthogonal to the first direction. The two electrodes include extending parts extending out so as to come close to each other. In a cross section orthogonal to the second direction, the extending parts extend into a region interposed between a pair of tangent lines. The pair of tangent lines tangent to both the two semiconductor layers and do not cross each other. | 11-26-2015 |
| 20150340606 | SWITCHING ELEMENT AND METHOD FOR FABRICATING SEMICONDUCTOR SWITCHING DEVICE - In switching elements each using a two-terminal-type variable resistance element, improper writing or any improper operation is often caused and the reliability of the switching elements cannot be improved easily. A switching element according to the present invention is equipped with a first variable resistance element equipped with a first input/output terminal and a first connection terminal, a second variable resistance element equipped with a second input/output terminal and a second connection terminal, and a rectifying element equipped with a control terminal and a third connection terminal, wherein the first connection terminal, the second connection terminal and the third connection terminal are connected to one another. | 11-26-2015 |
| 20150340608 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 11-26-2015 |
| 20150340609 | SWITCHING ELEMENT AND METHOD FOR MANUFACTURING SWITCHING ELEMENT - The present invention provides a non-volatile switching element that can be applied to a programmable-logic wiring changeover switch and in which an electrochemical reaction is used. Of the two electrodes for applying a bias voltage to the variable resistance layer of the non-volatile switching element, the electrode that does not feed metal ions to the variable resistance layer when the switch is in the ON state is made from a ruthenium alloy. The ruthenium alloy includes ruthenium and a metal in which the standard Gibbs energy of forming ΔG when metal ions are generated from the metal is higher in the negative direction than ΔG of ruthenium. As a result, it becomes possible to maintain the low-resistance state in the ON state for a longer period of time without increasing the amount of electrical current required when a switch is made between the ON state and the OFF state. | 11-26-2015 |
| 20150340610 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines over the first conductive lines, which extend in a second direction not parallel to the first direction, memory cells including a variable resistance element, each of which is formed at an intersection of the first and second conductive lines, first insulation layer patterns extending in the first direction between the memory cells, second insulation layer patterns extending in the second direction between the memory cells, first thermal barrier layer patterns extending in the first direction, which is spaced apart from the memory cells in the second direction between the first insulation layer patterns, and second thermal barrier layer patterns extending in the second direction, which is spaced apart from the memory cells in the first direction between the second insulation layer patterns. | 11-26-2015 |
| 20150349024 | RESISTOR MEMORY BIT-CELL AND CIRCUITRY AND METHOD OF MAKING THE SAME - A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit. | 12-03-2015 |
| 20150349025 | MEMORY DEVICE AND MEMORY UNIT - There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode. | 12-03-2015 |
| 20150349247 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment comprises a base layer. A material layer is provided on the base layer. A lower layer portion is provided in lower parts of trenches or holes formed in the material layer and has a crystal structure in a direction not perpendicular to a surface of the base layer. An upper layer portion is provided on the lower layer portion in the trenches or the holes and has a crystal structure in a direction substantially perpendicular to the surface of the base layer. | 12-03-2015 |
| 20150349248 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions. | 12-03-2015 |
| 20150349249 | MEMORY CELLS HAVING A NUMBER OF CONDUCTIVE DIFFUSION BARRIER MATERIALS AND MANUFACTURING METHODS - Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described. | 12-03-2015 |
| 20150349252 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device according to an embodiment includes an electrode extending in a first direction, two semiconductor members spaced from each other in the first direction and extending in a second direction crossing the first direction, an insulating film placed between each of the two semiconductor members and the electrode and made of a first insulating material, and a first dielectric member placed between the two semiconductor members and made of a second insulating material having a higher permittivity than the first insulating material. | 12-03-2015 |
| 20150349253 | Highly Reliable Nonvolatile Memory and Manufacturing Method Thereof - The present invention relates to a highly reliable nonvolatile memory and a manufacturing method thereof. The nonvolatile memory comprises top electrodes, bottom electrodes and a resistive material layer disposed therebetween, wherein the top electrodes are positioned on top in the memory; the bottom electrodes are positioned on a substrate; metal oxide for forming the resistive material layer is doped with metal; and a metal oxygen storage layer is further disposed between the top electrodes and the resistive material layer. The manufacturing method adopts a method in which a doping method and a double-layer forming method are combined, so that the highly reliable and highly uniform resistive random access memory can be fabricated and accordingly the performance of the memory can be increased. | 12-03-2015 |
| 20150349255 | Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells - An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed. | 12-03-2015 |
| 20150357379 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface. | 12-10-2015 |
| 20150357381 | RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE - A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole. | 12-10-2015 |
| 20150357559 | TOP ELECTRODE COUPLING IN A MAGNETORESISTIVE DEVICE USING AN ETCH STOP LAYER - A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack. | 12-10-2015 |
| 20150357563 | METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL - A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer ( | 12-10-2015 |
| 20150357564 | Phase Change Memory Cells - A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed. | 12-10-2015 |
| 20150357565 | MEMORY CELLS AND MEMORY CELL FORMATION METHODS USING SEALING MATERIAL - Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench. | 12-10-2015 |
| 20150357566 | RESISTIVE RANDOM-ACCESS MEMORY WITH IMPLANTED AND RADIATED CHANNELS - Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound. | 12-10-2015 |
| 20150364679 | RESISTIVE RANDOM ACCESS MEMORY DEVICE - A resistive random access memory device includes a first electrode made of inert material; a second electrode made of soluble material; a solid electrolyte including a region made of an oxide of a first metal element, referred to as first metal oxide doped by a second element, distinct from the first metal and able to form a second oxide, the second element being selected such that the band gap energy of the second oxide is strictly greater than the band gap energy of the first metal oxide, the atomic percentage of the second element within the region of the solid electrolyte being comprised between 5% and 20%. | 12-17-2015 |
| 20150364680 | RESISTIVE RANDOM ACCESS MEMORY DEVICE - A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer. | 12-17-2015 |
| 20150364681 | NONVOLATILE STORAGE DEVICE AND METHOD OF PRODUCING THE DEVICE - A nonvolatile storage device includes a first conductive layer disposed on a substrate, a contact plug including a conductive material and disposed on the first conductive layer, a variable resistance element covering the upper surface of the contact plug, resistance of the variable resistance element changing in accordance with an voltage applied to the variable resistance element, one single insulating layer that is directly or indirectly in contact with a sidewall of the contact plug and that is directly or indirectly in contact with a sidewall of the variable resistance element, and a second conductive layer disposed on the variable resistance element. | 12-17-2015 |
| 20150372056 | SEMICONDUCTOR DIODES, AND VARIABLE RESISTANCE MEMORY DEVICES - A semiconductor diode includes a first semiconductor pattern including a first impurity, a first diffusion barrier pattern on the first semiconductor pattern, an intrinsic semiconductor pattern on the first diffusion barrier pattern, a second diffusion barrier pattern on the intrinsic semiconductor pattern, and a second semiconductor pattern including a second impurity on the second diffusion barrier pattern. | 12-24-2015 |
| 20150372057 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE HAVING LATERAL CHANNEL - A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material. | 12-24-2015 |
| 20150372059 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer. | 12-24-2015 |
| 20150372060 | Memory Devices Having Low Permittivity Layers and Methods of Fabricating the Same - A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers. | 12-24-2015 |
| 20150372227 | MEMORY CELLS - Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the second electrode. The second electrode comprises a plurality of portions of material, each portion having a respective distance from the surface of the phase change material and each portion having a respective resistivity. A portion of the plurality of portions of material farthest from the surface of the phase change material has a lowest resistivity and a portion of the plurality of portions of material closest to the surface of the phase change material has a highest resistivity. The resistivity of each individual portion is lower than the resistivity of each portion located closer to the surface of the phase change material, and higher than the resistivity of each portion located farther from the surface of the phase change material. | 12-24-2015 |
| 20150372229 | RESISTIVE MEMORY DEVICE HAVING ASYMMETRIC DIODE STRUCTURE - A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode. | 12-24-2015 |
| 20150380463 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening. | 12-31-2015 |
| 20150380464 | MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes. | 12-31-2015 |
| 20150380641 | SEMICONDUCTOR DEVICE AND DIELECTRIC FILM - A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p. | 12-31-2015 |
| 20150380642 | TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 12-31-2015 |
| 20150380645 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a first metal and a second metal. The switching material is a second composition which includes the second metal. The second composition is directly against the first composition. Some embodiments include methods of forming memory cells. | 12-31-2015 |
| 20160005792 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR PRODUCING THE SAME - Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta | 01-07-2016 |
| 20160005961 | SEMICONDUCTOR DEVICE AND DIELECTRIC FILM - A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide containing at least one first element selected from Zn, Mg, Mn, Nb, Sc, Fe, Cr, Co, In, Li and N. | 01-07-2016 |
| 20160005962 | Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays - Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines. | 01-07-2016 |
| 20160005965 | MEMORY CELLS HAVING A FIRST SELECTING CHALCOGENIDE MATERIAL AND A SECOND SELECTING CHALCOGENIDE MATERIAL AND METHODS THEROF - The present disclosure includes memory cells and methods of forming the same. The memory cells disclosed herein can include a first selecting chalcogenide material, a second selecting chalcogenide material, and a storage material. | 01-07-2016 |
| 20160013246 | GATING DEVICE CELL FOR CROSS ARRAY OF BIPOLAR RESISTIVE MEMORY CELLS | 01-14-2016 |
| 20160013403 | MEMRISTORS WITH ASYMMETRIC ELECTRODES | 01-14-2016 |
| 20160013406 | VARIABLE RESISTIVE MEMORY DEVICE | 01-14-2016 |
| 20160013408 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME | 01-14-2016 |
| 20160020252 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer. | 01-21-2016 |
| 20160020255 | MEMORY HOLE BIT LINE STRUCTURES - Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion. | 01-21-2016 |
| 20160020256 | MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element. | 01-21-2016 |
| 20160020390 | PROTECTIVE SIDEWALL TECHNIQUES FOR RRAM - Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer. | 01-21-2016 |
| 20160020392 | CURRENT-LIMITING ELECTRODES - A resistive-switching memory (ReRAM cell) has a current-limiting electrode layer that combines the functions of an embedded resistor, an outer electrode, and an intermediate electrode, reducing the thickness of the ReRAM stack and simplifying the fabrication process. The materials include compound nitrides of a transition metal and one of aluminum, boron, or silicon. In experiments with tantalum silicon nitride, peak yield in the desired resistivity range corresponded to | 01-21-2016 |
| 20160028002 | FORMING SELF-ALIGNED CONDUCTIVE LINES FOR RESISTIVE RANDOM ACCESS MEMORIES - Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines. | 01-28-2016 |
| 20160028005 | MEMRISTOR STRUCTURE WITH A DOPANT SOURCE - A memristor including a dopant source is disclosed. The structure includes an electrode, a conductive alloy including a conducting material, a dopant source material, and a dopant, and a switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material. A method for fabricating the memristor including a dopant source is also disclosed. | 01-28-2016 |
| 20160028006 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction, A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer. | 01-28-2016 |
| 20160028007 | PHASE CHANGE MATERIAL SWITCH AND METHOD OF MAKING THE SAME - A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element. | 01-28-2016 |
| 20160028008 | ReRAM cells with diffusion-resistant metal silicon oxide layers - A metal silicon oxide barrier layer between a nitride electrode containing the same metal and an oxide variable-resistance layer in a ReRAM cell prevents the metal from diffusing into the variable-resistance layer and prevents oxygen from diffusing into and oxidizing the electrode. Compound oxides of the same metal and silicon with varying stoichiometries and metal/silicon ratios may optionally replace part or all of the variable-resistance layer, a defect-reservoir layer, or both. The metal nitride electrode may include a metal silicon nitride current-limiting portion. Optionally, all the layers sharing the common metal may be formed in-situ as part of a single unit process, such as atomic layer deposition. | 01-28-2016 |
| 20160035790 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. | 02-04-2016 |
| 20160035792 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films. | 02-04-2016 |
| 20160035973 | Directly Heated RF Phase Change Switch - An RF switch is provided with a direct heating method. The RF switch is comprised of two RF electrodes disposed on opposing sides of a phase change element. Depending on the state of the phase change material, the RF electrodes form a conductive path through the phase change material for an RF signal. To control the state of the phase change material, the RF switch further includes a heater formed from two heater electrodes. The two heater electrodes are configured to draw a current through the phase change element in a direction transverse to the conductive path. | 02-04-2016 |
| 20160035974 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells. | 02-04-2016 |
| 20160035975 | TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT - Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess. | 02-04-2016 |
| 20160043139 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function. | 02-11-2016 |
| 20160043140 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film. | 02-11-2016 |
| 20160043141 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device according to one embodiment includes a substrate, a first wiring placed on the substrate and extending in a first direction, a second wiring placed on the first wiring and extending in a second direction, a memory element coupled the first wiring and the second wiring, an engagement member coupled a portion of the second wiring, the portion is displaced from a region directly above the first wiring, a via engaged with the engagement member, a stopper member placed in a region including a region directly below the engagement member, and an interlayer insulating film provided on the substrate and covering the first wiring, the second wiring, the memory element, the engagement member, the via, and the stopper member. | 02-11-2016 |
| 20160043142 | TWO-TERMINAL SWITCHING ELEMENT HAVING BIDIRECTIONAL SWITCHING CHARACTERISTIC, RESISTIVE MEMORY CROSS-POINT ARRAY INCLUDING SAME, AND METHOD FOR MANUFACTURING TWO-TERMINAL SWITCHING ELEMENT AND CROSS-POINT RESISTIVE MEMORY ARRAY - Provided are a two-terminal switching element having a bidirectional switching characteristic, a resistive memory cross-point array including the same, and methods for manufacturing the two-terminal switching element and the cross-point resistive memory array. The two-terminal switching element includes a first electrode and a second electrode. A pair of first conductive metal oxide semiconductor layers electrically connected to the first electrode and the second electrode, respectively, is provided. A second conductive metal oxide semiconductor layer is disposed between the first conductive metal oxide semiconductor layers. Therefore, the two-terminal switching element can show a symmetrical and bidirectional switching characteristic. | 02-11-2016 |
| 20160043143 | FULLY ISOLATED SELECTOR FOR MEMORY DEVICE - A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction. | 02-11-2016 |
| 20160043310 | PROGRAMMABLE RESISTANCE MEMORY ELEMENTS WITH ELECTRODE INTERFACE LAYER AND MEMORY DEVICES INCLUDING THE SAME - A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material. | 02-11-2016 |
| 20160043311 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode. | 02-11-2016 |
| 20160043312 | MEMRISTORS WITH DOPANT-COMPENSATED SWITCHING - A memristor with dopant-compensated switching, the memristor having a bottom electrode, a top electrode, and an active region sandwiched between the bottom electrode and the top electrode. The active region is made up of an electrically insulating material and an electrically conducting material. The insulating material includes compensating dopants to partially or fully compensate for native dopants in the insulating material. Methods for making the memristor are also disclosed. | 02-11-2016 |
| 20160049446 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function. | 02-18-2016 |
| 20160049447 | RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE - A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line. | 02-18-2016 |
| 20160049583 | MEMORY STRUCTURE HAVING TOP ELECTRODE WITH PROTRUSION - The present disclosure relates to an RRAM (resistive random access memory) cell having a top electrode with a geometry configured to improve the electric performance of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a lower insulating layer with a micro-trench located over a lower metal interconnect layer disposed within a lower inter-level dielectric (ILD) layer that overlies a semiconductor substrate. A bottom electrode is disposed over the micro-trench, and a dielectric data storage layer is located over the bottom electrode. A top electrode is disposed over the dielectric data storage layer. The top electrode has a protrusion that extends outward from a bottom surface of the top electrode at a position overlying the micro-trench. The protrusion generates a region having an enhanced electric field within the dielectric data storage layer, which improves performance of the RRAM cell. | 02-18-2016 |
| 20160049584 | OXIDE FILM SCHEME FOR RRAM STRUCTURE - The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode. | 02-18-2016 |
| 20160049604 | Organic Resistive Random Access Memory and a Preparation Method Thereof - The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al | 02-18-2016 |
| 20160056376 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern. | 02-25-2016 |
| 20160056377 | NANOCHANNEL ARRAY OF NANOWIRES FOR RESISTIVE MEMORY DEVICES - A resistive memory structure includes two electrodes sandwiching an insulating region. The structure further includes a nanochannel array providing a conducting path between the two electrodes. The nanochannel array includes a plurality of nanowires that extends from one electrode to the other. | 02-25-2016 |
| 20160064453 | SELF-RECTIFYING RRAM CELL STRUCTURE AND RRAM 3D CROSSBAR ARRAY ARCHITECTURE - The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided. | 03-03-2016 |
| 20160064655 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING FERROELECTRIC MEMORY CELLS - A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material. | 03-03-2016 |
| 20160064657 | PHASE CHANGE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer. | 03-03-2016 |
| 20160064661 | RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material. | 03-03-2016 |
| 20160064662 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device includes first pillar-shaped silicon layers, a first gate insulating film formed around the first pillar-shaped silicon layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped silicon layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped silicon layers, second diffusion layers formed in lower portions of the first pillar-shaped silicon layers, and variable-resistance memory elements formed on the second contacts. | 03-03-2016 |
| 20160064663 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, second diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance films. | 03-03-2016 |
| 20160064664 | High K Scheme to Improve Retention Performance of Resistive Random Access Memory (RRAM) - An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided. | 03-03-2016 |
| 20160064665 | MATERIALS AND COMPONENTS IN PHASE CHANGE MEMORY DEVICES - Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith which includes carbon and tungsten doped with nitrogen are disclosed and described. Such electrodes have a low contact resistance with the phase change material and a high thermal stability from room temperature to temperatures needed for programming operations. | 03-03-2016 |
| 20160064666 | MEMORY CELLS INCLUDING DIELECTRIC MATERIALS, MEMORY DEVICES INCLUDING THE MEMORY CELLS, AND METHODS OF FORMING SAME - A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described. | 03-03-2016 |
| 20160071908 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit. | 03-10-2016 |
| 20160071909 | ELECTRONIC DEVICE HAVING FLASH MEMORY ARRAY FORMED IN AT DIFFERENT LEVEL THAN VARIABLE RESISTANCE MEMORY CELLS - An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. The first cell array, the first peripheral circuit, and the second peripheral circuit are formed at a first level over a surface of a semiconductor substrate, and the second cell array is disposed at a second level over the surface of a semiconductor substrate, the second level being higher than the first level. A portion of the second cell array overlaps in a plan view the second peripheral circuit and/or the first cell array. | 03-10-2016 |
| 20160072061 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer. | 03-10-2016 |
| 20160072062 | AL-W-O STACK STRUCTURE APPLICABLE TO RESISTIVE RANDOM ACCESS MEMORY - An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer. The invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, to obtain a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio. | 03-10-2016 |
| 20160079309 | RESISTANCE CHANGE MEMORY, METHOD OF MANUFACTURING RESISTANCE CHANGE MEMORY, AND FET - According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines. | 03-17-2016 |
| 20160079310 | SELECTOR-RESISTIVE RANDOM ACCESS MEMORY CELL - Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. | 03-17-2016 |
| 20160079522 | MEMORY DEVICE - According to one embodiment, a memory device includes a plug, a variable resistance film provided on the plug, and an electrode provided on the variable resistance film. The variable resistance film includes, a first portion having a superlattice structure, and a second portion having an amorphous structure. | 03-17-2016 |
| 20160079525 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers. | 03-17-2016 |
| 20160079526 | STORAGE DEVICE AND STORAGE UNIT - A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive. | 03-17-2016 |
| 20160087005 | Semiconductor Device with Variable Resistive Element - A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device. | 03-24-2016 |
| 20160087006 | 3-DIMENSIONAL STACK MEMORY DEVICE - A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type. | 03-24-2016 |
| 20160087009 | RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHODS - A resistive memory storage device includes a lower electrode, an upper electrode and a plurality of composite material layers disposed between the lower electrode and the upper electrode. Each composite material layer includes a first layer and a second layer. The first layer is a metal-based high-K dielectric material layer having a first metal element, and the second layer is a metal layer having the first metal element. | 03-24-2016 |
| 20160087010 | Semiconductor Constructions, and Methods of Forming Cross-Point Memory Arrays - Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode. | 03-24-2016 |
| 20160087196 | Strained Multilayer Resistive-Switching Memory Elements - The resistive-switching memory element of the present invention comprises a first electrode, a resistive-switching element; and a second electrode wherein the resistive-switching element is arranged between the first electrode and the second electrode and the resistive-switching element comprises, or consists of a plurality of metal oxide layers and wherein neighboring metal oxide layers of the resistive-switching element comprise, or consist of, different metal oxides. | 03-24-2016 |
| 20160087198 | RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory (RRAM) includes a top electrode (TE), a bottom electrode (BE), and a transition metal oxide (TMO) layer between the top and the bottom electrodes. The RRAM further includes a metal cap layer above the top electrode and a transparent metal oxide (TCO) layer between the metal cap layer and the top electrode. | 03-24-2016 |
| 20160087199 | RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode. | 03-24-2016 |
| 20160087200 | MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL - Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed. | 03-24-2016 |
| 20160087202 | ORGANIC MOLECULAR MEMORY - An organic molecular memory in an embodiment includes a first conductive layer; a second conductive layer; and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer including an organic molecule having an oligophenylene ethynylene backbone, the oligophenylene ethynylene backbone including three or more benzene rings, and the oligophenylene ethynylene backbone including two fluorine atoms added in ortho positions or meta positions of one of the benzene rings other than benzene rings at both ends. | 03-24-2016 |
| 20160087203 | ORGANIC MOLECULAR MEMORY - An organic molecular memory in an embodiment includes a first electrode having a first work function; a second electrode having a second work function; and an organic molecular layer provided between the first electrode and the second electrode, the organic molecular layer containing a first organic molecule chemically bonded to the first electrode, the first organic molecule having a resistance-change type molecular chain, and the first organic molecule having a first energy level higher than the first work function, and a second organic molecule chemically bonded to the second electrode and the second organic molecule having a second energy level higher than the second work function and lower than the first energy level. | 03-24-2016 |
| 20160087205 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAME - A resistive random access memory (RRAM) including a substrate, a dielectric layer, memory cells and an interconnect structure is provided. The dielectric layer is disposed on the substrate. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first electrode, a second electrode and a variable resistance structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode. In two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other. The interconnect structure is disposed in the dielectric layer and connects the first electrodes of the memory cells. | 03-24-2016 |
| 20160093671 | NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) - A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line. | 03-31-2016 |
| 20160093672 | LOGIC HIGH-K/METAL GATE 1T-1C RRAM MTP/OTP DEVICES - Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium oxalate and silicon dioxide. The method provides a bottom electrode (BE), wherein the BE is comprised of at least one of silicon or tungsten. | 03-31-2016 |
| 20160093800 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode and a second electrode. The memory device also includes a first variable resistance layer which is disposed between the first electrode and the second electrode. The memory device also includes a leakage current suppression layer which is disposed between the first electrode and the first variable resistance layer. The memory device also includes a second variable resistance layer which is disposed between the first electrode and the leakage current suppression layer. The memory device also includes a metal source layer which is disposed between the first electrode and the second variable resistance layer. In which metal oxide is contained in at least one of a boundary region in the first variable resistance layer to the leakage current suppression layer and a boundary region in the leakage current suppression layer to the first variable resistance layer. | 03-31-2016 |
| 20160093801 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a substrate, a first wiring layer including a first interconnect extending in a first direction which is disposed on the substrate, a second wiring layer including a second interconnect which is disposed so as to extend in a second direction intersecting the first direction above the first wiring layer, a memory cell which is disposed between the first interconnect and the second interconnect, and a pattern which is spaced from the memory cell. The memory cell and the pattern, respectively, includes a resistance change layer which is disposed between the first wiring layer and the second wiring layer, and an electrode layer which is provided below the second wiring layer and directly above the resistance change layer, and the memory cell further including a metal source layer which is provided between the resistance change layer and the electrode layer. | 03-31-2016 |
| 20160093802 | SELF-RECTIFYING RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE - A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer. | 03-31-2016 |
| 20160093803 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells. | 03-31-2016 |
| 20160093804 | LAMINATE DIFFUSION BARRIERS AND RELATED DEVICES AND METHODS - Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described. | 03-31-2016 |
| 20160099289 | SEMICONDUCTOR MEMORY DEVICE - A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position. | 04-07-2016 |
| 20160099290 | MEMORY DEVICE - According to one embodiment, a memory device includes a first gate electrode, a second gate electrode, a third gate electrode, a first active area and a second active area on a substrate. The first to the third gate electrodes extend in a first direction. The first active area and the second active area extend in a second direction. The first direction and the second direction cross each other. The memory device includes a first contact, a second contact, a third contact, a fourth contact, variable resistance layer, a first interconnection layer, a second interconnection layer and the second interconnection layer. The variable resistance layer and the first interconnection layer extend in the first direction. The second interconnection layer and the third interconnection layer extend in the second direction. | 04-07-2016 |
| 20160099291 | METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF - Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area. | 04-07-2016 |
| 20160099292 | RESISTANCE-CHANGE SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared. | 04-07-2016 |
| 20160104747 | APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY - Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described. | 04-14-2016 |
| 20160104748 | MEMORY CELL ARRAY STRUCTURES AND METHODS OF FORMING THE SAME - The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure. | 04-14-2016 |
| 20160104836 | CONDUCTIVE BRIDGE MEMORY SYSTEM AND METHOD OF MANUFACTURE THEREOF - A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer. | 04-14-2016 |
| 20160104837 | MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. | 04-14-2016 |
| 20160104838 | RESISTIVE RANDOM ACCESS MEMORY DEVICE HAVING A NANO-SCALE TIP, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF - The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized. | 04-14-2016 |
| 20160104839 | RESISTIVE RANDOM ACCESS MEMORY DEVICE HAVING NANO-SCALE TIP AND NANOWIRE, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF - A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode. | 04-14-2016 |
| 20160104840 | RESISTIVE MEMORY WITH A THERMALLY INSULATING REGION - A resistive memory includes a memory cell having a first electrode, a second electrode and a resistive memory element between the first electrode and the second electrode. The memory cell includes a thermally insulating region. The thermally insulating region may be included in at least one electrode of the memory cell and/or within an electrically insulating region. The thermally insulating region can confine heat within the memory cell and thereby can reduce the current and/or voltage needed to write information in the resistive memory element. | 04-14-2016 |
| 20160111636 | PHASE CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 04-21-2016 |
| 20160111638 | SWITCHING ELEMENT, SWITCHING ELEMENT MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - To provide a switching element having excellent operational stability and a high production yield, and a semiconductor device using the switching element, a switching element according to this invention includes a non-volatile resistive-change element, a rectifying element, and an insulating material. The non-volatile resistive-change element includes a first electrode, a second electrode, and a non-volatile resistive-change layer provided between the first electrode and the second electrode. The rectifying element includes the second electrode, a third electrode, and a volatile resistive-change layer provided between the second electrode and the third electrode. The insulating material is provided at least on the side surface of the third electrode. | 04-21-2016 |
| 20160111640 | RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory including two electrode layers and a multi-resistance layer mounted between the two electrode layers. The multi-resistance layer consists essentially of insulating material with oxygen and lithium ions. The number of resistance states of a memory element can be increased by the resistive random access memory to increase the integration density of a memory module having a plurality of memory elements. | 04-21-2016 |
| 20160111641 | MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - According to one embodiment, a memory device includes a substrate, a conductive wire provided above the substrate to extend in a first direction and including an end portion decreases in width toward a distal end, and a contact connected to the conductive wire at least a side surface of the end portion. The end portion includes, in the contact, a first portion having a shortest distance from an outer peripheral surface of the contact and a second portion extending from the first portion and having a distance from the outer peripheral surface of the contact longer than the shortest distance. | 04-21-2016 |
| 20160118441 | Switching Components and Memory Units - Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior. | 04-28-2016 |
| 20160118579 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR PRODUCING SAME - A resistive random access memory includes two electrode layers and a resistive switching layer mounted between the two electrode layers. The resistive switching layer consists essentially of insulating material with oxygen, metal material, and mobile ions. The polarity of the mobile ions is opposite to the polarity of oxygen ions. A method for producing a resistive random access memory includes preparing a first metal layer and sputtering a resistive switching layer on the first metal layer. Surface treatment is conducted on the resistive switching layer by using a plasma containing mobile ions to dope the mobile ions into the resistive switching layer. The polarity of the mobile ions is opposite to the polarity of oxygen ions. Then, a second metal layer is sputtered on the resistive switching layer. | 04-28-2016 |
| 20160126290 | Memory Arrays And Methods Of Forming An Array Of Memory Cell - A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed. | 05-05-2016 |
| 20160126292 | CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER - An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device. | 05-05-2016 |
| 20160133635 | FLASH CELL AND FLASH CELL SET - A flash cell includes a gate, a source/drain and a selector. The gate is disposed on a substrate, wherein the gate includes a control gate disposed on the substrate and a floating gate sandwiched by the control gate and the substrate. The source/drain is disposed in the substrate beside the gate. The selector electrically connects the source/drain, wherein the selector includes a bottom electrode, a resistance threshold switching material layer and a top electrode, and the resistance threshold switching material layer is sandwiched by the bottom electrode and the top electrode. A flash cell set includes a plurality of said flash cells. The flash cells electrically connect to each other by their selectors, and all of the selectors electrically connect to one same bit line. | 05-12-2016 |
| 20160133671 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void. | 05-12-2016 |
| 20160133835 | Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell - An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed. | 05-12-2016 |
| 20160141492 | MEMRISTOR AND METHODS FOR MAKING THE SAME - An example of the memristor includes a bottom electrode, a switchable material positioned on the bottom electrode, and a cured negative or positive resist that forms an interlayer dielectric positioned on the switchable material. An open area is formed in the interlayer dielectric. The open area exposes a surface of the switchable material. A top electrode is positioned in contact with the exposed surface of the switchable material at the open area. | 05-19-2016 |
| 20160141493 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first metal layer, a second metal layer, a first layer, a second layer, and a third layer. The first metal layer contains at least one first metal selected from the group consisting of Al, Ni, Ti, Co, Mg, Cr, Mn, Zn, and In. The second metal layer contains at least one second metal selected from the group consisting of Ag, Cu, Fe, Sn, Pb, and Bi. The first layer is provided between the first metal layer and the second metal layer, and contains a first oxide. The second layer is provided between the first layer and the second metal layer, and contains a second oxide. The third layer is provided between the first layer and the second layer, and contains one of a silicon oxide, a silicon nitride, and a silicon oxynitride. | 05-19-2016 |
| 20160141494 | RESISTIVE MEMORY DEVICE HAVING FIELD ENHANCED FEATURES - A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided. | 05-19-2016 |
| 20160148976 | Simultaneous Carbon and Nitrogen Doping of Si in MSM Stack as a Selector Device for Non-Volatile Memory Application - Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on a silicon semiconductor layer doped with both carbon and nitrogen. The metal layer of the selector element can include conductive materials such as carbon, tungsten, titanium nitride, or combinations thereof. | 05-26-2016 |
| 20160149125 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor integrated circuit device and a fabrication method thereof are disclosed. The resistive memory device includes a lower electrode, a resistive layer formed in a resistance change region on the lower electrode, an upper electrode formed on the resistive layer, and an insertion layer configured to allow a reset current path of the resistive layer, which is formed from the upper electrode to the lower electrode, to be bypassed in a direction perpendicular to or parallel to a surface of the lower electrode. | 05-26-2016 |
| 20160149128 | Diamond Like Carbon (DLC) as a Thermal Sink in a Selector Stack for Non-Volatile Memory Application - Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance. | 05-26-2016 |
| 20160149129 | Using Metal Silicides as Electrodes for MSM Stack in Selector for Non-Volatile Memory Application - Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The metal layer of the selector element can include conductive materials such as metal silicides, and metal silicon nitrides. Conductive materials of the MSM may include tantalum silicide, tantalum silicon nitride, titanium silicide, titanium silicon nitride, or combinations thereof. | 05-26-2016 |
| 20160155779 | STACK TYPE SEMICONDUCTOR MEMORY DEVICE | 06-02-2016 |
| 20160155938 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING MEMORY DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE | 06-02-2016 |
| 20160155940 | INORGANIC LIGHT EMITTING MEMORY AND METHOD FOR PRODUCING THE SAME | 06-02-2016 |
| 20160155941 | CHARGE ORDERED VERTICAL TRANSISTORS | 06-02-2016 |
| 20160163975 | BARRIER FILM TECHNIQUES AND CONFIGURATIONS FOR PHASE-CHANGE MEMORY ELEMENTS - Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, a top electrode layer disposed on the phase-change material layer, and a barrier film comprising a group IV transition metal, a group VI transition metal, carbon (C) and nitrogen (N), the barrier film being disposed between the bottom electrode layer and the top electrode layer. Other embodiments may be described and/or claimed. | 06-09-2016 |
| 20160163976 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING MEMORY DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A memory device includes a reset gate whose resistance changes. The memory device also includes a pillar-shaped phase-change layer, a reset gate insulating film surrounding the pillar-shaped phase-change layer, and the reset gate surrounding the reset gate insulating film. The pillar-shaped phase-change layer and the reset gate are electrically insulated from each other by the reset gate insulating film. | 06-09-2016 |
| 20160163977 | Doped Ternary Nitride Embedded Resistors for Resistive Random Access Memory Cells - Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, which is different from the first metal. The second metal may have less affinity to form covalent bonds with nitrogen than the first metal. As such, the second metal may be unbound and more mobile in the embedded resistor that the first metal. The second metal may help establishing conductive paths in the embedded resistor in addition to the metal nitride resulting in more a stable resistivity despite changing potential applies to the ReRAM cell. In other words, the embedded resistor having such composition will have more linear I-V performance. The concentration of the second metal in the embedded resistor may be substantially less than the concentration of the first metal. | 06-09-2016 |
| 20160163978 | TRANSITION METAL OXIDE RESISTIVE SWITCHING DEVICE WITH DOPED BUFFER REGION - A resistive switching memory comprising a first electrode and a second electrode; an active resistive switching region between the first electrode and the second electrode, the resistive switching region comprising a transition metal oxide and a dopant comprising a ligand, the dopant having a first concentration; a first buffer region between the first electrode and the resistive switching material, the first buffer region comprising the transition metal oxide and the dopant, wherein the dopant has a second concentration that is greater than the first concentration. In one embodiment, the second concentration is twice the first concentration. In one embodiment, the first buffer region is thicker than the active resistive switching region. | 06-09-2016 |
| 20160163979 | RESISTIVE MEMORY DEVICES - A resistive memory device includes: a first electrode; a variable resistive material layer that is formed on the first electrode and includes a metal oxide N | 06-09-2016 |
| 20160163980 | METHODS FOR FABRICATING A MEMORY DEVICE WITH AN ENLARGED SPACE BETWEEN NEIGHBORING BOTTOM ELECTRODES - Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls. | 06-09-2016 |
| 20160172587 | Memory Cells, Integrated Devices, and Methods of Forming Memory Cells | 06-16-2016 |
| 20160181321 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 06-23-2016 |
| 20160181324 | PHASE-CHANGE MEMORY CELL IMPLANT FOR DUMMY ARRAY LEAKAGE REDUCTION | 06-23-2016 |
| 20160181385 | Semiconductor Devices Having Buried Contact Structures and Methods of Manufacturing the Same | 06-23-2016 |
| 20160181515 | EMBEDDED PHASE CHANGE MEMORY DEVICES AND RELATED METHODS | 06-23-2016 |
| 20160181518 | CONDUCTIVE BRIDGING MEMORY DEVICE | 06-23-2016 |
| 20160181519 | INTERFACIAL CAP FOR ELECTRODE CONTACTS IN MEMORY CELL ARRAYS | 06-23-2016 |
| 20160181521 | VARIABLE RESISTANCE MATERIAL LAYERS AND VARIABLE RESISTANCE MEMORY DEVICES INCLUDING THE SAME | 06-23-2016 |
| 20160189775 | VOLTAGE CONTROL FOR CROSSPOINT MEMORY STRUCTURES - The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a diode disposed in parallel with the memory element between the first conductor and the second conductor. | 06-30-2016 |
| 20160190209 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 06-30-2016 |
| 20160190438 | PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE - Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described. | 06-30-2016 |
| 20160190439 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ENCAPSULATION FILM AND METHOD OF FABRICATING THE SAME - A semiconductor integrated circuit device and a method of fabricating the same are disclosed. The semiconductor integrated circuit device includes a resistive layer and an encapsulation film formed to surround an outer wall of the resistive layer The encapsulation film contains an oxygen absorbing ingredient. | 06-30-2016 |
| 20160190441 | Resistive Memory Cell With Sloped Bottom Electrode - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top. | 06-30-2016 |
| 20160190442 | Resistive Memory Cell Having A Reduced Conductive Path Area - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed. | 06-30-2016 |
| 20160190443 | Memory Arrays and Methods of Forming Memory Arrays - Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays. | 06-30-2016 |
| 20160190445 | ALL-PRINTED PAPER MEMORY - All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer. | 06-30-2016 |
| 20160197036 | ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY UNIT THAT INCLUDES CELL MATS OF A PLURALITY OF PLANES VERTICALLY STACKED | 07-07-2016 |
| 20160197121 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 07-07-2016 |
| 20160197271 | NON VOLATILE RESISTIVE MEMORY CELL AND ITS METHOD OF MAKING | 07-07-2016 |
| 20160197272 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | 07-07-2016 |
| 20160197273 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE | 07-07-2016 |
| 20160204343 | STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON | 07-14-2016 |
| 20160204344 | STRUCTURE AND FORMATION METHOD OF MEMORY DEVICE | 07-14-2016 |
| 20160254319 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE | 09-01-2016 |
| 20160254448 | NONLINEAR MEMRISTOR DEVICES WITH THREE-LAYER SELECTORS | 09-01-2016 |
| 20160380029 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, the second magnetic layer containing a material with a composition (lR | 12-29-2016 |
| 20160380191 | Techniques for Filament Localization, Edge Effect Reduction, and Forming/Switching Voltage Reduction in RRAM Devices - The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer. | 12-29-2016 |
| 20160380192 | Sidewall-Type Memory Cell - A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall. | 12-29-2016 |
| 20160380193 | TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT - Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess. | 12-29-2016 |
| 20160380194 | THERMAL MANAGEMENT STRUCTURE FOR LOW-POWER NONVOLATILE FILAMENTARY SWITCH - Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components. | 12-29-2016 |
| 20170236869 | HIGH DENSITY MULTI-TIME PROGRAMMABLE RESISTIVE MEMORY DEVICES AND METHOD OF FORMING THEREOF | 08-17-2017 |
| 20170236871 | IMPLEMENTATION OF VMCO AREA SWITCHING CELL TO VBL ARCHITECTURE | 08-17-2017 |
| 20170236872 | SEMICONDUCTOR MEMORY DEVICE | 08-17-2017 |
| 20170237000 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 08-17-2017 |
| 20170237001 | FABRICATION OF CORRELATED ELECTRON MATERIAL DEVICES COMPRISING NITROGEN | 08-17-2017 |
| 20170237002 | RESISTIVE SWITCHING CO-SPUTTERED PT-(NIO-AL2O3)-PT DEVICES | 08-17-2017 |
| 20180026026 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE RELATING TO AN ELECTRICAL OVER STRESS PROTECTING CIRCUIT | 01-25-2018 |
| 20180026076 | HIGH DENSITY MULTI-TIME PROGRAMMABLE RESISTIVE MEMORY DEVICES AND METHOD OF FORMING THEREOF | 01-25-2018 |
| 20180026077 | MEMORY DEVICE | 01-25-2018 |
| 20180026183 | NONVOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | 01-25-2018 |
| 20180026184 | RESISTANCE RANDOM ACCESS MEMORY DEVICE | 01-25-2018 |
| 20190148454 | SELECTOR-RESISTIVE RANDOM ACCESS MEMORY CELL | 05-16-2019 |
| 20190148455 | TWO-TERMINAL SWITCHING ELEMENT HAVING BIDIRECTIONAL SWITCHING CHARACTERISTIC, RESISTIVE MEMORY CROSS-POINT ARRAY INCLUDING SAME, AND METHOD FOR MANUFACTURING TWO-TERMINAL SWITCHING ELEMENT AND CROSS-POINT RESISTIVE MEMORY ARRAY | 05-16-2019 |
| 20190148456 | MEMORY DEVICE | 05-16-2019 |
| 20190148638 | Resistance Variable Memory Structure and Method of Forming the Same | 05-16-2019 |
| 20220140234 | SEMICONDUCTOR DEVICE INCLUDING RESISTANCE CHANGING LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer that are alternately stacked over the substrate. The semiconductor device includes a hole pattern penetrating the gate structure over the substrate, and a gate insulating layer, a channel layer, a resistor layer, and a resistance changing layer sequentially disposed on a sidewall surface of the gate structure within the hole pattern. Each of the resistor layer and the resistance changing layer is disposed opposite to the gate insulating layer, based on the channel layer. | 05-05-2022 |
| 20220140239 | Semiconductor structure and manufacturing method thereof - The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses. | 05-05-2022 |
