UNIMICRON TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20140264335 | PACKAGE SUBSTRATE AND METHOD FOR TESTING THE SAME - A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit. | 09-18-2014 |
20140263168 | METHOD FOR MANUFACTURING PACKAGE SUBSTRATE - A method for manufacturing a package substrate is provided, including etching a substrate to form trenches each having a buffer portion, and forming a circuit in each of the trenches. The trenches are formed by etching instead of excimer laser to increase the aspect ratio of the trench, thereby solving the problem that the metallic layer is not thick enough and achieving a high yield of the circuit and a good process capability index. | 09-18-2014 |
20140239490 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate and a fabrication method thereof are disclosed. The packaging substrate includes: a substrate body having a plurality of first and second conductive pads formed on a surface thereof; a first insulating layer formed on the surface of the substrate body and having a plurality of first and second openings for respectively exposing the first and second conductive pads; a conductive layer formed on the first and second conductive pads and the first insulating layer around peripheries of the first and second conductive pads; a plurality of first and second conductive bumps formed on the conductive layer on the first and second conductive pads, respectively; a solder layer formed on the second conductive bumps; and a plurality of conductive posts formed on the first conductive bumps and having a width different from that of the first conductive bumps. The invention improves the fabrication efficiency. | 08-28-2014 |
20140201992 | CIRCUIT BOARD STRUCTURE HAVING EMBEDDED ELECTRONIC ELEMENT AND FABRICATION METHOD THEREOF - A method for fabricating a circuit board structure having at least an embedded electronic element is disclosed, which includes the steps of: providing a substrate and embedding at least an electronic element in the substrate with an active surface and a plurality of electrode pads of the electronic element exposed from a surface of the substrate; forming a plurality of conductive bumps on the electrode pads of the electronic element; and covering the surface of the substrate and the active surface of the electronic element with a dielectric layer and a metal layer stacked on the dielectric layer, wherein the conductive bumps penetrate the dielectric layer so as to be in contact with the metal layer, thereby simplifying the fabrication process, reducing the fabrication cost and saving the fabrication time. | 07-24-2014 |
20140182912 | PACKAGING SUBSTRATE - A packaging substrate is provided, including a substrate body having a plurality of conductive pads, an insulating protective layer formed on the substrate body for the conductive pads to be exposed therefrom, and a plurality of conductive pillars disposed on the conductive pads. Each of the conductive pillars has a bottom end and a top end narrower than the bottom end, thereby forming a cone-shaped structure that does not have a wing structure. Therefore, the distance between contact points is reduced and the demands for fine-pitch and multi-joints are satisfied. | 07-03-2014 |
20140117557 | PACKAGE SUBSTRATE AND METHOD OF FORMING THE SAME - A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased. | 05-01-2014 |
20140110713 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated. | 04-24-2014 |
20140102777 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased. | 04-17-2014 |
20140090794 | METHOD OF FABRICATING PACKAGING SUBSTRATE - A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved. | 04-03-2014 |
20140084463 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect. | 03-27-2014 |
20140084413 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced. | 03-27-2014 |
20140076492 | FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS - A packaging substrate includes: a substrate having a core layer, a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; a first capacitor disposed in the cavity; a bonding layer formed on the first capacitor in the cavity of the substrate; a second capacitor disposed on the bonding layer so as to be received in the cavity; and a dielectric layer formed on the substrate and in the cavity for covering the first and second capacitors. By stacking the first and second capacitors in the cavity through the bonding layer, the single core layer is embedded with two layers of the capacitors to thereby meet the multi-function requirement. | 03-20-2014 |
20140035138 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 02-06-2014 |
20140027925 | THROUGH-HOLED INTERPOSER, PACKAGING SUBSTRATE, AND METHODS OF FABRICATING THE SAME - A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer. | 01-30-2014 |
20130335928 | CARRIER AND METHOD FOR FABRICATING CORELESS PACKAGING SUBSTRATE - A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes. | 12-19-2013 |
20130312911 | WET-ETCHING EQUIPMENT AND ITS SUPPLYING DEVICE - A supplying device including a supplying part and an adjustment part is provided. The supplying part includes a run-through supplying path for transporting a fluid. The adjustment part includes a channel and one or more recovery paths adjacent to the channel. The supplying part is disposed in the channel to allow the fluid to flow out of the channel through the supplying part and to allow the recovery paths to suck a portion of the etching solution outputted from the channel in order to control the amount of output of the fluid. Wet-etching equipment including the supplying device is also provided. | 11-28-2013 |
20130309817 | METHOD OF FABRICATING PACKAGE STRUCTURE - A package structure includes a metal sheet having perforations; a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has electrode pads thereon, conductive bumps are disposed on the electrode pads, the semiconductor chip is combined with the metal sheet via the inactive surface thereof, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip; an encapsulant formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps. A method of fabricating the package structure and a package-on-package device including the package structure are also provided. | 11-21-2013 |
20130258623 | PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an embedded electronic element includes: a substrate having two opposite surfaces and a cavity penetrating the two opposite surfaces; at least a metal layer disposed on the sidewall of the cavity and extending to the surfaces of the substrate; an electronic element disposed in the cavity and having a plurality of electrode pads disposed on side surfaces thereof; and a solder material electrically connecting the electrode pads of the electronic element and the metal layer, thereby effectively alleviating the problems of alignment difficulty and high fabrication cost as encountered in the prior art. | 10-03-2013 |
20130252380 | METHOD FOR FABRICATING PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT - A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. | 09-26-2013 |
20130249083 | PACKAGING SUBSTRATE - A packaging substrate is provided, wherein a plurality of conductive posts together with a conductive bonding layer formed thereon form a plurality of external connection structures with the same height, thereby preventing tilted stack structures and poor coplanarity in a subsequent stacking process. | 09-26-2013 |
20130230947 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented. | 09-05-2013 |
20130175687 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element, a second package structure having a plurality of second metal posts and a second electronic element, and an encapsulant formed between the first and second package structures to encapsulate the first electronic element. By connecting the second metal posts to the first metal posts, respectively, the second package structure is stacked on the first package structure with the support of the metal posts. Further, the gap between the two package structures is filled with the encapsulant to avoid warpage of the substrates. | 07-11-2013 |
20130147041 | STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls. | 06-13-2013 |
20130118680 | METHOD FOR FABRICATING A PACKAGING SUBSTRATE - A method for fabricating a packaging substrate includes: stacking two metal layers; | 05-16-2013 |
20130105943 | PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS AND FABRICATION METHOD THEREOF | 05-02-2013 |
20130105213 | PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER AND METHOD OF FABRICATING THE SAME | 05-02-2013 |
20130083503 | PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided. | 04-04-2013 |
20130062100 | CIRCUIT BOARD STRUCTURE - Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure. | 03-14-2013 |
20130040427 | FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN - A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. | 02-14-2013 |
20130032390 | PACKAGING SUBSTRATE HAVING EMBEDDED INTERPOSER AND FABRICATION METHOD THEREOF - A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability. | 02-07-2013 |
20130009306 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate. | 01-10-2013 |
20130009293 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved. | 01-10-2013 |
20130008706 | CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed. | 01-10-2013 |
20130008705 | CORELESS PACKAGE SUBSTRATE AND FABRICATION METHOD THEREOF - A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced. | 01-10-2013 |
20120314377 | PACKAGING STRUCTURE EMBEDDED WITH ELECTRONIC ELEMENTS AND METHOD OF FABRICATING THE SAME - A packaging structure is provided which includes: a substrate, at least an electronic module, and an adhesive material. The substrate has two opposing surfaces, at least an opening penetrating the two surfaces, and two metallic frames formed on two opening ends of the at least an opening. The electronic module is disposed in the opening and has electronic elements and an encapsulant encapsulating the electronic elements. Each of the electronic elements has two opposing active surfaces exposed from the encapsulant and electrode pads formed on the two opposing active surfaces. The electrode pads are exposed from the opening. The adhesive material is filled into the opening and a gap between the electronic module and the opening, so as to secure in position the electronic modules in the opening. Compared with the prior art, the embedded electronic elements of the packaging structure according to the present invention is prevented from short circuit, and thus has increased yield rate. | 12-13-2012 |
20120302012 | METHOD FOR FABRICATING PACKAGING SUBSTRATE WITH EMBEDDED SEMICONDUCTOR COMPONENT - A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively. | 11-29-2012 |
20120273941 | PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses. | 11-01-2012 |
20120273930 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect. | 11-01-2012 |
20120255771 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density. | 10-11-2012 |
20120228764 | PACKAGE STRUCTURE, FABRICATING METHOD THEREOF, AND PACKAGE-ON-PACKAGE DEVICE THEREBY - A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps. | 09-13-2012 |
20120217627 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure is provided that includes a metal plate; a semiconductor chip having an active surface, electrode pads disposed on the active surface, conductive bumps disposed on the electrode pads, and an inactive surface opposing the active surface and attached with the metal plate by a thermal conductive adhesive; an encapsulant formed on the metal plate for encapsulating a perimeter of the semiconductor chip, with the active surface of the semiconductor chip being exposed thereon; a first dielectric layer formed on the encapsulant and the active surface of the semiconductor chip, and having wiring trenches for exposing the conductive bumps; and a first wiring layer formed in the wiring trenches of the first dielectric layer and electrically connected to the conductive bumps. The wiring layer, through the electrical connection of the conductive bumps with the semiconductor chip prevents the use of bonding wires as a conductive pathway. | 08-30-2012 |
20120193789 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate. | 08-02-2012 |
20120168959 | PACKAGE SUBSTRATE HAVING A THROUGH HOLE AND METHOD OF FABRICATING THE SAME - A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit. | 07-05-2012 |
20120164854 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate is proposed, which includes: a circuit layer formed on a substrate and having conductive pads, an insulating protective layer formed on the substrate for covering the circuit layer and having openings for correspondingly exposing the conductive pads; copper bumps each having a connection portion formed in a corresponding one of the openings and electrically connected to a corresponding one of the conductive pads, and a protruding portion integrally connected to the connection portion and extending to a portion of the insulating protective layer surrounding the corresponding one of the openings, allowing the protruding portion to be greater in diameter than the connection portion, and a surface treatment layer having an electroplated nickel material formed on top surfaces of the protruding portions of the copper bumps, and an electroplated gold material formed on the electroplated nickel material. The surface treatment layer is not formed on side surfaces of the protruding portions, such that the thickness of the surface treatment layer is irrelevant to the diameter of the protruding portion. | 06-28-2012 |
20120146209 | PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN AND FABRICATION METHOD THEREOF - A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved. | 06-14-2012 |
20120120609 | PACKAGE STRUCTURE HAVING A SEMICONDUCTOR COMPONENT EMBEDDED THEREIN AND METHOD OF FABRICATING THE SAME - A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure. | 05-17-2012 |
20120104598 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 05-03-2012 |
20120097430 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate and a method of fabricating the packaging substrate. The packaging substrate includes: a dielectric layer that has an external contact surface and an opposing chip mounting surface; a circuit layer that is embedded in the dielectric layer and exposed from the external contact surface and the chip mounting surface, the circuit layer having wire-bonding pads, conductive pads, and a circuit that electrically connects the wire-bonding pads and the conductive pads, wherein the widths of the wire-bonding pads, conductive pads, and the circuit narrow gradually from chip mounting surface to the external contact surface; and a first insulating protective layer disposed on the external contact surface of the dielectric layer and covering the dielectric layer and the circuit layer, a plurality of conductive pad openings being formed in the first insulating protective layer for exposing the conductive pads. The dielectric layer is used directly as a foundation of the packaging substrate, thereby providing advantage in miniaturization, simpler fabrication procedure, and thus low cost production. | 04-26-2012 |
20120097429 | PACKAGE SUBSTRATE AND FABRICATION METHOD THEREOF - A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art. | 04-26-2012 |
20120037411 | PACKAGING SUBSTRATE HAVING EMBEDDED PASSIVE COMPONENT AND FABRICATION METHOD THEREOF - A packaging substrate includes: a core board with at least a cavity; a dielectric layer unit having upper and lower surfaces and encapsulating the core board and filling the cavity; a plurality of positioning pads embedded in the lower surface of the dielectric layer unit; at least a passive component having upper and lower surfaces with electrode pads disposed thereon and embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position corresponding to the positioning pads; first and second wiring layers disposed on the upper and lower surfaces of the dielectric layer unit and electrically connected to the electrode pads of the upper and lower surfaces of the passive component through conductive vias, respectively. By embedding the passive component in the core board and the dielectric layer unit, the invention effectively reduces the height of the overall structure. | 02-16-2012 |
20120037404 | PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN AND METHOD OF FABRICATING THE SAME - A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height. | 02-16-2012 |
20120032282 | MICROELECTROMECHANICAL SYSTEM (MEMS) CARRIER AND METHOD OF FABRICATING THE SAME - An MEMS carrier is provided that includes a core board having a first surface and an opposite second surface, a circuit layer formed on the first surface and having a plurality of conductive pads, and a through hole formed through the first and the second surfaces; a carrier layer formed on the second surface of the core board and covering an end of the through hole; a patterned metal layer formed on a portion of the carrier layer that covers the end of the through hole; a solder mask layer formed on the first surface of the core board and the circuit layer, wherein the solder mask layer has a plurality of openings for exposing the conductive pads; and a shielding metal layer disposed on a sidewall of the through hole, the patterned metal layer, and the portion of the carrier layer that covers the end of the through hole. Without the use of a circuit board, the MEMS carrier has reduced height and size. | 02-09-2012 |
20120013002 | PACKAGE STRUCTURE - Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance. | 01-19-2012 |
20120012962 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated. | 01-19-2012 |
20110097851 | METHOD OF FABRICATING A PACKAGE STRUCTURE - A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced. | 04-28-2011 |
20110097850 | METHOD OF FABRICATING A PACKAGING STRUCTURE - A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result. | 04-28-2011 |
20110057323 | PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening region predefined on the first surface; forming a first metallic frame around the periphery of the predefined opening region on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. The invention can precisely control the shape of the opening through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. | 03-10-2011 |
20110053318 | FABRICATION METHOD OF PACKAGE STRUCTURE - Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other. In the fabrication process, the alignment error between packaging substrate units in each packaging substrate block can be reduced by cutting the packaging substrate into packaging substrate blocks of appropriate size, thereby increasing the yield, and also the packaging of the semiconductor chips can be performed at the same time on all packaging substrate units in each substrate block so as to integrate fabrication of substrates with the packaging of semiconductor chips to simplify fabrication steps, thus increasing the productivity and reducing fabrication costs. | 03-03-2011 |
20110042128 | CORELESS PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided. | 02-24-2011 |
20110031606 | PACKAGING SUBSTRATE HAVING EMBEDDED SEMICONDUCTOR CHIP - A packaging substrate includes: a core board having opposite first and second surfaces and a cavity penetrating therethrough; a semiconductor chip disposed in the cavity and having an active surface with electrode pads and an opposite inactive surface; a first reinforcing dielectric layer containing a reinforcing material disposed on the first surface and the active surface and filling the gap between the chip and the cavity; a second reinforcing dielectric layer containing a reinforcing material disposed on the second surface and the inactive surface and filling the gap between the chip and the cavity; and first and second wiring layers disposed on the first and second reinforcing dielectric layers respectively and the first wiring layer electrically connecting to the electrode pads. The first and second reinforcing dielectric layers enhance the support force of the entire structure to thereby prevent delamination of the wiring layers from the dielectric layers and increase product yield and reliability. | 02-10-2011 |
20100319966 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A method for fabricating a packaging substrate includes: stacking two metal layers; encapsulating the two metal layers with assistant dielectric layers; forming built-up structures on the assistant dielectric layers, respectively; and separating the built-up structures along the interface between the two metal layers so as to form two packaging substrates. Owing to the adhesive characteristic of the assistant dielectric layers, the two metal layers are unlikely to separate from each other during formation of the built-up structures. But after portions of the dielectric layer around the periphery of the metal layers are cut and removed, the two metal layers can be readily separated from each other. The two metal layers can be patterned to form wiring layers, metal bumps, or supporting structures to avoid waste of materials. A packaging substrate and a fabrication method thereof are provided. | 12-23-2010 |
20100314037 | METHOD FOR FABRICATING PACKAGING SUBSTRATE - A method for fabricating a packaging substrate includes: providing a base having a release film with two opposite surfaces, two first auxiliary dielectric layers enclosing the release film, and two metal layers disposed on the two first auxiliary dielectric layers, therewith an effective area defined on the two metal layers; forming an inner wiring layer from the two metal layers; forming on each of the two first auxiliary dielectric layers and the inner wiring layers a built-up structure having first conductive pads so as for two initial substrates to be formed on the opposite surfaces of the release film; removing whatever is otherwise lying outside the effective area; removing the release film; and forming dielectric layer openings in the two first auxiliary dielectric layers so as for two substrate bodies to be formed from the initial substrates, wherein a portion of the inner wiring layers are exposed to thereby function as second conductive pads. | 12-16-2010 |
20100187003 | CIRCUIT BOARD STRUCTURE AND FABRICATION METHOD THEREOF - Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure. | 07-29-2010 |
20100108345 | LID FOR MICRO-ELECTRO-MECHANICAL DEVICE AND METHOD FOR FABRICATING THE SAME - A lid for a micro-electro-mechanical device and a method for fabricating the same are provided. The lid includes a board with opposite first and second surfaces and a first conductor layer. The first surface has a first metal layer thereon. The first metal layer and the board have a recess formed therein. The recess has a bottom surface and a side surface adjacent thereto. The first conductor layer is formed on the first metal layer and the bottom and side surfaces of the recess. The shielding effect of the side surface of the board is enhanced because of the recess integral to the board, the homogeneous bottom and side surfaces of the recess, and the first conductor layer covering the first metal layer, the bottom and side surfaces of the recess. Hence, the shielding effect upon the micro-electro-mechanical device is enhanced. | 05-06-2010 |
20100053920 | PACKAGING SUBSTRATE WITH EMBEDDED SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively. | 03-04-2010 |
20100052148 | PACKAGE STRUCTURE AND PACKAGE SUBSTRATE - Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps. | 03-04-2010 |
20100032827 | PACKAGE STRUCTURE - Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance. | 02-11-2010 |
20100006331 | Printed Circuit Board With Embedded Semiconductor Component and Method for Fabricating the Same - A printed circuit board having a semiconductor component embedded therein and a method of fabricating the same are proposed, including: providing a circuit board body having a through hole, a first surface and an opposing second surface both provided with a core circuit layer thereon; forming on the first surface a first dielectric layer with a dielectric-layer opening for exposing part of the first surface; forming a first circuit layer on the first dielectric layer, and forming first conductive vias in the first dielectric layer; fixing in position to the through hole a semiconductor chip having an active surface with electrode pads thereon; forming in the dielectric-layer opening a third dielectric layer for covering the active surface of the semiconductor chip; forming a third circuit layer on the third dielectric layer, and forming third conductive vias in the third dielectric layer. The printed circuit board thus fabricated is warpage-free. | 01-14-2010 |