| TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20160131708 | ON-CHIP EYE DIAGRAM CAPTURE - A system for capturing an eye diagram is disclosed. In various embodiments, the system includes: a delay line arranged to receive a digital signal and output a time delayed version of the digital signal; an edge detection circuit arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal; a voltage comparator arranged to receive the digital signal and a reference voltage, the voltage comparator operating to output a first signal when a voltage of the digital signal and the reference voltage are equal to each other; and a controller that includes: an edge detection circuit receiver connected to receive the output signal from the edge detection circuit; a delay line control circuit connected to provide a delay time control signal to the delay line; a voltage comparator receiver connected to receive the first signal from the voltage comparator; and a voltage control unit connected to provide a controlled voltage to the voltage comparator. | 05-12-2016 |
| 20160126309 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material. | 05-05-2016 |
| 20160118960 | SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE - A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal. | 04-28-2016 |
| 20160118580 | METHOD FOR FORMING RRAM CELL INCLUDING V-SHAPED STRUCTURE - A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer. | 04-28-2016 |
| 20160118471 | MECHANISM FOR FORMING METAL GATE STRUCTURE - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively. | 04-28-2016 |
| 20160118350 | INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure. | 04-28-2016 |
| 20160118336 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other. | 04-28-2016 |
| 20160114460 | METHOD OF FORMING DIAMOND CONDITIONERS FOR CMP PROCESS - A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process. | 04-28-2016 |
| 20160113099 | THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE - The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection. | 04-21-2016 |
| 20160111542 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure. | 04-21-2016 |
| 20160111541 | GATE LAST SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure. | 04-21-2016 |
| 20160111540 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure. | 04-21-2016 |
| 20160111420 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure. | 04-21-2016 |
| 20160111371 | STRUCTURE AND FORMATION METHOD OF DAMASCENE STRUCTURE - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. | 04-21-2016 |
| 20160104704 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance. | 04-14-2016 |
| 20160099337 | GATE STRUCTURE HAVING DESIGNED PROFILE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C. | 04-07-2016 |
| 20160099324 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate. | 04-07-2016 |
| 20160099216 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen. | 04-07-2016 |
| 20160093736 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure. | 03-31-2016 |
| 20160093606 | ESD PROTECTION FOR 2.5D/3D INTEGRATED CIRCUIT SYSTEMS - An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices. | 03-31-2016 |
| 20160089765 | SLURRY DISPERSION SYSTEM WITH REAL TIME CONTROL - A slurry dispersion system is provided, and includes a slurry source system, an in-line analyzer and a controller. The slurry source system provides a slurry for a chemical mechanical polishing (CMP) process. The in-line analyzer measures at least one parameter of a sampled slurry sampled from the slurry dispersion system, and generates an indication signal based on the parameter, in which the indication signal indicates at lease one characteristic of the slurry. The controller receives the indication signal, and generates a control signal based on the indication signal for performing a real time control on the slurry dispersion system for controlling quality of the slurry. | 03-31-2016 |
| 20160087037 | SEMICONDUCTOR STRUCTURE WITH STRAINED SOURCE AND DRAIN STRUCTURES AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid. | 03-24-2016 |
| 20160086945 | SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER HAVING PROTRUDING BOTTOM PORTION AND METHOD FOR FORMING THE SAME - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers. | 03-24-2016 |
| 20160079358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer. | 03-17-2016 |
| 20160071976 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack , and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure . The etch stop layer is in contact with the sealing structure. | 03-10-2016 |
| 20160071899 | METHOD FOR FORMING IMAGE-SENSOR DEVICE - A method for forming an image-sensor device is provided. The method includes providing a first semiconductor substrate having a first surface and a second surface opposite to the first surface. The method includes forming a device layer over the first surface of the first semiconductor substrate. The method includes bonding the first semiconductor substrate to a second semiconductor substrate after the formation of the device layer. The second surface faces the second semiconductor substrate. The method includes forming a diffusion layer between the first semiconductor substrate and the second semiconductor substrate. The diffusion layer has a dopant concentration gradient that increases in a direction from the first semiconductor substrate toward the second semiconductor substrate. | 03-10-2016 |
| 20160071805 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 03-10-2016 |
| 20160070843 | APPARATUS AND METHOD FOR E-BEAM WRITING - A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value. | 03-10-2016 |
| 20160064541 | VERTICAL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor. | 03-03-2016 |
| 20160064486 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations. | 03-03-2016 |
| 20160064483 | SEMICONDUCTOR STRUCTURE WITH CONTACT OVER SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H | 03-03-2016 |
| 20160064433 | BACKSIDE ILLUMINATED IMAGE SENSOR STRUCTURE - Backside illuminated image sensor structures are provided. The backside illuminated image sensor structure includes a device substrate having a frontside and a backside and pixels formed at the frontside of the substrate. The backside illuminated image sensor structure further includes a metal element formed in a dielectric layer over the backside of the substrate and a color filter layer formed over the dielectric layer. In addition, the metal element is configured to form a light blocking area in the device substrate and is made of copper. | 03-03-2016 |
| 20160049477 | III-V COMPOUND SEMICONDUCTOR DEVICE HAVING DOPANT LAYER AND METHOD OF MAKING THE SAME - A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer. | 02-18-2016 |
| 20160043576 | SYSTEM AND METHOD FOR INDUCTIVE WIRELESS SIGNALING - A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil. | 02-11-2016 |
| 20160043545 | ELECTROSTATIC DISCHARGE PROTECTION FOR THREE DIMENSIONAL INTEGRATED CIRCUIT - The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line. | 02-11-2016 |
| 20160043003 | MECHANISMS FOR FORMING FINFETS WITH DIFFERENT FIN HEIGHTS - Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation structures and a second isolation structure adjacent to the substrate. The first fin is partially surrounded by the first isolation structure and a second fin is partially surrounded by the second isolation structure, and the first isolation structure has a dopant concentration higher than that of the second isolation structure. | 02-11-2016 |
| 20160042964 | METHOD FOR REMOVING SEMICONDUCTOR FINS USING ALTERNATING MASKS - A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks. | 02-11-2016 |
| 20160041225 | CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES - A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element. | 02-11-2016 |
| 20160027501 | THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME - A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. | 01-28-2016 |
| 20160019943 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 01-21-2016 |
| 20150380521 | STRAINED SOURCE AND DRAIN (SSD) STRUCTURE AND METHOD FOR FORMING THE SAME - Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers. | 12-31-2015 |
| 20150380516 | DOPED PROTECTION LAYER FOR CONTACT FORMATION - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening. | 12-31-2015 |
| 20150379189 | TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION - Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium. | 12-31-2015 |
| 20150371860 | METHOD AND SYSTEM FOR THINNING WAFER THEREOF - A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided. | 12-24-2015 |
| 20150364593 | STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure. | 12-17-2015 |
| 20150364580 | STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of germanium greater than that of the epitaxially grown source/drain structure. | 12-17-2015 |
| 20150364579 | STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of carbon greater than that of the epitaxially grown source/drain structure. | 12-17-2015 |
| 20150363540 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 12-17-2015 |
| 20150349125 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure also includes a gate electrode formed over the fin structure, and the gate electrode has a grid-like pattern when seen from a top-view. | 12-03-2015 |
| 20150349045 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion. | 12-03-2015 |
| 20150349020 | MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE - A method for fabricating an image-sensor device is provided. The method includes forming a radiation-sensing region and a doped isolation region in a semiconductor substrate. The doped isolation region is adjacent to the radiation-sensing region. The method also includes thinning the semiconductor substrate such that the radiation-sensing region and the doped isolation region are exposed. The method further includes partially removing the doped isolation region to form a recess. In addition, the method includes forming a negatively charged film over an interior surface of the recess and a surface of the radiation-sensing exposed after the thinning of the semiconductor substrate. | 12-03-2015 |
| 20150348965 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL GATE - A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure also includes a dielectric structure over the semiconductor substrate and adjacent to the gate stack. The dielectric structure is in direct contact with the work function layer and the metal filling. | 12-03-2015 |
| 20150348856 | PLANARIZATION METHOD, METHOD FOR POLISHING WAFER, AND CMP SYSTEM - A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light. | 12-03-2015 |
| 20150348847 | SUBSTRATE HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD - A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate. | 12-03-2015 |
| 20150348838 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer. | 12-03-2015 |
| 20150348779 | COATING APPARATUS AND METHOD OF FORMING COATING FILM - A method of forming a coating film over a substrate is provided. The method includes spinning the substrate. The method further includes providing a central coating liquid spray over a central portion of the substrate. The method also includes providing first coating liquid sprays over the substrate. The first coating liquid sprays surround the central coating liquid spray and are spaced apart from the central coating liquid spray by a same first distance. | 12-03-2015 |
| 20150333173 | SPLIT GATE MEMORY DEVICES AND METHODS OF MANUFACTURING - Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device. | 11-19-2015 |
| 20150333054 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 11-19-2015 |
| 20150333021 | SEMICONDUCTOR STRUCTRURE WITH COMPOSITE BARRIER LAYER UNDER REDISTRIBUTION LAYER AND MANUFACTURING METHOD THEREOF - A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer. | 11-19-2015 |
| 20150331309 | RETICLE AND METHOD OF FABRICATING THE SAME - A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion. | 11-19-2015 |
| 20150330885 | APPARATUS AND METHOD FOR INSPECTING FILTERING CARTRIDGE - An apparatus applicable to a storage container is provided and includes a filtering cartridge, a gas supply device and a particle counter. The filtering cartridge is configured to be disposed on the storage container. The filtering cartridge includes a flexible housing and a filter. The flexible housing has a first portion and a second portion opposite to the first portion. The flexible housing includes a gas inlet, a first gas outlet and a second gas outlet. The gas inlet is disposed on the first portion. The first gas outlet is disposed on the first portion. The second gas outlet is disposed on the second portion and connected to the storage container. The filter is disposed over the second gas outlet. The gas supply device is connected to the gas inlet, thereby purging gas into the flexible housing. The particle counter is connected to the first gas outlet. | 11-19-2015 |
| 20150329353 | SENSOR INTEGRATION WITH AN OUTGASSING BARRIER AND A STABLE ELECTRICAL SIGNAL PATH - The present disclosure relates to a structure and method of forming a MEMS-CMOS integrated circuit with an outgassing barrier and a stable electrical signal path. An additional poly or metal layer is embedded within the MEMS die to prevent outgassing from the CMOS die. Patterned conductors formed by a damascene process and a direct bonding between the two dies provide a stable electrical signal path. | 11-19-2015 |
| 20150325690 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer, a metal gate over the gate dielectric layer, a first insulating layer over the metal gate and a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different. The semiconductor device structure also includes spacers over opposite sidewalls of the gate stack. The spacers and the metal gate surround a recess, and the first insulating layer and the second insulating layer are in the recess. | 11-12-2015 |
| 20150325646 | STRUCTURES AND FORMATION METHODS OF FINFET DEVICE - A semiconductor device includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device also includes a first epitaxial fin and a second epitaxial fin over the semiconductor substrate, and the first epitaxial fin and the second epitaxial fin protrude from the isolation structure. The semiconductor device further includes a gate stack over and traversing the first epitaxial fin and the second epitaxial fin. In addition, the semiconductor device includes a recess extending from a top surface of the isolation structure. The recess is between the first epitaxial fin and the second epitaxial fin. | 11-12-2015 |
| 20150311159 | ELECTROMAGNETIC BANDGAP STRUCTURE FOR THREE DIMENSIONAL ICS - An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die. | 10-29-2015 |
| 20150311140 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar. | 10-29-2015 |
| 20150309414 | METHOD AND TOOL OF LITHOGRAPHY - A tool and a method of lithography are provided. In various embodiments, the method of lithography includes forming a photoresist layer on a substrate. The method further includes exposing the photoresist layer to form an exposed photoresist layer. The method further includes rinsing the exposed photoresist layer. The method further includes treating the exposed photoresist layer with a chemical modifier to form a modified photoresist layer. The method further includes baking the modified photoresist layer. The method further includes developing the modified photoresist layer. | 10-29-2015 |
| 20150309405 | METHOD OF MAKING AN EXTREME ULTRAVIOLET PELLICLE - The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film. | 10-29-2015 |
| 20150309404 | PELLICLE STRUCTURE AND METHOD FOR FORMING THE SAME - A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame. | 10-29-2015 |
| 20150309401 | LITHOGRAPHY SYSTEM AND METHOD FOR PATTERNING PHOTORESIST LAYER ON EUV MASK - A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor. | 10-29-2015 |
| 20150306737 | CHEMICAL MECHANICAL POLISHING PAD - The present disclosure relates to a radiance decomposable CMP pad, and an associated method to refresh the CMP pad. In some embodiments, the CMP pad has a polymer layer and some macro pores disposed therein. A monomer of the polymer layer has a photoactive compound unit. | 10-29-2015 |
| 20150296563 | BAKING APPARATUS FOR PRIMING SUBSTRATE - A baking apparatus for priming a substrate is provided, which includes a chamber, a hot plate and a barrier element. The hot plate is in the chamber and configured to bake the substrate on the hot plate. The barrier element is in contact with a periphery of the substrate and the hot plate to prevent contamination on a lower surface of the substrate. Another baking apparatus for priming a substrate is also provided, which includes a chamber and a hot plate. The hot plate is in the chamber and in full contact with a lower surface of the substrate to prevent contamination thereon. | 10-15-2015 |
| 20150295172 | RRAM Cell with Bottom Electrode - The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell. | 10-15-2015 |
| 20150295085 | Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices - The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance. | 10-15-2015 |
| 20150295063 | MECHANISM FOR FORMING METAL GATE STRUCTURE - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate and forming a metal gate stack including a metal gate electrode over the semiconductor substrate. The method also includes applying an oxidizing solution containing an oxidizing agent over the metal gate electrode to oxidize the metal gate electrode to form a metal oxide layer on the metal gate electrode. | 10-15-2015 |
| 20150295020 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer. | 10-15-2015 |
| 20150295019 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor. | 10-15-2015 |
| 20150295005 | DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS - Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench. | 10-15-2015 |
| 20150294968 | FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) - A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device. | 10-15-2015 |
| 20150294963 | METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV) - Method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV. | 10-15-2015 |
| 20150294936 | MIM CAPACITOR STRUCTURE - The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication. | 10-15-2015 |
| 20150294914 | Flexible Device Modulation By Oxide Isolation Structure Selective Etching Process - A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device. | 10-15-2015 |
| 20150288940 | PIXEL ARRAY WITH CLEAR AND COLOR PIXELS EXHIBITING IMPROVED BLOOMING PERFORMANCE - This disclosure provides pixel arrays made up of a clear pixel and a color pixel. The color pixel includes a first photo-detecting element and a color pixel access transistor to selectively couple the first photo-detecting element to a first charge-storage node. The clear pixel includes a second photo-detecting element and a clear pixel access transistor to selectively couple the second photo-detecting element to a second charge-storage node. The color pixel access transistor transfers a first charge per unit time between the first photo-detecting element and the first charge-storage node. The clear pixel access transistor transfers a second charge per unit time between the clear pixel access transistor and the second charge-storage node. The first charge per unit time is less than the second charge per unit time to mitigate blooming. In other embodiments, the clear pixel includes an excess-charge transfer path that couples the clear pixel to a DC supply node to mitigate blooming. | 10-08-2015 |
| 20150287918 | RRAM CELL BOTTOM ELECTRODE FORMATION - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved. | 10-08-2015 |
| 20150287605 | METHOD FOR FORMING GATE DIELECTRIC LAYER - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer. | 10-08-2015 |
| 20150286765 | CUT MASK DESIGN LAYERS TO PROVIDE COMPACT CELL HEIGHT - Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer. | 10-08-2015 |
| 20150284240 | STRUCTURES AND FORMATION METHODS OF MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - A micro-electro mechanical system (MEMS) device is provided. The MEMS device includes a cap substrate and a MEMS substrate bonded with the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber between the MEMS substrate and the cap substrate, and the first movable element is in the first closed chamber. The MEMS device further includes an outgassing layer in the first closed chamber. In addition, the MEMS device includes a second closed chamber between the MEMS substrate and the cap substrate, and the second movable element is in the second closed chamber. | 10-08-2015 |
| 20150280004 | EMBEDDED NONVOLATILE MEMORY - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 10-01-2015 |
| 20150279849 | SILICON NITRIDE (SiN) ENCAPSULATING LAYER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation. | 10-01-2015 |
| 20150279729 | Semiconductor Structure With Anti-Etch Structure In Via And Method For Manufacturing The Same - A semiconductor structure includes a semiconductor substrate, a dielectric layer formed over the semiconductor substrate, a first anti-etch layer, a second anti-etch layer and a conductive material. The dielectric layer has an opening. The first anti-etch layer is formed on the sidewall of the opening and made of a material having resistance to peroxide. The second anti-etch layer is formed over the first anti-etch layer and made of a material having resistance to acid. The conductive material is formed within the opening and in contact with the second anti-etch layer. | 10-01-2015 |
| 20150278428 | CELL BOUNDARY LAYOUT - Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance. | 10-01-2015 |
| 20150277231 | LIGHT TRANSMISSION DEVICE AND METHOD FOR SEMICONDUCTOR MANUFACTURING PROCESS - A light transmission device is provided. The light transmission device includes a light source, a light transmission module and at least one light regulator. The light transmission module transmits a portion of the light of the light source for implementing a first semiconductor manufacturing process over the wafer. The light source is utilized to implement a second semiconductor manufacturing process over a wafer. The first semiconductor manufacturing process is different from the second semiconductor manufacturing process. The at least one light regulator regulates the light of the light transmission module transmitted to the wafer. | 10-01-2015 |
| 20150270371 | COMPOUND SEMICONDUCTOR DEVICE HAVING GALLIUM NITRIDE GATE STRUCTURES - The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer. | 09-24-2015 |
| 20150270275 | DAMASCENE NON-VOLATILE MEMORY CELLS AND METHODS FOR FORMING THE SAME - A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode. | 09-24-2015 |
| 20150270260 | ESD PROTECTION CIRCUIT CELL - A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd | 09-24-2015 |
| 20150270215 | VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER - The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening. | 09-24-2015 |
| 20150270103 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 09-24-2015 |
| 20150269997 | Resistive Memory Array - A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line. | 09-24-2015 |
| 20150264233 | IMAGE SENSOR DEVICE WITH LIGHT GUIDING STRUCTURE - An image sensor device and a manufacturing method for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate having an array region and a periphery region. The image sensor device also includes a light sensing region in the array region of the semiconductor substrate. The image sensor device further includes a dielectric structure over the array region and the periphery region, and the dielectric structure has a substantially planar top surface. In addition, the image sensor device includes a recess in the dielectric structure and substantially aligned with the light sensing region. The image sensor device also includes a filter in the recess and a light blocking grid in the dielectric structure and surrounding a portion of the filter. | 09-17-2015 |
| 20150263164 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAWKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 09-17-2015 |
| 20150263073 | RRAM ARRAY HAVING LATERAL RRAM CELLS AND VERTICAL CONDUCTING STRUCTURES - An RRAM array is provided. The RRAM array includes a plurality of horizontal electrode lines elongated in a horizontal direction. The RRAM array also includes a plurality of conducting structures elongated in a vertical direction. Each of the conducting structures includes a plurality of electrode blocks and a plurality of contact vias which are alternately arranged. The electrode blocks and the electrode lines are on the same horizontal planes. The RRAM array further includes a plurality of resistance variable elements sandwiched between the electrode lines and the electrode blocks. | 09-17-2015 |
| 20150263015 | FLASH MEMORY STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer. | 09-17-2015 |
| 20150263010 | Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary. | 09-17-2015 |
| 20150262955 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD - A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. | 09-17-2015 |
| 20150262954 | SOLDER STUD STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate. | 09-17-2015 |
| 20150262953 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD - A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed. | 09-17-2015 |
| 20150262952 | BUMP STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a seed layer formed over the metal pad and a conductive pillar formed over the seed layer. In addition, the seed layer has a sidewall and a bottom surface, and an angle between the sidewall and the bottom surface of the seed layer is in a range from about 20° to about 90°. | 09-17-2015 |
| 20150262951 | BUMP STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction. | 09-17-2015 |
| 20150262846 | PACKAGE STRUCTURE AND MANUFACTURING METHOD - A package structure and a manufacturing method are provided. The package structure includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The package structure also includes a substrate and a second conductive feature over the substrate. The second conductive feature is bonded with the first conductive feature through a bonding structure. The package structure further includes a protection material surrounding the bonding structure, and the protection material is in direct contact with a side surface of the first conductive feature. | 09-17-2015 |
| 20150262812 | CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS - An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate. | 09-17-2015 |
| 20150262655 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 09-17-2015 |
| 20150262629 | APPARATUS AND METHOD FOR SENSE AMPLIFYING - A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted V | 09-17-2015 |
| 20150260783 | SPLIT GATE STRUCTURE AND METHOD OF USING SAME - A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB. | 09-17-2015 |
| 20150255718 | RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER - The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. | 09-10-2015 |
| 20150255604 | WRAP AROUND CONTACT - Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces. | 09-10-2015 |
| 20150255575 | CONTACTS FOR TRANSISTORS - The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region. | 09-10-2015 |
| 20150255330 | BARRIER-SEED TOOL FOR FINE-PITCHED METAL INTERCONNECTS - A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix. | 09-10-2015 |
| 20150255303 | HARD MASK REMOVAL SCHEME - A method for hard mask layer removal includes dispensing a chemical on a hard mask layer, in which the chemical includes an acidic chemical. The chemical is drained from a chamber after hard mask removal. | 09-10-2015 |
| 20150255272 | SYSTEM, METHOD AND RETICLE FOR IMPROVED PATTERN QUALITY IN EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY AND METHOD FOR FORMING THE RETICLE - A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained. | 09-10-2015 |
| 20150255268 | METHOD FOR FABRICATING OXIDES/SEMICONDUCTOR INTERFACES - By depositing a layer of metal on the semiconductor surface where the metal is deposited in a non-oxidized state first and then depositing a layer of the high-k oxide material over the layer of metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface. | 09-10-2015 |
| 20150252475 | CVD APPARATUS WITH GAS DELIVERY RING - The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber. | 09-10-2015 |
| 20150251132 | AIR WASHER OF MAKE-UP AIR UNIT - An air washer includes a contamination removal membrane and a nozzle rack. The contamination removal membrane purifies an outdoor air for a clean room. The nozzle rack sprays water on the contamination removal membrane. The nozzle rack includes a supply pipe, a plurality of spray pipes connecting to the supply pipe and a plurality of nozzles fixed on the spray pipes to spray the water on the contamination removal membrane. The contamination removal membrane is a cellulose paper sheet, an agglomeration ceramic pad, a stainless steel filter or the combination thereof. In addition, a make-up air unit having the air washer is also disclosed therein. | 09-10-2015 |
| 20150249436 | MULTI-STAGE AMPLIFIER WITH PULSE WIDTH MODULATION (PWM) NOISE SHAPING - A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load. | 09-03-2015 |
| 20150249141 | SEMICONDUCTOR TRANSISTOR DEVICE WITH DOPANT PROFILE - A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel. | 09-03-2015 |
| 20150249080 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION - An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor. | 09-03-2015 |
| 20150249051 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 09-03-2015 |
| 20150249024 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 09-03-2015 |
| 20150248517 | ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE - A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells. | 09-03-2015 |
| 20150246425 | POLISHING APPARATUS AND POLISHING METHOD - Embodiments of a polishing apparatus are provided. The polishing apparatus includes a polishing pad having a polishing surface. The polishing apparatus also includes a dispensing device including a dispensing arm located over the polishing pad and a liquid nozzle disposed on the dispensing arm. The liquid nozzle is configured to dispense washing liquid onto the polishing surface along a dispensing direction. The dispensing direction has an acute angle with respect to the polishing surface. | 09-03-2015 |
| 20150243805 | IMAGE SENSOR DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate including a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a light-blocking structure positioned in the trench to absorb or reflect incident light. | 08-27-2015 |
| 20150243759 | COUNTER POCKET IMPLANT TO IMPROVE ANALOG GAIN - A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region. | 08-27-2015 |
| 20150243750 | III-V COMPOUND SEMICONDUCTOR DEVICE HAVING METAL CONTACTS AND METHOD OF MAKING THE SAME - A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound. | 08-27-2015 |
| 20150243746 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure. | 08-27-2015 |
| 20150243730 | MULTI-STEP METHOD OF FORMING A METAL FILM - The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes). | 08-27-2015 |
| 20150243697 | IMAGE SENSOR DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%. | 08-27-2015 |
| 20150243696 | IMAGE SENSOR DEVICE WITH LIGHT BLOCKING STRUCTURE - The disclosure provides an image sensor device and a manufacturing method. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a light blocking structure in the semiconductor substrate and adjacent to the light sensing region. A sidewall of the light blocking structure is a curved surface. | 08-27-2015 |
| 20150243653 | Shallow Trench Isolation Structure - A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess. | 08-27-2015 |
| 20150243643 | 3D IC WITH SERIAL GATE MOS DEVICE, AND METHOD OF MAKING THE 3D IC - A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV. | 08-27-2015 |
| 20150243630 | DIE STACKING APPARATUS AND METHOD - Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device. | 08-27-2015 |
| 20150243600 | CONDUCTIVE LINE ROUTING FOR MULTI-PATTERNING TECHNOLOGY - A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns. | 08-27-2015 |
| 20150243537 | MECHANISMS FOR CLEANING SUBSTRATE SURFACE FOR HYBRID BONDING - The mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. The mechanisms for a hybrid bonding and a integrated system are also provided. | 08-27-2015 |
| 20150243495 | APPARATUS AND PROCESS FOR WAFER CLEANING - A process and apparatus for cleaning a wafer, the wafer having a front side and a back side, are provided. The process begins with placing the wafer on a platform, and a first gas stream delivering in a direction from a center to an edge of the front side of the wafer. The first gas stream prevents liquid drops entering a work piece region on the front side of the wafer and protects the integrity of the integrated circuits. A cleaning brush is rinsed by a first liquid stream and contacting the edge of the wafer for cleaning the wafer. The cleaning brush scrubs unwanted residual materials from the edge of the wafer, and the first liquid stream flushes the cleaning brush to recover the cleaning ability. | 08-27-2015 |
| 20150241902 | Integrated Circuit With Transistor Array And Layout Method Thereof - An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array. | 08-27-2015 |
| 20150241789 | IN-LINE INSPECTION AND CLEAN FOR IMMERSION LITHOGRAPHY - An immersion lithography apparatus includes a lens system, an immersion hood, a wafer stage, an inspection system and a cleaning fluid supplier. The lens system is configured to project a pattern onto a wafer. The immersion hood is configured to confine an immersion fluid between the lens system and the wafer, and includes a peripheral hole configured to suck up the immersion fluid. The wafer stage is configured to position the wafer under the lens system. The inspection system is configured to detect whether there is contamination in the peripheral hole. The cleaning fluid supplier is coupled to the inspection system and configured to supply a cleaning fluid through the peripheral hole to remove the contamination, in which the inspection system and the cleaning fluid supplier are coupled to the wafer stage. | 08-27-2015 |
| 20150241786 | Tool And Method Of Developing - A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer. | 08-27-2015 |
| 20150241507 | Test Circuit And Method - A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas. | 08-27-2015 |
| 20150241471 | Probe Card - An apparatus and a method are disclosed herein. The apparatus includes a circuit board, a housing, a spacer and a pin. The circuit board is configured to test a device-under-test (DUT). The housing includes a raised portion and a supporting portion. The spacer is mounted on the supporting portion of the housing. The pin penetrates through the raised portion and the supporting portion of the housing, and is configured to electrically connect the circuit board to the DUT. | 08-27-2015 |
| 20150236157 | Transistor Strain-Inducing Scheme - A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess. | 08-20-2015 |
| 20150236132 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure. | 08-20-2015 |
| 20150236131 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure. | 08-20-2015 |
| 20150236110 | SPLIT GATE CELLS FOR EMBEDDED FLASH MEMORY - In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer. | 08-20-2015 |
| 20150236030 | Split Gate Memory Device and Method of Fabricating the Same - The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them. | 08-20-2015 |
| 20150235897 | Reverse Tone Self-Aligned Contact - Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact. | 08-20-2015 |
| 20150235879 | DEVICE AND METHOD FOR WAFER TAPING - In accordance with some embodiments, a wafer taping device is provided. The wafer taping device includes a tape delivering along a first direction. The wafer taping device also includes a wafer mount unit disposed below the tape. The wafer mount unit has an upper surface for supporting a wafer and having a notch for allowing a cut mark of the wafer to align with it. The notch is staggered with a second direction in the upper surface, and the second direction is substantially perpendicular to the first direction. In addition, the wafer taping device includes a laminating roller disposed above the wafer mount unit and having a long axis elongated in the second direction. The laminating roller is configured to reciprocate along the first direction for pressing the tape to the wafer. | 08-20-2015 |
| 20150235858 | WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES - A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads. | 08-20-2015 |
| 20150235823 | PLASMA APPARATUS, MAGNETIC-FIELD CONTROLLING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process. | 08-20-2015 |
| 20150234979 | SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS - A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns. | 08-20-2015 |
| 20150229287 | Device For Blocking High Frequency Signal And Passing Low Frequency Signal - A device is disclosed that includes a transmission plate, a conductive plate, and a capacitive unit. The transmission plate includes a winding structure and is configured to be electrically coupled between an input source and a load. The conductive plate is configured to be electrically coupled to ground. The capacitive unit is electrically coupled between the conductive plate and the transmission plate. | 08-13-2015 |
| 20150228791 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 08-13-2015 |
| 20150228770 | Robust ESD Protection with Silicon-Controlled Rectifier - Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane. | 08-13-2015 |
| 20150228763 | NON-PLANAR FIELD EFFECT TRANSISTOR HAVING A SEMICONDUCTOR FIN AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. | 08-13-2015 |
| 20150228746 | MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE - Methods of modifying a self-aligned contact process in a semiconductor fabrication and a semiconductor device are provided. A method includes forming a transistor over a substrate, including depositing a high-k dielectric layer over the substrate; depositing a work function metal layer over the high-k dielectric layer; forming a metal gate over the work function metal layer; forming two spacers sandwiching the work function metal layer and the metal gate; and forming a doped region in the substrate; etching the work function metal layer and the metal gate to leave a metal residue over inner walls of the two spacers exposing the work function metal layer and the metal gate; modifying the metal residue and the exposed work function metal layer and metal gate to form a metal compound; depositing an insulator covering the metal compound; and forming contact pads respectively electrically connected to the metal gate and the doped region. | 08-13-2015 |
| 20150228646 | GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME - Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure. | 08-13-2015 |
| 20150228593 | Under Bump Metallization - A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved. | 08-13-2015 |
| 20150228537 | Contact Critical Dimension Control - In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole. | 08-13-2015 |
| 20150228534 | Semiconductor Device With Shallow Trench Isolation - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide. | 08-13-2015 |
| 20150228472 | Sacrificial Oxide With Uniform Thickness - A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer. | 08-13-2015 |
| 20150227050 | METHOD AND APPARATUS FOR BAKING PHOTORESIST PATTERNS - In accordance with some embodiments, a method and an apparatus for baking photoresist patterns are provided. The method includes putting a wafer over a heating assembly. A photoresist pattern is formed over a top surface of the wafer. The method further includes curing the wafer from the top surface of the wafer by a curing assembly while heating the wafer from a bottom surface of the wafer by a heating assembly. | 08-13-2015 |
| 20150224624 | ABRASIVE ARTICLE, CONDITIONING DISK AND METHOD FOR FORMING ABRASIVE ARTICLE - In accordance with some embodiments, an abrasive article is provided. The abrasive article includes a carrier. The abrasive article further includes a matrix layer on the carrier. The matrix layer includes a copper-titanium-tin alloy, wherein the copper-titanium-tin alloy includes from about 70 wt % to about 90 wt % of copper, from about 5 wt % to about 15 wt % of titanium, and from about 5 wt % to about 15 wt % of tin. The abrasive article also includes at least one abrasive particle partially embedded in the matrix layer. The abrasive particle includes carbon. | 08-13-2015 |
| 20150221743 | SEMICONDUCTOR DEVICE WITH GATE STACKS AND METHOD OF MANUFACTURING THE SAME - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate stack. The first gate stack includes a gate dielectric layer, a first work function metal layer and a second work function metal layer directly on the first work function metal layer. The second work function metal layer and the first work function metal layer have the same metal element. The semiconductor device also includes a second gate stack. The second gate stack includes a gate dielectric layer, a barrier layer and a second work function metal layer. The second work function metal layer and the barrier layer do not have the same metal element. A first thickness of the second work function metal layer of the first gate stack is larger than a second thickness of the second work function metal layer of the second gate stack. | 08-06-2015 |
| 20150221737 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD - Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate. | 08-06-2015 |
| 20150221696 | Pixel With Transistor Gate Covering Photodiode - The semiconductor device includes a semiconductor substrate, an isolation feature, a photodiode and a transistor gate. The isolation feature is disposed in the semiconductor substrate. The photodiode is disposed in the semiconductor substrate and adjacent to the isolation feature. The photodiode includes a first pinned photodiode (PPD) with a first dopant type and a second PPD with a second dopant type. The second PPD is embedded in the first PPD, and is different from the first dopant type. The transistor gate is disposed over the photodiode and includes a first portion and a second portion. The first portion with the first dopant type is used for controlling the operation of the semiconductor device. The second portion with the second dopant type is adjacent to the first portion. The second portion covers the photodiode and extends toward the isolation feature. | 08-06-2015 |
| 20150221689 | MECHANISMS FOR FORMING IMAGE SENSOR WITH LATERAL DOPING GRADIENT - Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient. | 08-06-2015 |
| 20150221640 | Semiconductor Device And Method For Manufacturing Thereof - A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein. | 08-06-2015 |
| 20150221555 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein. | 08-06-2015 |
| 20150221515 | METHOD AND APPARATUS FOR COOLING WAFER IN ION IMPLANTATION PROCESS - Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer. | 08-06-2015 |
| 20150214893 | VOLTAGE CONTROLLED OSCILLATOR WITH A LARGE FREQUENCY RANGE AND A LOW GAIN - A circuit includes a voltage controlled oscillator (“VCO”) having a VCO cell. The VCO cell includes a first transistor and a second transistor. The first transistor has a gate terminal coupled to a first node that also is coupled to a low-pass filter from which the gate terminal receives a first control voltage signal. A second terminal of the first transistor is connected to a first voltage source. The second transistor has a gate terminal coupled to a second node that is disposed between a capacitor and a resistor of the low pass filter. The second transistor has a second terminal connected to the first voltage source. The second transistor is larger than the first transistor, and the VCO has an output terminal for providing an output frequency signal. | 07-30-2015 |
| 20150214892 | FINFET VARACTOR - The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor. | 07-30-2015 |
| 20150214170 | SEMICONDUCTOR DEVICE WITH BUMP STOP STRUCTURE - A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided. | 07-30-2015 |
| 20150214035 | PROCESS AND SYSTEM FOR TREATING FLUID - Embodiments of a process for treating a fluid are provided. The process for treating a fluid includes supplying a first fluid to a circulating chamber and introducing a first gas to the first fluid. A portion of the first gas is dissolved in the first fluid and a portion of the first gas is held in a head space portion of the circulating chamber. The process further includes mixing a portion of the first fluid drawn out from the circulating chamber and a portion of the first gas drawn out from the head space portion to form a mixture. The process further includes spraying the mixture back into the circulating chamber by a two-fluid nozzle. In addition, the first gas is further dissolved into the first fluid to form a high conductivity fluid. The process further includes draining the high conductivity fluid from the circulating chamber. | 07-30-2015 |
| 20150214027 | WAFER CLEANING SYSTEM AND METHOD - Embodiments of a wafer cleaning system and method are provided. A brush element is configured to clean a backside of the wafer. The backside has a clear area and an unclear area, and some contaminants are located in the unclear area. A control device performs a first cleaning process to the brush element when the brush element is located at the clear area, and the control device performs a second cleaning process when the brush element is located at the unclear area. The contaminants are cleaned by an enhanced cleaning process. Since the contaminants are cleaned, the backside of the wafer is flatter, and quality of the exposed photoresist on the wafer is improved. | 07-30-2015 |
| 20150211122 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-30-2015 |
| 20150210537 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Embodiments of a semiconductor device structure are provided. The semiconductor device structure includes a cap structure. The cap structure includes: a first bonding layer and a cap substrate, and the first bonding layer is embedded in the cap substrate. The semiconductor device structure also includes a substrate structure. | 07-30-2015 |
| 20150207065 | RRAM CELL INCLUDING V-SHAPED STRUCTURE - Embodiments of a resistive random access memory (RRAM) cell structure are provided. The RRAM cell structure includes a first electrode over a substrate. The RRAM cell structure also includes a resistance variable layer over the first electrode. The resistance variable layer has a first portion in a V-shape. The RRAM cell structure further includes a second electrode over the resistance variable layer. | 07-23-2015 |
| 20150206964 | SEMICONDUCTOR DEVICE STRUCTURE WITH METAL RING ON SILICON-ON-INSULATOR (SOI) SUBSTRATE - In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring. | 07-23-2015 |
| 20150206917 | IMAGE-SENSOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING - Embodiments of an image-sensor device structure and a method of manufacturing thereof are provided. The image-sensor device structure includes a semiconductor substrate and a light-sensing region in the semiconductor substrate. The image-sensor device structure also includes an interconnect structure over the semiconductor substrate, and the interconnect structure includes a transparent dielectric layer over the light-sensing region. The transparent dielectric layer has an optical transmittance ranging from about 90% to about 97%. | 07-23-2015 |
| 20150206915 | IMAGE-SENSOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An image-sensor device includes a first semiconductor substrate. The image-sensor device further includes a second semiconductor substrate under the first semiconductor substrate. The first semiconductor substrate has a first dopant concentration less than a second dopant concentration of the second semiconductor substrate. A ratio of a first resistance of the first semiconductor substrate to a second resistance of the second semiconductor substrate is larger than or equal to about 100. The image-sensor device also includes a diffusion layer positioned between the first semiconductor substrate and the second semiconductor substrate. A ratio of a first thickness of the diffusion layer to a second thickness of the first semiconductor substrate ranges from about 0.1 to about 1. | 07-23-2015 |
| 20150206902 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer. | 07-23-2015 |
| 20150206891 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate. | 07-23-2015 |
| 20150206887 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography. | 07-23-2015 |
| 20150206845 | INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME - Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure. | 07-23-2015 |
| 20150206840 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a dielectric layer on the semiconductor substrate. The semiconductor device structure also includes at least one conductive structure embedded in the dielectric layer. A plurality of crystal grains are composed of the conductive structure, and a ratio of an average grain size of the crystal grains to a width of the conductive structure ranges from about 0.75 to about 40. | 07-23-2015 |
| 20150206792 | METHOD FOR FORMING CONDUCTING VIA AND DAMASCENE STRUCTURE - In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH | 07-23-2015 |
| 20150206791 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench. | 07-23-2015 |
| 20150206753 | SELF-ALIGNED CONTACT AND METHOD OF FORMING THE SAME - Some embodiments of the present disclosure relate to a method to form a source/drain SAC for a transistor. The method comprises forming a pair of gate structures within a first dielectric material on a surface of a substrate, which are isolated from the first dielectric material by an etch stop material. A cap material is formed over the pair of gate structures and the first dielectric material. A pattern of mask material is formed by implanting regions of the cap material with dopants. The implanted regions of the cap material are then removed by a selective etch, which forms the pattern of mask material over each gate structure. The pattern of mask material is configured to shield each gate structure during a subsequent etch step to prevent shorting of the gate structure to the SAC. | 07-23-2015 |
| 20150206741 | APPARATUS AND METHOD FOR IN SITU STEAM GENERATION - Embodiments of an apparatus for in situ steam generation oxidation are provided. The apparatus includes a reactor chamber. The apparatus also includes a radiant source over the chamber. The radiant source includes a plurality of lamps for heating the reactor chamber. The apparatus further includes a lamphead over the radiant source for adjusting the temperature of the radiant source. In addition, the apparatus includes a gas inlet system coupled to the lamphead. The gas inlet system includes a mass flow controller for adjusting the flow rate of cooling gas into the lamphead. The apparatus includes a gas outlet system, on the opposite side of the cooling gas inlet system, coupled to the lamphead. The gas outlet system includes a pressure controller for accelerating the exhaust rate of the cooling gas. | 07-23-2015 |
| 20150206690 | SYSTEM AND METHOD FOR GENERATING IONS IN AN ION SOURCE - Embodiments of a method for generating ions in an ion source are provided. The method for generating ions in an ion source includes introducing a dopant gas and a diluent gas into an ion source arc chamber. The method for generating ions in an ion source further includes generating plasma in the ion source arc chamber based on the dopant gas and the diluent gas. In addition, the dopant gas includes carbon monoxide, and the diluent gas includes xenon and hydrogen | 07-23-2015 |
| 20150206583 | Operating Resistive Memory Cell - A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source. | 07-23-2015 |
| 20150206555 | THREE-DIMENSIONAL WORDLINE SHARING MEMORY - A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines. | 07-23-2015 |
| 20150205267 | TUNABLE DELAY CELLS FOR TIME-TO-DIGITAL CONVERTER` - A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor. | 07-23-2015 |
