STMicroelectronics International N.V Patent applications |
Patent application number | Title | Published |
20160105017 | OVER-VOLTAGE PROTECTION CIRCUIT FOR A DRIVE TRANSISTOR - A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal. | 04-14-2016 |
20160103458 | CIRCUIT FOR REGULATING STARTUP AND OPERATION VOLTAGE OF AN ELECTRONIC DEVICE - An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals. | 04-14-2016 |
20160094217 | DRIVER CIRCUIT INCLUDING DRIVER TRANSISTORS WITH CONTROLLED BODY BIASING - A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad. | 03-31-2016 |
20160080013 | ADAPTIVE ISO-GAIN PRE-DISTORTION FOR AN RF POWER AMPLIFIER OPERATING IN ENVELOPE TRACKING - The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage is adaptively pre-distorted to achieve a constant ISO-Gain (and phase) in the RF PA. In particular, a nonlinear function is interpolated from a finite number gain values calculated from the feedback and transmission signals. This nonlinear function is then used to pre-distort the transmission signal envelope, resulting in a constant gain at the RF PA over a wide range of supply voltage values. Since the gains are calculated from a feedback signal, the pre-distortion may be recalculated at event triggers, such as an RF frequency change. | 03-17-2016 |
20160078815 | METHOD FOR DETERMINING A REFRESH FREQUENCY FOR A MATRIX OF OLED ACTIVE PIXELS AND CORRESPONDING DEVICE - A device includes an OLED pixel and a control circuit controlled at a refresh rate thereof. The device includes first and second dummy control circuits having similar operating characteristics to the control circuit. A controller and logic circuit switch on the first and second dummy control circuits and apply an input voltage so the first and second dummy control circuits output first and second output voltages. At a first time, the controller and logic circuit switch off the second dummy control circuit so a leakage current flows through the second dummy control circuit to ground, causing the second output voltage to reduce. Comparison circuitry determines a second time at which, due to the reduction of the second output voltage, a difference between the first and second output voltages is greater than a threshold. Determination circuitry determines the refresh frequency based upon elapsed time between the first and second times. | 03-17-2016 |
20160056921 | LOW COMPLEXITY MAXIMUM-LIKELIHOOD-BASED METHOD FOR ESTIMATING EMITTED SYMBOLS IN A SM-MIMO RECEIVER - A receiver estimates a vector of emitted symbols over a MIMO transmission channel which is emitted by emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbols as the vector of emitted symbols among said subset which minimizes said metric. | 02-25-2016 |
20160056830 | ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle. | 02-25-2016 |
20160049189 | METHOD OF MINIMIZING THE OPERATING VOLTAGE OF AN SRAM CELL - An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively. | 02-18-2016 |
20150371588 | DEVICE COMPRISING A MATRIX OF ACTIVE OLED PIXELS WITH BRIGHTNESS ADJUSTMENT, AND CORRESPONDING METHOD - A device includes a matrix of active pixels. Each active pixel includes an OLED and a control circuit configured to refresh the active pixel and including at least one transistor having a first conduction terminal coupled to a supply line and a second conduction terminal coupled to the OLED. Supply circuitry is configured to apply a supply voltage to the supply line of each active pixel during the refreshing of the active pixel and for a time period less than a duration of the refreshing of the active pixel. | 12-24-2015 |
20150366026 | INTEGRATED DEVICE COMPRISING A MATRIX OF OLED ACTIVE PIXELS WITH IMPROVED DYNAMIC RANGE - An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another. | 12-17-2015 |
20150365693 | VIDEO ENCODERS/DECODERS AND VIDEO ENCODING/DECODING METHODS FOR VIDEO SURVEILLANCE APPLICATIONS - Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer. | 12-17-2015 |
20150341017 | AUTOMATIC POWER SWITCHING AND POWER HARVESTING IN THIN OXIDE OPEN DRAIN TRANSMITTER CIRCUITS, SYSTEMS, AND METHODS - A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit. | 11-26-2015 |
20150331985 | Area Optimized Driver Layout - A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area. | 11-19-2015 |
20150330778 | TRACKING DYNAMIC ON-STAGE OBJECTS - Methods and systems for dynamic tracking of on-stage objects using microelectromechanical systems (MEMS) presented herein do not require illumination to track a randomly moving object and are easily configurable for various stage sizes and for stages movable relative to the ground. In some instances, a tracking method includes determining an initial state of an MEMS motion tracker carried on a dynamic object, such as a performer. Acceleration and orientation information gathered by the motion tracker is monitored. A change of state in response to the monitored acceleration and orientation information is then determined. An instant state is calculated using the change of state and the initial state. Actuation signals based on the calculated instant state are generated for actuating a gimbal. The gimbal faces a device supported thereby toward the dynamic object. | 11-19-2015 |
20150323945 | STAND-ALONE DC POWER SYSTEM FOR NETWORKS NOT CONNECTED TO THE GRID - A stand-alone DC power network is provided with a DC to DC power converter only, and does not have a converter that will convert AC to DC. In addition, each of the different terminals that provides the DC voltage at different levels will be ranked according to priority as to which ones are the most important to supply the full voltage to, and which ones are of secondary importance in the event there is insufficient power in the system to provide full voltage at the specified current for the different loads. A processor monitors the voltage and current at each of the terminals, and in the event a current is attempted to be drawn from the system which would cause a first priority terminal to be reduced in voltage, the processor will instead reduce the power provided to the second priority terminal and ensure that the first priority terminal does not have a significant reduction in the specified voltage or the amount of current supplied to that terminal at the specified voltage. | 11-12-2015 |
20150323782 | SCANNING MICROMIRROR WITH IMPROVED PERFORMANCE AND RELATED ELECTRONIC DEVICE - A micromechanical mirror includes a mobile mass carrying a mirror element and provided in a body including semiconductor material. A driving structure is coupled to the mobile mass to cause a scanning movement thereof. The driving structure is configured to generate a combination of a two or more sinusoidal resonant modes in the micromechanical mirror at respective resonant frequencies. This combination approximates a scanning pattern of the mobile mass defined by a linear function which may, in particular, be a triangular shaped function. | 11-12-2015 |
20150323594 | MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING - The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer. | 11-12-2015 |
20150323593 | SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS - An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output. | 11-12-2015 |
20150317225 | REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS - Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array. | 11-05-2015 |
20150302917 | SRAM Cell and Cell Layout Method - Embodiments of the present disclosure include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts. | 10-22-2015 |
20150280898 | OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER - A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. | 10-01-2015 |
20150280728 | ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle. | 10-01-2015 |
20150280716 | BUFFER CIRCUIT WITH REDUCED STATIC LEAKAGE THROUGH CONTROLLED BODY BIASING IN FDSOI TECHNOLOGY - A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit. | 10-01-2015 |
20150280714 | VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR WIDE SUPPLY VOLTAGE APPLICATIONS - A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage. | 10-01-2015 |
20150276885 | Method of Computing State of Charge and Battery State of Charge Monitor - Disclosed herein are a method of computing an estimated SOC and a battery state of charge (SOC) monitor. An embodiment method for computing an estimated SOC includes periodically measuring a present battery current and a present battery voltage. A hysteresis compensation value is then computed based on a previous SOC, the present battery current, and the present battery voltage when a change in battery current exceeds a threshold. The estimated SOC is then determined based on the hysteresis compensation value and a baseline SOC determined based on the present battery voltage and the present battery current. | 10-01-2015 |
20150270947 | REFERENCELESS CLOCK AND DATA RECOVERY CIRCUIT - A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits. | 09-24-2015 |
20150270836 | CLOCK GLITCH AND LOSS DETECTION CIRCUIT - A conversion circuit measures individual period lengths for periods of a clock signal. Two of the measured period lengths are selected and compared. The comparison operates to compare a first period length against a threshold set as a function of the second period length. The result of the comparison is indicative of the presence of a clock error. If the threshold is set less than the second period length, the comparison functions to detect a clock glitch. If the threshold is set more than the second period, the comparison functions to detect a loss of clock. The result of the comparison may be used to control further handling of the clock signal by, for example, blocking logic state changes in the clock signal for the length of one period in response to the detection of the clock error. | 09-24-2015 |
20150270776 | Power Management System and Method of Use Thereof - One embodiment of a power management system includes a reservoir configured to collect energy. The system also includes a voltage regulator coupled to the reservoir via an input terminal and configured to convert the energy to an output voltage via an output terminal when enabled. A threshold detector is coupled to the reservoir and is configured to sense the energy and enable the voltage regulator when the energy exceeds a threshold. The system further includes a feedback circuit coupled between the output terminal and the threshold detector, and configured to feedback the output voltage to the threshold detector to compensate for a voltage drop across the threshold detector due to an output current drawn by the load. | 09-24-2015 |
20150270393 | INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS - Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance. | 09-24-2015 |
20150268133 | SAFE SCHEDULER FOR FINITE STATE DETERMINISTIC APPLICATION - A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison. | 09-24-2015 |
20150263726 | NOVEL METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY - An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter. | 09-17-2015 |
20150263707 | SCHMITT TRIGGER IN FDSOI TECHNOLOGY - A Schmitt Trigger is implemented in FDSOI technology. The Schmitt Trigger includes a first inverting stage having an NMOS and PMOS transistor having their drains tied together. The NMOS and PMOS transistor each have a first gate coupled to the input voltage and a back gate coupled to the output of the Schmitt Trigger. | 09-17-2015 |
20150229654 | SECURED TRANSACTIONS IN INTERNET OF THINGS EMBEDDED SYSTEMS NETWORKS - A secure network enabled device has a distinct security module and lacks a human user input interface. The security module is formed in an integrated circuit. The security module is initialized. Data is electronically communicated to and from the secure network enabled device via at least one transceiver. The security module is configured to test the integrity of a subset of the data communicated to the secure network enabled device, and the security module is configured to test the integrity of a transaction protocol, which governs the stream of data bits of the data communicated to the secure network enabled device. | 08-13-2015 |
20150212945 | CACHE MEMORY SYSTEM WITH SIMULTANEOUS READ-WRITE IN SINGLE CYCLE - A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read. | 07-30-2015 |
20150200632 | HYSTERESIS COMPARATOR CIRCUIT HAVING DIFFERENTIAL INPUT TRANSISTORS WITH SWITCHED BULK BIAS VOLTAGES - A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages. | 07-16-2015 |
20150198665 | SYSTEM AND METHOD FOR REDUCING VOLTAGE DROP DURING AUTOMATIC TESTING OF INTEGRATED CIRCUITS - A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time. | 07-16-2015 |
20150198663 | ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING - A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip. | 07-16-2015 |
20150179282 | AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING - An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. | 06-25-2015 |
20150177605 | SAFETY FEATURE FOR PROJECTION SUBSYSTEM USING LASER TECHNOLOGY - A projection subsystem includes a projector for projecting an image on a projection surface and a safety feature for tuning the projector when presence of a human is detected in front of the projection surface. This safety feature includes:—an apparatus for computing a depth view corresponding to at least a portion of the projection surface,—a camera for acquiring a captured image,—a computing circuit for detecting an object between the projector and the projection surface from this depth view and determining that the object is a human from the captured image, and a control circuit for tuning the projector accordingly. | 06-25-2015 |
20150145608 | HIGH FREQUENCY LOW-GAIN NOISE RING-TYPE VCO OSCILLATOR LEADING TO A LOW-NOISE/AREA PLL - A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle. | 05-28-2015 |
20150143072 | METHOD IN A MEMORY MANAGEMENT UNIT FOR MANAGING ADDRESS TRANSLATIONS IN TWO STAGES - A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry. | 05-21-2015 |
20150137862 | SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS - A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses. | 05-21-2015 |
20150137776 | DC-DC Converter with Enhanced Automatic Switching Between CCM and DCM Operating Modes - A DC-DC converter transitions between continuous conduction mode (CCM) and discontinuous conduction mode (DCM) without causing any overshoot or undershoot deviation output voltage. The DC-DC converter operates in a PWM mode in CCM. During DCM, it skips PWM pulses when a sustained negative current is detected in an output inductor. The current sensing is achieved by sampling and integrating a voltage, the sign of which is inverse to current direction. The sample and hold and integrator circuits are small, simple, and scale to high frequencies. The pulse skipping circuit automatically adjusts the duty cycle of power pulses to force a zero inductor current at the end of each pulse. | 05-21-2015 |
20150130531 | SYSTEM AND METHOD FOR REMOTE TEMPERATURE SENSING WITH ROUTING RESISTANCE COMPENSATION - An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group. | 05-14-2015 |
20150130528 | WIDE RANGE CORE SUPPLY COMPATIBLE LEVEL SHIFTER CIRCUIT - A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the V | 05-14-2015 |
20150129967 | DUAL GATE FD-SOI TRANSISTOR - Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module. | 05-14-2015 |
20150127998 | System and Method for Improving Memory Performance and Identifying Weak Bits - According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge. | 05-07-2015 |
20150126141 | Adaptive ISO-Gain Pre-Distortion for an RF Power Amplifier Operating in Envelope Tracking - The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage V | 05-07-2015 |
20150123721 | System and Method for Gaussian Random Noise Generation - In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal. | 05-07-2015 |
20150110123 | LIMITATION OF SERIAL LINK INTERFERENCE - A plurality of frames of data are transmitted over a serial interface in a manner that limits interference on the interface. This involves generating a pseudo-random number and asserting a read control signal at a moment in time, wherein a timing of the moment in time is influenced by the pseudo-random number. In response to the asserted read control signal, a frame of data is read from a data buffer. The read frame of data is then transmitted over the serial interface. A number of alternative embodiments are possible, such as embodiments in which buffer read operations are triggered based on the buffer fill level, and other embodiments in which buffer read operations are triggered by a timer. By using the pseudo-random number to influence the buffer read operations, timing coherency between the reading of frames is made low, thereby limiting interference. | 04-23-2015 |
20150109408 | SYSTEM AND METHOD FOR CAPTURING AND RENDERING A LANDSCAPE IMAGE OR VIDEO - The present disclosure provides a system and method for capturing and rendering a landscape image such that the field of view of the captured image remains consistent across any orientation maintained by the camera device at the time the image is captured. The retained field of view corresponds to the maximum landscape field of view achievable from the aspect ratio of the image when captured by the device, when the device is positioned in portrait orientation. Thus, the field of view of a landscape image captured when the camera device is positioned in landscape orientation is identical to the field of view of a landscape image captured when the device is positioned in portrait orientation. Furthermore, the system and method provide for a consistent field of view at the time of playback regardless of whether the captured image is displayed on a device having a portrait or landscape display orientation. | 04-23-2015 |
20150108956 | SWITCHED MODE POWER SUPPLY PEAK-EFFICIENCY DETECTION - A peak efficiency detection system may include a switched power supply (SPS) module providing an output supply signal. The SPS module may have an internal node, and a plurality of SPS circuits configured to generate the output supply signal on the internal node. A dead type module may generate control signals. A central node external to the SPS module may deliver the output supply signal to a load module. A power stage size control module may generate control signals for controlling the SPS module. A peak-efficiency detection (PED) module may receive the output supply signal from the central node, the control signals from the SPS module, and the control signals from the power stage size control module. The PED module may generate a signal representative of an efficiency of the SPS module. | 04-23-2015 |
20150098267 | Method and Circuit to Enable Wide Supply Voltage Difference in Multi-Supply Memory - A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels. | 04-09-2015 |
20150084609 | FEEDBACK NETWORK FOR LOW-DROP-OUT GENERATOR - A circuit may include a differential amplifier and a feedback network. The feedback network may have a chain of resistance sets coupled in series, with a first end terminal coupled to an output terminal of the differential amplifier and a second end terminal coupled to a power reference terminal of the differential amplifier. Respective nodes may be coupled between successive ones of the resistance sets. A feedback terminal may be coupled to an inverting input terminal of the differential amplifier. A controller may control a set of switches to electrically couple a given node to the feedback terminal. A first resistance set of the chain adjacent the first end terminal may be two resistance subsets coupled in series, with an intermediate node coupled therebetween. A programmable current generator may have a current output coupled to the intermediate node and may produce a controlled current flowing at the current output terminal. | 03-26-2015 |
20150082060 | POWER CONSUMPTION MANAGEMENT SYSTEM AND METHOD - A power consumption management system for a central processing unit may include a power consumption estimation block and an activity control block. The power consumption estimation block may be configured to estimate power consumption of the central processing unit based on information related to a status of the central processing unit. The activity control block may be configured to use the estimated power consumption to determine a control to be applied to the central processing unit for regulating a rate of change in power consumption of the central processing unit. | 03-19-2015 |
20150081983 | PRE-FETCH IN A MULTI-STAGE MEMORY MANAGEMENT SYSTEM - A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request. | 03-19-2015 |
20150078577 | ACCESSORY PLUG DETECTION - The presence and/or state of an accessory having a connector of a first type (e.g. male connector) adapted to be plug into a connector of a second type (e.g. female connector) of an electronic device is detected based on an analysis of an electrical line coupled to the female connector of the device, wherein the electrical line analysis is started only when it is determined that the connector of the accessory is completely inserted into the connector of the device. | 03-19-2015 |
20150078069 | INTEGRATED CMOS CIRCUIT HAVING FIRST AND SECOND CIRCUIT PARTS - An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus. | 03-19-2015 |
20150077165 | METHOD AND APPARATUS FOR AVOIDING SPURS IN CHIP - A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift. | 03-19-2015 |
20150070090 | SUSPEND MODE IN CHARGE PUMP - A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load. | 03-12-2015 |
20150058578 | ENHANCED PRE-FETCH IN A MEMORY MANAGEMENT SYSTEM - A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit. | 02-26-2015 |
20150055805 | MULTIPLE LEVEL CHARGE PUMP GENERATING VOLTAGES WITH DISTINCT LEVELS AND ASSOCIATED METHODS - A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit. | 02-26-2015 |
20150043681 | DATA SAMPLER CIRCUIT - A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal. | 02-12-2015 |
20150042301 | VOLTAGE REGULATORS - An embodiment of an arrangement includes a voltage regulator configured to provide an output voltage, said voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, said selection signal being used to control which of said regulator reference voltages said voltage regulator receives. | 02-12-2015 |
20150030107 | LOW COMPLEXITY MAXIMUM-LIKELIHOOD-BASED METHOD FOR ESTIMATING EMITTED SYMBOLS IN A SM-MIMO RECEIVER - A receiver estimates a vector of emitted symbols over a MIMO transmission channel which are emitted by a emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbol as the vector of emitted symbols among said subset which minimizes said metric. | 01-29-2015 |
20150029795 | SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY - A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell. | 01-29-2015 |
20150025823 | TEMPERATURE-COMPENSATED STATE OF CHARGE ESTIMATION FOR RECHARGEABLE BATTERIES - The remaining state of charge of a rechargeable battery is calculated by: measuring the instantaneous voltage, impedance and temperature of the battery, and then inputting the measured voltage, impedance and temperature values into an equation, wherein the equation yields a state of charge value that is a function of the said measured voltage, impedance and temperature values. | 01-22-2015 |
20150025822 | BATTERY DC IMPEDANCE MEASUREMENT - The state of charge of a rechargeable battery is determined by calculating the DC impedance of the battery. The impedance is calculated by: performing a two different constant current discharges of the battery at a first and second C-rates, respectively; measuring the voltage and current during the interval of each constant current discharge and calculating the amount of charge extracted from the battery up to a point where the battery voltage drops to a threshold value; calculating the state of charge of the battery; and calculating the DC impedance of the battery as a function of the difference between the battery voltages and discharge currents for the two different discharges. | 01-22-2015 |
20150024683 | SYSTEM AND METHOD FOR POLLING NFC-A DEVICES ALONGSIDE RF BARCODE DEVICES - A NFC reader is connected for communication to NFC devices such as an NFC-A device and an RF barcode device. The reader detects and logs the active and sleep intervals of the RF barcode device in response to receipt of periodically received UID communications. The transmission and reception of data to and from each NFC-A device is then synchronized to occurs only when the RF barcode device is in a sleep interval between UID communications. | 01-22-2015 |
20150024682 | ACTIVE PASSIVE NEAR FIELD COMMUNICATION ANTI-COLLISION METHOD, INITIATOR AND TAG - In near field communication between an active initiator and a plurality of passive listening devices, the initiator device obtains a unique identity code from each listening device using an initialization process. The initiator transmits a poll request signal including a sequence of coupled data including an identification vector and an allocation vector. Each listening device stores an embedded introduction vector. In response to receive of the poll request signal, the listening device compares each received introduction vector with its stored embedded introduction vector. If a match is found, the listening device calculates a time slot for transmission of its poll response signal based on the coupled allocation vector with the matched introduction vector. The time slot calculated will not overlap with any other time slot so that bit level collisions in the poll response signals will be avoided. | 01-22-2015 |
20150011161 | NEAR FIELD COMMUNICATION ENABLED DEVICE WITH IMPROVED ELECTROMAGNETIC COMPATIBILITY AND A METHOD OF LOAD MODULATING IN NEAR FIELD COMMUNICATION - A near field communication (NFC) initiator communicates with a target device. The carrier is modulated to transmit a digital signal. During time slots allocated for target communication, the field is load modulated by the target. The target load modulator is driven by a digital modulator to vary voltage at antenna terminals so that peak amplitude of the carrier varies for specified periods between high and low values. To alleviate interference in the target device caused by the generation of aliases during transition, the load modulator sequentially applies a range of resistances to vary the amplitude (voltage) during transition according to a specific waveform determined by the infinite impulse response of a low pass filter tuned to the cut of frequency and sampling frequency determined according to the coexistence and cohabitation specifications of a chip in which the NFC functionality is embedded. | 01-08-2015 |
20140375358 | HIGH VOLTAGE TOLERANT INPUT BUFFER - A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain. | 12-25-2014 |
20140375332 | METHOD OF VALLEY INDUCTANCE CURRENT POLARITY DETECTION IN A PULSE WIDTH MODULATED CIRCUIT WITH AN INDUCTIVE CHARGE - A valley inductance current polarity change in a pulse width modulated circuit charged with an inductive charge is detected by comparing respective times that a first output of the circuit charged with an inductive charge and a second output of a pulse width modulated reference circuit with no inductive charge reach an output level. Responsive thereto, control over operation of the pulse width modulated circuit charged with an inductive charge is made with respect to switching to a pulse skipping mode of operation or keeping the pulse width modulation mode of operation. | 12-25-2014 |
20140333460 | MEMORYLESS SLIDING WINDOW HISTOGRAM BASED BIST - A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source. | 11-13-2014 |
20140300386 | VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR HIGH SPEED APPLICATIONS - A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters. | 10-09-2014 |
20140293723 | MEMORY WITH AN ASSIST DETERMINATION CONTROLLER AND ASSOCIATED METHODS - A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value. | 10-02-2014 |
20140292402 | SYNCLESS UNIT INTERVAL VARIATION TOLERANT PWM RECEIVER CIRCUIT, SYSTEM AND METHOD - A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal. | 10-02-2014 |
20140292385 | INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, AND RELATED METHODS - An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals. | 10-02-2014 |
20140286116 | NOISE TOLERANT SENSE CIRCUIT - A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation. | 09-25-2014 |
20140281101 | INCOMING BUS TRAFFIC STORAGE SYSTEM - In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM. | 09-18-2014 |
20140269137 | CANARY BASED SRAM ADAPTIVE VOLTAGE SCALING (AVS) ARCHITECTURE AND CANARY CELLS FOR THE SAME - A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank. | 09-18-2014 |
20140253213 | LEVEL SHIFTING CIRCUIT WITH ADAPTIVE FEEDBACK - An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners. | 09-11-2014 |
20140247035 | NOISE CANCELING CURRENT MIRROR CIRCUIT FOR IMPROVED PSR - A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability. | 09-04-2014 |
20140241539 | NOISE REMOVAL SYSTEM - A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal. | 08-28-2014 |
20140241416 | ADAPTIVE FILTER FOR VIDEO SIGNAL PROCESSING FOR DECODER THAT SELECTS RATE OF SWITCHING BETWEEN 2D AND 3D FILTERS FOR SEPARATION OF CHROMA AND LUMA SIGNALS - An adaptive temporal motion filter for a video decoder system operates in an infinite impulse response (IIR), a max or a bypass mode. The adaptive temporal motion filter includes an adaptive time constant control module and a filter gain module. A gain factor of the filter gain module is varied by the adaptive time constant control module for every pixel in a current composite video signal. The adaptive time constant control module selects a variable gain for the filter gain module based on the motion magnitude, motion polarity and chroma luma status of the pixel. | 08-28-2014 |
20140241102 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 08-28-2014 |
20140233321 | WORD-LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 08-21-2014 |
20140204656 | LOW VOLTAGE DUAL SUPPLY MEMORY CELL WITH TWO WORD LINES AND ACTIVATION CIRCUITRY - A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage. | 07-24-2014 |
20140189175 | GENERIC BUS DE-MULTIPLEXER/PORT EXPANDER WITH INHERENT BUS SIGNALS AS SELECTORS - A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal. | 07-03-2014 |
20140167812 | System and Method for Critical Path Replication - Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode. | 06-19-2014 |
20140166763 | SIM CARD ADAPTER - A SIM card adapter assembly is to adapt a SIM card to a SIM slot. The adapter assembly includes a SIM card plastic support including a first portion of a predetermined thickness. The SIM card is removably attached and a second portion has an increased thickness wherein at least one adapter is removably attached. | 06-19-2014 |
20140161359 | METHOD FOR DETECTING A STRAIGHT LINE IN A DIGITAL IMAGE - An embodiment is a computer-implemented method for detecting a straight line in a digital image comprising a plurality of pixels comprising the steps: detecting an edge in the digital image, generating a first straight line which passes through a first pixel of the detected edge, generating a second straight line which passes through a second pixel of the detected edge, which is different from the first pixel, determining at least two intersections with a boundary of the digital image for each generated straight line, determining a set of two parameter values for each generated straight line based on the respective determined at least two intersections, wherein the set of two parameter values uniquely determines the respective generated straight line, and detecting the straight line in the digital image based on the determined sets of two parameter values. | 06-12-2014 |
20140153074 | MOEMS APPARATUS AND A METHOD FOR MANUFACTURING SAME - An apparatus is formed from a double active layer silicon on insulator (DSOI) substrate that includes first and second active layers separated by an insulating layer. An electrostatic comb drive is formed from the substrate to include a first comb formed from the first active layer and a second comb formed from the second active layer. The comb drive may be used to impart a tilting motion to a micro-mirror. The method of manufacturing provides comb teeth exhibiting an aspect ratio greater than 1:20, with an offset distance between comb teeth of the first and second combs that is less than about 6 μm. | 06-05-2014 |
20140132434 | LOW LATENCY FILTER - In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples. | 05-15-2014 |
20140132308 | FAST LOCK ACQUISITION AND DETECTION CIRCUIT FOR PHASE-LOCKED LOOPS - A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock. | 05-15-2014 |
20140125503 | QUADRATURE SIGNAL DECODING USING A DRIVER - A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator. | 05-08-2014 |
20140112081 | DATA-DEPENDENT PULLUP TRANSISTOR SUPPLY AND BODY BIAS VOLTAGE APPLICATION FOR A STATIC RANDOM ACCESS MEMORY (SRAM) CELL - A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node. | 04-24-2014 |
20140111532 | CONTENT ADAPTIVE IMAGE RESTORATION, SCALING AND ENHANCEMENT FOR HIGH DEFINITION DISPLAY - An image processor includes generates a content adaptive kernel from an image block with noise of a luminance component signal with a low resolution. The content adaptive kernel is convolved with the luminance component signal. A noise signal and an extracted texture which excludes noise are generated. The luminance component signal is filtered as function of the noise signal to generate an enhanced luminance component signal. Horizontal and vertical scaling is performed on the enhanced luminance component signal, the extracted texture, and the luminance component signal, with the luminance component signal adaptively scaled as a function of the extracted texture. The horizontally and vertically scaled enhanced luminance component signal, extracted texture and luminance component signal are then combined to generate an output luminance component signal with a high resolution. | 04-24-2014 |
20140111258 | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability - A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area. | 04-24-2014 |
20140111248 | LOW SUPPLY VOLTAGE ANALOG DISCONNECTION ENVELOPE DETECTOR - An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition. When compared to conventional disconnect detection circuitry, the disclosed circuit utilizes a relatively low supply voltage to detect high differential voltage disconnect conditions with improved accuracy. | 04-24-2014 |
20140103900 | LOW POWER REFERENCE GENERATOR CIRCUIT - A PTAT circuit includes a first, second, third, and fourth transistors plus a resistor. The first and second transistors have control terminals coupled to each other. The third and fourth transistors have control terminals coupled to each other. The third transistor sources a first current to the first transistor and the fourth transistor sources a second current to the second transistor. The resistor is coupled at a node to the second transistor. A current source circuit sources additional current into the node that is derived from the first and second currents. In one implementation, the additional current is a scaled mirror of the second current. In another implementation, the additional current is a scaled mirror of the sum of the first and second currents. An output current is obtained by mirroring one of the first-third currents. A band-gap output voltage is obtained by applying the additional current across a resistance. | 04-17-2014 |
20140070843 | IMPEDANCE CALIBRATION CIRCUIT AND METHOD - An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled. | 03-13-2014 |
20140062460 | POWER MEASUREMENT CIRCUIT - A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device. | 03-06-2014 |
20140055438 | IMAGE PROCESSING ARRANGEMENT ILLUMINATING REGIONS OF AN IMAGE BASED ON MOTION - An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic. | 02-27-2014 |
20140047285 | MEMORY MANAGER - An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold. | 02-13-2014 |
20140035672 | LEVEL SHIFTING CIRCUIT WITH ADAPTIVE FEEDBACK - An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners. | 02-06-2014 |
20140035644 | ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING - Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput. | 02-06-2014 |
20140025869 | METHOD AND SYSTEM FOR IMPROVING A CONTROL OF A LIMIT ON WRITING CYCLES OF AN IC CARD - The present invention relates to a method and system for controlling a number of writing cycles supported by a cell or portion ( | 01-23-2014 |
20140009430 | COMBINING TOUCH SCREEN AND OTHER SENSING DETECTIONS FOR USER INTERFACE CONTROL - A touch sensitive display includes a capacitive touch sensor configured to output capacitance values. A motion sensor makes a motion detection and generates a motion signal including a motion value indicative of sensed motion detection. A touch detection circuit is coupled to receive the capacitance values and motion values. The touch detection circuit processes the capacitance values to make a hovering detection and a touching detection with respect to the display. The touch detection circuit further generates an output signal including the motion value correlated in time with each of the hovering detection and touching detection. The output signal may be processed as a user interface control signal. The output signal may also be processed to determine an impulsive strength of the touching detection as a function of an elapsed time between hover and touch and the measured motion values. | 01-09-2014 |
20140003121 | COMPLEMENTARY READ-ONLY MEMORY (ROM) CELL AND METHOD FOR MANUFACTURING THE SAME | 01-02-2014 |
20130343137 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 12-26-2013 |
20130332785 | TESTING OF NON STUCK-AT FAULTS IN MEMORY - A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. | 12-12-2013 |
20130332766 | METHOD AND SYSTEM FOR CALCULATING A CLOCK FREQUENCY OF A CLOCK SIGNAL FOR AN IC CARD - A clock frequency of a clock signal is calculated, with the clock signal being received by an IC card from a terminal or an internal clock within the IC card. A first time-stamp is received from the terminal, and a first value of the timer is set. The timer of the IC card is started when the first time-stamp is received. A second time-stamp is received, and a second value of the timer is read when the second time-stamp is received. The frequency is calculated by comparing a difference between the second and the first timer values, and a difference between the second and the first time stamps. | 12-12-2013 |
20130330013 | PARALLELIZATION OF VARIABLE LENGTH DECODING - Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel. | 12-12-2013 |
20130328150 | ADJUSTABLE AVALANCHE DIODE IN AN INTEGRATED CIRCUIT - An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm. | 12-12-2013 |
20130290617 | METHOD AND SYSTEM FOR CONTROLLING LOSS OF RELIABILITY OF NON-VOLATILE MEMORY - A method for controlling a loss of reliability of a non-volatile memory (NVM) included in an integrated circuit card (ICC) may include determining whether the NVM is reliable at the operating system (OS) side of the ICC, and generating an event associated with the reliability of the NVM at the OS side for an application of the ICC, if the NVM is determined to be unreliable. | 10-31-2013 |
20130287098 | SYSTEM AND METHOD FOR TRANSCODING DATA FROM ONE VIDEO STANDARD TO ANOTHER VIDEO STANDARD - A system and method transcodes an input video bit stream having a first encoding profile into an output video bit stream having a second encoding profile. The system includes a first module ( | 10-31-2013 |
20130285708 | STRESS REDUCED CASCODED CMOS OUTPUT DRIVER CIRCUIT - An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors. | 10-31-2013 |
20130169696 | DISPLAY PANEL AND DISPLAY PANEL SYSTEM - A display panel comprises an array of light elements arranged in n rows by m columns. At least one driver is configured to drive one of said columns and rows, wherein the or each driver is configured to drive each of said columns or said rows. A plurality of the display panels may be used together to form a display panel system. | 07-04-2013 |
20130169331 | APPARATUS - An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon. | 07-04-2013 |
20130169311 | ADAPTIVE BUFFER - An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. | 07-04-2013 |
20130159802 | TESTING OF MULTI-CLOCK DOMAINS - A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains. | 06-20-2013 |
20130127537 | OUTPUT COMMON MODE VOLTAGE STABILIZER OVER LARGE COMMON MODE INPUT RANGE IN A HIGH SPEED DIFFERENTIAL AMPLIFIER - A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage. | 05-23-2013 |
20130110898 | APPARATUS FOR SIGNAL PROCESSING | 05-02-2013 |
20130088272 | LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF - The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated. | 04-11-2013 |
20130083590 | SENSE AMPLIFIER USING REFERENCE SIGNAL THROUGH STANDARD MOS AND DRAM CAPACITOR - A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor. | 04-04-2013 |
20130044774 | CONTROLLING LASER POWER - An intensity of radiation emitted from at least two laser diodes of a projecting apparatus is optimized by providing an offset distance between at least two focal points of the at least two laser diodes and providing a maximum value for radiation intensity emitted by each of the laser diodes, irrespective of simultaneous transmission by one of the laser diodes with another of the laser diodes. The intensity of the radiation emitted from each of the at least two laser diodes is adjusted such that an aggregated value of the radiation intensity emitted by all of the laser diodes within a predefined period of time may exceed a threshold value allowed for the maximum permissible exposure to radiation. | 02-21-2013 |
20120280756 | MATRIX STRUCTURE OSCILLATOR - An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance | 11-08-2012 |