SILICONWARE PRECISION INDUSTRIES CO., LTD. Patent applications |
Patent application number | Title | Published |
20160071780 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated. | 03-10-2016 |
20160005695 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit. | 01-07-2016 |
20150263421 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure provided on the substrate, wherein the antenna structure has at least a supporting portion and an extending portion supported by the supporting portion over the substrate and surrounding the electronic element; and a shielding structure provided on the substrate and overlapping with the antenna structure, thereby saving the surface area of the substrate so as to meet the miniaturization requirement of the electronic package. | 09-17-2015 |
20150243574 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring. | 08-27-2015 |
20150206814 | LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield. | 07-23-2015 |
20150188510 | CIRCUIT STRUCTURE - A circuit structure is provided, which includes: a first circuit portion having at least a capacitor; a first dielectric portion combined with the first circuit portion; a second circuit portion electrically connected to the first circuit portion and having at least an inductor; and a second dielectric portion combined with the second circuit portion, wherein the first dielectric portion has a greater dielectric constant than the second dielectric portion, thereby increasing the capacitance value and density and causing the inductor to have a high enough Q value. | 07-02-2015 |
20150187741 | PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween. | 07-02-2015 |
20150187722 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture. | 07-02-2015 |
20150179598 | FLIP-CHIP PACKAGING STRUCTURE - A flip-chip packaging structure is provided, which includes: a packaging substrate having a substrate body and a circuit layer formed on the substrate body, wherein the circuit layer has a plurality of conductive pads embedded in the substrate body and exposed from a surface of the substrate body; and a chip disposed on and electrically connected to the packaging substrate through a plurality of conductive elements, wherein the conductive elements and the exposed portions of the conductive pads have a width ratio in a range of 0.7 to 1.3, thereby improving the product yield and reliability. | 06-25-2015 |
20150179597 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a first electronic element; a plurality of conductive elements formed on the first electronic element; a second electronic element having a plurality of conductive bumps and disposed on the first electronic element through the conductive bumps, wherein the conductive bumps are correspondingly electrically connected to the conductive elements; and an underfill formed between the second electronic element and the first electronic element for encapsulating the conductive bumps and the conductive elements, wherein the underfill contains a plurality of conductive particles having a particle size between 0.1 and 1 um, a plurality of insulating particles having a particle size between 1 and 10 um and a polymer. The invention overcomes the conventional drawback of poor electrical connection between the second electronic element and the first electronic element through the conductive particles so as to enhance the electrical performance of the semiconductor package. | 06-25-2015 |
20150162661 | ELECTRONIC COMPONENT - An electronic component is provided, which includes a substrate having opposite first and second surfaces and an antenna structure combined with the substrate. The antenna structure has at least a first extending portion disposed on the first surface of the substrate, at least a second extending portion disposed on the second surface of the substrate, and a plurality of connecting portions disposed in the substrate for electrically connecting the first extending portion and the second extending portion. Any adjacent ones of the connecting portions are connected through one of the first extending portion and the second extending portion. As such, the antenna structure becomes three-dimensional. The present invention does not need to provide an additional region on the substrate for disposing the antenna structure, thereby reducing the width of the substrate so as to meet the miniaturization requirement of the electronic component. | 06-11-2015 |
20150162301 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is provided, which includes the steps of: providing a carrier having at least a semiconductor chip disposed thereon, the semiconductor chip having a first surface attached to the carrier, and an opposite second surface having a plurality of first conductive elements thereon; disposing an interposer on the first conductive elements, wherein the interposer has opposite third and fourth surfaces, the interposer is disposed on the first conductive elements via the third surface, and a plurality of conductive posts are embedded in the interposer and electrically connected to the third surface; forming an encapsulant on the carrier for encapsulating the semiconductor chip and the interposer; removing a portion of the encapsulant from the upper surface thereof and a portion of the interposer from the fourth surface thereof to expose ends of the conductive posts; and removing the carrier, thereby improving the connection quality between the semiconductor chip and the interposer. | 06-11-2015 |
20150162264 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure. | 06-11-2015 |
20150155250 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility. | 06-04-2015 |
20150145747 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is disclosed, which includes: a substrate; at least an electronic element disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic element; and an antenna body embedded in the encapsulant without contacting with the substrate and exposed from a surface of the encapsulant. Since the antenna body is not disposed on the substrate, the surface area of the substrate can be reduced to meet the miniaturization requirement of the electronic package. | 05-28-2015 |
20150144384 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads. | 05-28-2015 |
20150137337 | SEMICONDUCTOR PACKAGE AND LEAD FRAME - A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use. | 05-21-2015 |
20150123287 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE AND PACKAGING STRUCTURE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween. | 05-07-2015 |
20150123251 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed, which includes: a packaging structure having at least a semiconductor element; and at least three shielding layers sequentially stacked on the packaging structure so as to cover the semiconductor element, wherein a middle layer of the shielding layers is lower in electrical conductivity than adjacent shielding layers on both sides of the middle layer, thereby reducing electromagnetic interferences so as to increase the shielding effectiveness. | 05-07-2015 |
20150102484 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging. | 04-16-2015 |
20150091150 | PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield. | 04-02-2015 |
20150069628 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided. | 03-12-2015 |
20150069605 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF AND SEMICONDUCTOR STRUCTURE - A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer. | 03-12-2015 |
20150064850 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications. | 03-05-2015 |
20150054150 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor package is disclosed, which includes: providing first and second packaging substrates, wherein a surface of the first packaging substrate has first conductive pads and first conductive posts formed on the first conductive pads, a surface of the second packaging substrate has second conductive pads and second conductive posts formed on the second conductive pads, and the surface of the second packaging substrate further has a semiconductor chip disposed thereon; disposing the first packaging substrate on the second packaging substrate in a manner that the first conductive posts correspond in position to and are electrically connected to the second conductive posts; and forming an encapsulant between the first and second packaging substrates for encapsulating the first and second conductive posts and the semiconductor chip, thereby effectively preventing solder bridging and increasing the product yield and reliability. | 02-26-2015 |
20150041972 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component. | 02-12-2015 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 02-12-2015 |
20150035164 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced. | 02-05-2015 |
20150035163 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced. | 02-05-2015 |
20150028913 | TESTING APPARATUS AND TESTING METHOD - The present invention proposes a testing method for testing a semiconductor element, including: providing a semiconductor element having a first surface on which a first testing area is formed and a second surface on which a second testing surface is formed; placing the semiconductor element on a plane surface, allowing any one of the first surface and the second surface to be in no parallel to the plane surface; and electrically connecting a testing apparatus to the first testing area and the second testing area of the semiconductor element. The semiconductor element is placed in a non-horizontal manner on the testing apparatus, which makes contact with the two opposing surfaces of the semiconductor element in a horizontal way without directly exerting a downward force against the surface of the semiconductor element, thereby preventing the semiconductor element from damages. | 01-29-2015 |
20150028485 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die attach area defined on the surface of the substrate body corresponding in position to the opening for a semiconductor chip to be disposed thereon. The die attach area covers the entire opening or the metal layer is formed within the die attach area, thereby effectively preventing package delamination and improving the product yield. | 01-29-2015 |
20150028081 | METHOD FOR FABRICATING WIRE BONDING STRUCTURE - A method for fabricating a wire bonding structure is disclosed, which includes: providing a substrate having a plurality of bonding pads; and foaming a ball end of a bonding wire on at least one of the bonding pads by performing a scrubbing process along a path around a periphery of the bonding pad, thereby preventing delamination of the ball end of small size from the bonding pad. | 01-29-2015 |
20150014864 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a package unit mounted on and electrically connected to the substrate, and a second encapsulant formed on the substrate and encapsulating the package unit. The package unit includes an interposer, a semiconductor chip mounted on the interposer in a flip-chip manner, and a first encapsulant formed on the interposer and encapsulating the semiconductor chip. The present invention reduces the fabricating time and increases the yield of the final product. | 01-15-2015 |
20150014848 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield. | 01-15-2015 |
20140367850 | STACKED PACKAGE AND METHOD OF FABRICATING THE SAME - A stacked package and a method of fabricating the same are provided. The stacked package includes: a first package, having a first encapsulant, a first electrical connection structure formed on one surface of the first encapsulant, a plurality of first conductive pillars formed in the first encapsulant, and a first semiconductor chip disposed in the first encapsulant are electrically connected to the first electrical connection structure; and a second package stacked on the first package, wherein the second package has a second encapsulant, a second electrical connection structure formed on the second encapsulant, a second semiconductor, a chip disposed in the second encapsulant and electrically connected to the second electrical connection structure, and a plurality of second conductive pillars formed in the second encapsulant and electrically connected to the first electrical conduction pillars. The stacked package can provide a great number of inputs/outputs for electronic applications. | 12-18-2014 |
20140367849 | INTERPOSER AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an interposer is provided, including forming a plurality of first openings on one surface side of a substrate, forming a first metal layer in the first openings, forming on the other surface side of the substrate a plurality of second openings that are in communication with the first openings, forming a second metal layer in the second openings, and electrically connecting the first metal layer to the second metal layer, so as to form conductive through holes. The conductive through holes are formed stage by stage, such that the fabrication time in forming the metal layers is reduced, and a metal material will not be accumulated too thick on a surface of the substrate. Therefore, the metal material has a smoother surface, and no overburden will be formed around end surfaces of the through holes. An interposer is also provided. | 12-18-2014 |
20140353850 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a circuit board; a carrier disposed on the circuit board; an RF chip disposed on the carrier; a plurality of high level bonding wires electrically connecting electrode pads of the RF chip and the circuit board; and an encapsulant formed on the circuit board for encapsulating the carrier, the high level bonding wires and the RF chip. The present invention positions the RF chip at a high level so as to facilitate element arrangement and high frequency wiring on the circuit board, thereby achieving a highly integrated wireless SiP (System in Package) module. | 12-04-2014 |
20140342506 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place. | 11-20-2014 |
20140342505 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant. | 11-20-2014 |
20140332976 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement. | 11-13-2014 |
20140327131 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers. | 11-06-2014 |
20140320374 | MULTI BANDWIDTH BALUN AND CIRCUIT STRUCTURE THEREOF - A multi bandwidth balun is provided, including a main signal port, a main inductor electrically connected to the main signal port, a first inductor inducted mutually with the main inductor to constitute a first inductor of a first conversion circuit, a first capacitor module connected in parallel to the first conversion circuit, two first signal ports electrically connected to the first capacitor module, a first main capacitor electrically connected to the first signal port and the first capacitor module therebetween, a second inductor inducted mutually with the main inductor to constitute a second inductor of a second conversion circuit, a second capacitor module connected in parallel to the second conversion circuit, two second signal ports electrically connected to the second capacitor module, and a second main capacitor electrically connected to the second signal port and the second capacitor module therebetween. | 10-30-2014 |
20140264958 | SEMICONDUCTOR PACKAGE, FABRICATION METHOD THEREOF AND MOLDING COMPOUND - A semiconductor package is disclosed, which includes: a substrate body; a semiconductor element disposed on the substrate body; and a molding compound forms on the substrate body for encapsulating the semiconductor element. The molding compound contains a metal oxide so as to have a high insulation impedance and a high heat dissipating rate and be capable of suppressing electromagnetic interference. | 09-18-2014 |
20140252603 | SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIAS - A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield. | 09-11-2014 |
20140231972 | MULTI-CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided. | 08-21-2014 |
20140217605 | INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF - An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time. | 08-07-2014 |
20140210672 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure is provided, including a substrate, a package encapsulant disposed on the substrate, and an antenna structure corresponding to a disposing area of the package encapsulant and having a first extension layer, a second extension layer disposed on the substrate, and a connection portion disposed between and electrically connected to the first extension layer and the second extension layer. Through the formation of the antenna structure on the disposing area of the package encapsulant, the substrate is not required to be widen, and, as such, the electronic package structure meets the miniaturization requirement. | 07-31-2014 |
20140206146 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 07-24-2014 |
20140204806 | DUPLEXER, CIRCUIT STRUCTURE THEREOF AND RF TRANSCEIVER APPARATUS COMPRISING THE DUPLEXER - A duplexer is provided, which includes a first, a second and a third signal ports; a first filter and a second filter. The first filter has first, second, and third resonant circuits that have first, second and third inductors, respectively. The first, second and third inductors are mutually inductive. The first and third resonant circuits are electrically connected to the first and second signal ports, respectively. The second filter has fourth, fifth and sixth resonant circuits that have fourth, fifth and sixth inductors, respectively. The fourth resonant circuit is connected in series with the first resonant circuit. The fifth inductor and the fourth inductor are mutually inductive. The sixth resonant circuit is electrically connected to the third signal port. The second filter further has a main capacitor connected in series with the fifth and sixth resonant circuits respectively and located therebetween. | 07-24-2014 |
20140203771 | ELECTRONIC PACKAGE, FABRICATION METHOD THEREOF AND ADHESIVE COMPOUND - An electronic package is provided, which includes: a substrate, a charging module and a coil module disposed on the substrate, and an encapsulant formed on the substrate for encapsulating the charging module and the coil module. The coil module has a plurality of coils having an opening, an adhesive compound formed on the coils in a manner that the opening of the coils is exposed from the adhesive compound, and a magnet inserted in the opening of the coils. Further, the adhesive compound comprises a metal oxide. Compared with the conventional ferrite, the adhesive compound is flexible and not easy to crack or break during transportation or assembly, thereby greatly improving the charging efficiency of the electronic package. | 07-24-2014 |
20140203395 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved. | 07-24-2014 |
20140191393 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including a carrier having electrical connecting pads, a semiconductor element disposed on the carrier and having electrode pads, conductive elements electrically connected to the electrode pads and the electrical connecting pads, fluorine ions formed between the conductive elements and the electrode pads or between the conductive elements and the electrical connecting pads, and an encapsulant formed on the carrier and the conductive elements, wherein the electrode pads or the electrical connecting pads are formed by aluminum materials to form fluorine aluminum by way of packaging the fluorine ions after the completion of the packaging process. Accordingly, the corrosion resistance of the semiconductor package is increased. | 07-10-2014 |
20140191386 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer. | 07-10-2014 |
20140191376 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided. | 07-10-2014 |
20140184261 | TESTING APPARATUS AND TESTING METHOD - A testing method is provided, including providing a testing apparatus including a carrier member and a testing element, the carrier member comprising a first surface, a second surface opposing the first surface, and an elastic conductive area defined on the first surface; disposing an object-to-be-tested on the elastic conductive area; electrically connecting the testing element to the object-to-be-tested and the carrier member, to form an electric loop among the carrier member, the object-to-be-tested and the testing element. Through the design of the elastic conductive area, the object-to-be-tested can be secured with a small pressure applied thereto, and is prevented from being cracked. | 07-03-2014 |
20140183755 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes a carrier having a mounting area and at least a grounding pad; a substrate body having opposite first and second surfaces and a plurality of conductive vias each having a first end exposed from the first surface and a second end opposite to the first end, the substrate body being disposed on the mounting area of the carrier through the second surface thereof; a metal layer formed on the first surface of the substrate body and exposing the first ends of the conductive vias; a conductive body electrically connecting the metal layer and the grounding pad; and a semiconductor element disposed on the substrate body and electrically connected to the first ends of the conductive vias, thereby achieving an EMI shielding effect to prevent interference between electromagnetic waves or electrical signals of the substrate body and the semiconductor element. | 07-03-2014 |
20140183721 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved. | 07-03-2014 |
20140179067 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip. | 06-26-2014 |
20140162409 | METHOD FOR FABRICATING QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE - A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield. | 06-12-2014 |
20140154842 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 06-05-2014 |
20140138791 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly. | 05-22-2014 |
20140134805 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: providing a heat dissipating structure having a heat dissipating portion, a deformable supporting portion coupled to the heat dissipating portion, and a coupling portion coupled to the supporting portion; coupling a carrier having a semiconductor element carried thereon to the coupling portion of the heat dissipating structure to form between the carrier and the heat dissipating portion a receiving space for the semiconductor element to be received therein; and forming in the receiving space an encapsulant that encapsulates the semiconductor element. The use of the supporting portion enhances the bonding between the heat dissipating structure and a mold used for packaging, thereby preventing the heat dissipating structure from having an overflow of encapsulant onto an external surface of the heat-dissipating portion. | 05-15-2014 |
20140134797 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips. | 05-15-2014 |
20140131072 | CONNECTION STRUCTURE FOR A SUBSTRATE AND A METHOD OF FABRICATING THE CONNECTION STRUCTURE - A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads. | 05-15-2014 |
20140127864 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer. | 05-08-2014 |
20140127838 | METHOD OF TESTING A SEMICONDUCTOR PACKAGE - A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased. | 05-08-2014 |
20140124950 | SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF - A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer. | 05-08-2014 |
20140118019 | METHOD OF TESTING A SEMICONDUCTOR STRUCTURE - A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save. | 05-01-2014 |
20140117538 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a package structure is provided, which includes the steps of: providing an interposer having a plurality of recess holes; forming a conductive bump in a lower portion of each of the recess holes; forming a conductive through hole on the conductive bump in each of the recess holes; removing a portion of the interposer so as for the conductive bumps to protrude from the interposer; and mounting at least a first external element on the conductive bumps, thereby simplifying the fabrication process, shortening the process time and reducing the material cost. | 05-01-2014 |
20140117537 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed is a semiconductor package including an encapsulant having a top surface and a bottom surface opposite to the top surface; a semiconductor chip embedded in the encapsulant having an active surface, an inactive surface opposite to the active surface, and lateral surfaces interconnecting the active surface and the inactive surface, wherein the active surface protrudes from the bottom surface of the encapsulant and the semiconductor chip further has a plurality of electrode pads disposed on the active surface; a positioning member layer formed on a portion of the bottom surface of the encapsulant, covering the lateral surfaces of the semiconductor chip that protrude therefrom, and exposing the active surface; and a build-up trace structure disposed on the active surface of the semiconductor chip and the positioning member layer formed on the bottom surface of the encapsulant. The present invention also provides a method of fabricating a semiconductor package. | 05-01-2014 |
20140099755 | FABRICATION METHOD OF STACKED PACKAGE STRUCTURE - A fabrication method of a stacked package structure is provided, which includes the steps of: providing a substrate having at least a semiconductor device disposed thereon; and disposing a semiconductor package on the substrate through a plurality of conductive elements such that the semiconductor device is located between the substrate and the semiconductor package, and forming an encapsulant between the substrate and the semiconductor package to encapsulate the semiconductor device. The encapsulant can be formed on the semiconductor package first and then laminated on the substrate to encapsulate the semiconductor device, or alternatively the encapsulant can be filled between the substrate and the semiconductor package driven by a capillary force after the semiconductor package is disposed on the substrate. Therefore, the present invention alleviates pressure and temperature effects on the package to prevent warpage of the substrate and facilitate fabrication of multi-layer stacked package structures. | 04-10-2014 |
20140091462 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods. | 04-03-2014 |
20140084455 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability. | 03-27-2014 |
20140080265 | FABRICATION METHOD OF CARRIER-FREE SEMICONDUCTOR PACKAGE - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 03-20-2014 |
20140080264 | METHOD FOR FABRICATING LEADFRAME-BASED SEMICONDUCTOR PACKAGE - A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant. | 03-20-2014 |
20140080242 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 03-20-2014 |
20140077387 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-20-2014 |
20140070424 | SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE, AND INTERPOSER STRUCTURE OF THE SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-13-2014 |
20140061928 | INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR PACKAGE - An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps. | 03-06-2014 |
20140057410 | METHOD OF FABRICATING A PACKAGING SUBSTRATE - A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement. | 02-27-2014 |
20140042638 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, which includes: a soft layer having opposite first and second surfaces and first conductive through hole vias; a chip embedded in the soft layer and having an active surface exposed from the first surface of the soft layer; a support layer formed on the second surface of the soft layer and having second conductive through hole vias in electrical connection with the first conductive through hole vias; a first RDL structure formed on the first surface of the soft layer and electrically connected to the active surface of the chip; and a second RDL structure formed on the support layer and electrically connected to the first RDL structure through the first and second conductive through hole vias. The invention prevents package warpage by providing the support layer, and allows disposing of other packages or electronic elements by electrically connecting the RDL structures through the conductive through hole vias. | 02-13-2014 |
20140035156 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency. | 02-06-2014 |
20140027926 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element. | 01-30-2014 |
20140021629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy. | 01-23-2014 |
20140021617 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate. | 01-23-2014 |
20140021591 | EMI SHIELDING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR STACK STRUCTURE - A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference. | 01-23-2014 |
20140015621 | BALANCED-TO-UNBALANCED CONVERTER - A balanced-to-unbalanced converter (balun) is provided, including: a converting circuit having a first processing circuit including a first inductor and a first capacitor connected in series, a second processing circuit including a second capacitor and a second inductor connected in series, the second capacitor being electrically connected to the first inductor, and two balanced output ends connected to the first processing circuit and the second processing circuit, respectively; and a preprocessing circuit connected to the converting circuit and including an unbalanced input end for converting real impedance at the unbalanced input end into complex impedance at the balanced output ends. Accordingly, the balun satisfies the need of the wireless communication chips by providing differential signals with complex impedance. This is done by employing the preprocessing circuit in conjunction with the converting circuit to convert an unbalanced signal with real impedance into a balanced signal with complex impedance. | 01-16-2014 |
20140015125 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements. | 01-16-2014 |
20140008819 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING THE SAME - A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure. | 01-09-2014 |
20140008787 | CONDUCTIVE BUMP STRUCTURE AND METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate. | 01-09-2014 |
20130344661 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased. | 12-26-2013 |
20130341806 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME - A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost. | 12-26-2013 |
20130341774 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield. | 12-26-2013 |
20130341739 | PACKAGE STRUCTURE HAVING MICRO-ELECTRO-MECHANICAL SYSTEM ELEMENT AND METHOD OF FABRICATION THE SAME - A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections. | 12-26-2013 |
20130334694 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability. | 12-19-2013 |
20130334684 | SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE - A substrate structure is provided, including a substrate body and a plurality of traces formed on a surface of the substrate body. At least one of the traces has an electrical contact formed in a groove thereof for electrically connecting an external element, thereby meeting the demands of fine line/fine pitch and miniaturization and improving the product yield. | 12-19-2013 |
20130330883 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure. | 12-12-2013 |
20130328584 | TESTING APPARATUS AND METHOD - Disclosed is a testing apparatus, including: a base having opposite upper and lower surfaces, and a plurality of electrical circuits formed in the base, each of the electrical circuits extending from the upper surface to the lower surface and bending backwards to the upper surface such that two terminal ends of the electrical circuit are located on the upper surface. While in a testing, an element is disposed on the upper surface of the base such that testing probes are placed on the electrical contact spots of both the element and the upper surface of the base, thus without resorting to double sided testing that testing probes are placed on the upper and lower surfaces of the element as mentioned in the prior art. Hence, the testing apparatus and testing method can simplify the testing process and prevent the element from damage caused by mechanical stresses of the testing probes. | 12-12-2013 |
20130326873 | METHOD OF FABRICATING MULTI-CHIP STACK PACKAGE STRUCTURE HAVING INNER LAYER HEAT-DISSIPATING BOARD - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 12-12-2013 |
20130320513 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including: a substrate having at least a conductive pad; a semiconductor element disposed on the substrate; a conductive adhesive formed on top and side surfaces of the semiconductor element and extending to the conductive pad; and an electronic element disposed on the conductive adhesive. The conductive adhesive and the conductive pad form a shielding structure so as to prevent electromagnetic interference from occurring between the semiconductor element and the electronic element. | 12-05-2013 |
20130320463 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure includes: a substrate having a plurality of first conductive pads and a plurality of second conductive pads; an MEMS element disposed on the substrate; a cover member disposed on the MEMS element and having a metal layer formed thereon; a plurality of bonding wires electrically connected to the MEMS element and the second conductive pads of the substrate; a plurality of first wire segments, each having one end electrically connected to a corresponding one of the first conductive pads; and an encapsulant formed on the substrate and encapsulating the MEMS element, the cover member, the first wire segments and the bonding wires, wherein the other end of each of the first wire segments is exposed from the encapsulant. Compared with the prior art, the package structure of the present invention has improved overall yield and functionality. | 12-05-2013 |
20130299968 | SEMICONDUCTOR PACKAGE AND A SUBSTRATE FOR PACKAGING - A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination. | 11-14-2013 |
20130299961 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. | 11-14-2013 |
20130292832 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer. | 11-07-2013 |
20130277858 | ELECTRICAL INTERCONNECTION STRUCTURE AND ELECTRICAL INTERCONNECTION METHOD - An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween. | 10-24-2013 |
20130256915 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency. | 10-03-2013 |
20130256875 | SEMICONDUCTOR PACKAGE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 10-03-2013 |
20130252383 | FABRICATION METHOD OF WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF WAFER LEVEL PACKAGING SUBSTRATE - A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield. | 09-26-2013 |
20130249589 | INTERPOSER AND ELECTRICAL TESTING METHOD THEREOF - An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer. | 09-26-2013 |
20130249082 | CONDUCTIVE BUMP STRUCTURE ON SUBSTRATE AND FABRICATION METHOD THEREOF - A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art. | 09-26-2013 |
20130234337 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved. | 09-12-2013 |
20130228921 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure. | 09-05-2013 |
20130228915 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs. | 09-05-2013 |
20130214310 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package and a fabrication method thereof are disclosed, which is characterized in that a solder material is used to bond an LED chip and a substrate so as to provide a thick joint between the substrate and the LED chip and hence reduce stresses generated between the LED chip and the substrate due to their CTE mismatch, thereby preventing delamination from occurring between the LED chip and the substrate after a reliability test. | 08-22-2013 |
20130203200 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING MEMS ELEMENT - A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process. | 08-08-2013 |
20130200508 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques. | 08-08-2013 |
20130187285 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 07-25-2013 |
20130175563 | LED CHIP STRUCTURE, PACKAGING SUBSTRATE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - An LED package structure includes: a substrate having a die attach pad; a first insulating layer formed on the die attach pad and having a plurality of openings; an LED chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; a second insulating layer formed on the inactive surface and having a plurality of openings, wherein the LED chip is disposed on the substrate with the openings of the second insulating layer corresponding in position to the openings of the first insulating layer; and a plurality of metallic thermal conductive elements formed in the openings of the first insulating layer and the corresponding openings of the second insulating layer, thereby effectively alleviating the conventional problem of thermal stresses induced by a mismatch in CTEs of the LED chip and the substrate. | 07-11-2013 |
20130161837 | SEMICONDUCTOR PACKAGE, PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art. | 06-27-2013 |
20130161802 | SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 06-27-2013 |
20130154765 | CROSS-COUPLED BANDPASS FILTER - A cross-coupled bandpass filter includes first, second, third and fourth resonators such that magnetic couplings are generated between the first and second resonators, between the third and fourth resonators and between the first and fourth resonators, a capacitive coupling is generated between the second and third resonators, and the magnetic coupling between the first and fourth resonators has a polarity opposite to that of the capacitive coupling between the second and third resonators, thereby generating two transmission zeros in a transmission rejection band. | 06-20-2013 |
20130141187 | CROSS-COUPLED BANDPASS FILTER - A cross-coupled bandpass filter includes first, second and third resonators such that a positive mutual inductance is generated between the first and third resonators and mutual inductance generated between the first and second resonators and mutual inductance generated between the second and third resonators have the same polarity, thereby generating a transmission zero in a high frequency rejection band. | 06-06-2013 |
20130115738 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer. | 05-09-2013 |
20130113095 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump. | 05-09-2013 |
20130093629 | PACKAGING STRUCTURE AND METHOD OF FABRICATING THE SAME - A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect. | 04-18-2013 |
20130093086 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased. | 04-18-2013 |
20130075888 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed. | 03-28-2013 |
20130059418 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE DEVICE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer. | 03-07-2013 |
20130034971 | INTERCONNECTING MECHANISM FOR 3D INTEGRATED CIRCUIT - An interconnecting mechanism is provide, which includes paired first sub-interconnecting mechanisms and paired second sub-interconnecting mechanisms. The first pair of sub-interconnecting mechanisms includes first and second axially symmetrical spiral conductive elements. The second pair of sub-interconnecting mechanisms includes third and fourth axially symmetrical spiral conductive elements. Configuring the pairs of sub-interconnecting mechanisms in a differential transmission structure having a spiral shape is used to avert sounds and noise signals between different chips or substrates caused by a miniaturizing fabrication process or an increased wiring density. | 02-07-2013 |
20130032931 | LAYER STRUCTURE WITH EMI SHIELDING EFFECT - A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates. | 02-07-2013 |
20130026657 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area. | 01-31-2013 |
20130026516 | LIGHT-EMITTING DIODE (LED) PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield. | 01-31-2013 |
20130020709 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting. | 01-24-2013 |
20130017643 | METHOD FOR FABRICATING PACKAGE STRUCTURE HAVING MEMS ELEMENTSAANM LIN; Chen-HanAACI Taichung HsienAACO TWAAGP LIN; Chen-Han Taichung Hsien TWAANM CHANG; Hong-DaAACI Taichung HsienAACO TWAAGP CHANG; Hong-Da Taichung Hsien TWAANM LIU; Cheng-HsiangAACI Taichung HsienAACO TWAAGP LIU; Cheng-Hsiang Taichung Hsien TWAANM LIAO; Hsin-YiAACI Taichung HsienAACO TWAAGP LIAO; Hsin-Yi Taichung Hsien TWAANM CHIU; Shih-KuangAACI Taichung HsienAACO TWAAGP CHIU; Shih-Kuang Taichung Hsien TW - A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced. | 01-17-2013 |
20130009311 | SEMICONDUCTOR CARRIER, PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first encapsulant having tapered through holes each having a wide top and a narrow bottom; tapered electrical contacts disposed in the tapered through holes; circuits disposed on a top surface of the first encapsulant and each having one end connecting one of the electrical contacts and the other end having a bonding pad disposed thereon such that the bonding pads are circumferentially arranged to define a die attach area on the top surface of the first encapsulant. As such, a semiconductor chip can be disposed on the top surface of the first encapsulant in the die attach area and electrically connected to the bonding pads through conductive elements, and further a second encapsulant encapsulates the semiconductor chip, the conductive elements, the circuits and the first encapsulant so as to prevent falling off of the electrical contacts and reduce the length of the conductive elements. | 01-10-2013 |
20120326305 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved. | 12-27-2012 |
20120313243 | CHIP-SCALE PACKAGE - A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer. | 12-13-2012 |
20120299683 | ASYMMETRIC DIFFERENTIAL INDUCTOR - An asymmetric differential inductor includes first and second conductive wirings spirally disposed on a substrate having a first input terminal, a second input terminal, a ground terminal, and a central conductive wiring. The central conductive wiring has a central contact connecting the ground terminal and a central end away from the ground terminal. The first conductive wiring extends across the central conductive wiring and has a first contact connecting the first input terminal and a first end connecting the central end. The second conductive wiring extends across the central conductive wiring and interlaces with the first conductive wiring and has a second contact connecting the second input terminal and a second end connecting the central end. Corresponding portions of wiring sections of the first and second conductive wirings at opposite sides of the central conductive wiring are asymmetrical to one another to thereby save substrate space and facilitate circuit layout. | 11-29-2012 |
20120299682 | SYMMETRIC DIFFERENTIAL INDUCTOR STRUCTURE - A symmetric differential inductor structure includes first, second, third and fourth spiral conductive wirings disposed in four quadrants of a substrate, respectively. Further, a fifth conductive wiring connects the first and fourth spiral conductive wirings, and a sixth conductive wiring connects the second and third spiral conductive wirings. The first and second spiral conductive wirings are symmetric but not intersected with one another, and the third and fourth spiral conductive wirings are symmetric but not intersected with one another. Therefore, the invention attains full geometric symmetry to avoid using conductive wirings that occupy a large area of the substrate as in the prior art and to thereby increase the product profit and yield. | 11-29-2012 |
20120299177 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THE SAME - A semiconductor component structure is provided, which includes a body formed with openings, an insulating layer formed on surfaces of the body and the openings, conductive bumps formed in the openings, and a re-distributed circuit formed by conductive traces electrically connecting the conductive bumps, wherein the conductive traces are formed on a portion of the insulating layer on the body. As the conductive traces and the conductive bumps are formed on and in the body prior to the formation of the re-distributed circuit. The process for fabricating the semiconductor component structure is simplified and the reliability of the semiconductor component structure is enhanced. A method for fabricating the semiconductor component is also provided. | 11-29-2012 |
20120292722 | PACKAGE STRUCTURE HAVING MEMS ELEMENTS AND FABRICATION METHOD THEREOF - A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs. | 11-22-2012 |
20120286425 | PACKAGE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization. | 11-15-2012 |
20120286308 | LED PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - An LED package structure and a method of fabricating the same. The LED package structure includes: a package unit including a submount with a cavity, and a light emitting chip disposed in the cavity; a first light-pervious element disposed in the cavity; a multi-layered dam structure concentrically disposed on the first light-pervious element or around a rim of the cavity; a first light-pervious packaging material filled in the dam structure; and a second light-pervious element that combines with the dam structure. Accordingly, the multi-layered dam structure provides an advantage of eliminating gaps and overcomes the problem resulting from the uneven thickness of the first light-pervious packaging material used in the prior technique, thereby ensuring high illumination efficiency and enhanced airtightness. | 11-15-2012 |
20120280384 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability. | 11-08-2012 |
20120256215 | PACKAGE HAVING LIGHT-EMITTING ELEMENT AND FABRICATION METHOD THEREOF - A package having a light-emitting element includes a substrate having a light-emitting element disposed thereon, an insulating layer formed on the substrate and having an opening for exposing the light-emitting element, a florescent layer formed in the opening of the insulating layer for encapsulating the light-emitting element, and a transparent material formed on the florescent layer and the insulating layer. As such, a specific space can be defined by the insulating layer for exposing the light-emitting element and forming the fluorescent layer, thereby overcoming the problem of non-uniform coating of phosphor powder as encountered in prior techniques. | 10-11-2012 |
20120241937 | PACKAGE STRUCTURE HAVING MICRO-ELECTROMECHANICAL ELEMENT - Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above. | 09-27-2012 |
20120235259 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes: a substrate having a plurality of semiconductor components disposed thereon; an encapsulant covering the substrate and the semiconductor components; and a metal layer formed on the exposed surfaces of the encapsulant, wherein the encapsulant is formed with a trench for dividing into a plurality of package units on the substrate to allow each of the package units to have at least one of the semiconductor components, and the metal layer is formed in the trench to encompass the encapsulant on the periphery of the semiconductor components, thereby preventing interference of electromagnetic waves between the semiconductor components. | 09-20-2012 |
20120228769 | CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 09-13-2012 |
20120224328 | INNER-LAYER HEAT-DISSIPATING BOARD, MULTI-CHIP STACK PACKAGE STRUCTURE HAVING THE INNER LAYER HEAT-DISSIPATING BOARD AND FABRICATION METHOD THEREOF - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 09-06-2012 |
20120223425 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress. | 09-06-2012 |
20120181562 | PACKAGE HAVING A LIGHT-EMITTING ELEMENT AND METHOD OF FABRICATING THE SAME - A package includes at least a chip encapsulated by an encapsulant. Conductive bumps are disposed on a first surface of the chip, for a circuit board to be disposed thereon. A phosphor layer is formed on a second surface of the chip opposing the first surface. The package further comprises a light-pervious mask that covers the phosphor layer. Since the phosphor layer and the light-pervious mask are directly formed on the chip, the chip is prevented from being disposed in the groove of the substrate. As a result, the wet etching process is omitted, and the fabrication cost is reduced. A method of fabricating the package is also provided. | 07-19-2012 |
20120170162 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes a substrate unit having conductive pads and ESD protection pads formed on a bottom surface thereof; an encapsulant covering a top surface of the substrate unit; and a metal layer disposed on a top surface of the encapsulant and having connecting extensions formed on side surfaces of the substrate unit and the encapsulant for electrically connecting the ESD protection pads, wherein portions of the side surfaces of the substrate unit corresponding in position to the conductive pads are exposed from the metal layer so as to ensure that solder bumps subsequently formed to connect the conductive pads of the semiconductor package to a circuit board are not in contact with the metal layer, thereby effectively avoiding the risk of short circuits. | 07-05-2012 |
20120168936 | MULTI-CHIP STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A multi-chip stack package structure includes: an inner-layer heat sink having a first surface and a second surface opposing one another and having a plurality of conductive vias penetrating the first surface and the second surface; a first chip disposed on the first surface of the inner-layer heat sink; and a second chip disposed on the second surface of the inner-layer heat sink. Thereby, a heat-dissipating path is provided within inner-layers of the multi-chip stack package structure, and the rigidity of the overall structure is enhanced. | 07-05-2012 |
20120168777 | LED PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - An LED package structure includes: a carrier; at least a first protruding portion and a plurality of electrical contacts formed on the carrier; a plurality of LED chips disposed on the first protruding portion and on the carrier in a region free from the first protruding portion, respectively; a plurality of bonding wires electrically connecting the | 07-05-2012 |
20120161301 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure. | 06-28-2012 |
20120133032 | PACKAGE HAVING ESD AND EMI PREVENTING FUNCTIONS AND FABRICATION METHOD THEREOF - A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits. | 05-31-2012 |
20120129315 | Method for fabricating semiconductor package - A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board. | 05-24-2012 |
20120127693 | LIGHT-PERMEATING COVER BOARD, METHOD OF FABRICATING THE SAME, AND PACKAGE HAVING THE SAME - A light-permeating cover board structure includes a first light-permeating board having a light-permeating substrate and a frame formed on the light-permeating substrate, wherein a first recess portion is defined by the frame and the light-permeating substrate; a first fluorescent material filled in the first recess portion; and a second light-permeating board disposed on the first light-permeating board and covering the first fluorescent material in the first recess portion. Therefore, the first light-permeating board and the second light-permeating board prevent the first fluorescent material from contacting moisture. | 05-24-2012 |
20120126397 | SEMICONDUCTOR SUBSTRATE AND METHOD THEREOF - A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test. | 05-24-2012 |
20120112363 | CHIP STRUCTURE HAVING REDISTRIBUTION LAYER - A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer. | 05-10-2012 |
20120104517 | PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT AND MANUFACTURING METHOD THEREOF - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 05-03-2012 |
20120086117 | PACKAGE WITH EMBEDDED CHIP AND METHOD OF FABRICATING THE SAME - A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified. | 04-12-2012 |
20120074538 | PACKAGE STRUCTURE WITH ESD AND EMI PREVENTING FUNCTIONS - A package structure with ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a carrier having first and second ground structures electrically insulated from one another; a semiconductor component disposed on one surface of the carrier and electrically connected to the first ground structure; and a lid member disposed to cover the carrier and the semiconductor component and electrically connected to the second ground structure. The semiconductor component and the lid member are electrically connected with the first ground structure and the second ground structure, respectively, such that electrostatic charges and electromagnetic waves can be conducted away individually without damaging the semiconductor component, thereby improving yield and reducing the risk of short circuits. | 03-29-2012 |
20120061825 | CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME - A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. | 03-15-2012 |
20120056279 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element includes: a packaging substrate having first and second wiring layers on two surfaces thereof and a chip embedded therein; a first dielectric layer disposed on the packaging substrate and the chip; a third wiring layer disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and the third wiring layer and having a recessed portion; a lid disposed in the recessed portion and on the top surface of the second dielectric layer around the periphery of the recessed portion, wherein the portion of the lid on the top surface of the second dielectric layer is formed into a lid frame on which an adhering material is disposed to allow a substrate having an MEMS element to be attached to the packaging substrate with the MEMS element corresponding in position to the recessed portion, thereby providing a package structure of reduced size and costs with better electrical properties. | 03-08-2012 |
20120038044 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage. | 02-16-2012 |
20120032347 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product. | 02-09-2012 |
20120018870 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result. | 01-26-2012 |
20120013006 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost. | 01-19-2012 |
20120007234 | SEMICONDUCTOR PACKAGE WITHOUT CHIP CARRIER AND FABRICATION METHOD THEREOF - A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer. | 01-12-2012 |
20120007233 | SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - A semiconductor element and a fabrication method thereof. The method includes forming an encapsulating layer on a semiconductor silicon substrate having electrode pads and a passivation layer formed thereon, the encapsulating layer covering the electrode pads and a part of the passivation layer that surrounds the electrode pads; forming a covering layer on the passivation layer and the encapsulating layer with a plurality of openings that expose a part of the encapsulating layer; forming a bonding metallic layer on the part of the encapsulating layer that are exposed from the openings and electrically connecting the bonding metallic layer to the encapsulating layer, wherein the bonding metallic layer is not greater in diameter than the encapsulating layer; and forming a conductive element on the bonding metallic layer. The encapsulating layer provides a good buffering effect to prevent electrode pads from delamination or being broken caused by the direct stress from the conductive element. | 01-12-2012 |
20120001328 | CHIP-SIZED PACKAGE AND FABRICATION METHOD THEREOF - A chip-sized package and a fabrication method thereof are provided. The method includes forming a protection layer on an active surface of a chip and attaching a non-active surface of the chip to a carrier made of a hard material; performing a molding process and removing a protection layer from the chip; performing an RDL process to prevent problems as encountered in the prior art, such as softening of adhesive films, an encapsulant overflow, a pliable chip and chip deviation or contamination caused by directly adhering the active surface of the chip to the adhesive film that may even lead to inferior electrical contacts between a circuit layer and a plurality of chip bond pads during subsequent RDL process, and cause the package to be scraped. Further, the carrier employed in this invention can be repetitively used in the process to help reduce manufacturing costs. | 01-05-2012 |
20120001274 | WAFER LEVEL PACKAGE HAVING A PRESSURE SENSOR AND FABRICATION METHOD THEREOF - A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path. | 01-05-2012 |
20110298126 | CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD - A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality. | 12-08-2011 |
20110287588 | METHOD FOR MANUFACTURING HEAT-DISSIPATING SEMICONDUCTOR PACKAGE STRUCTURE - A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking. | 11-24-2011 |
20110287587 | METHOD FOR FABRICATING HEAT DISSIPATION PACKAGE STRUCTURE - A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip, and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome. | 11-24-2011 |
20110227226 | MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA - The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier. | 09-22-2011 |
20110221059 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield. | 09-15-2011 |
20110221049 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield. | 09-15-2011 |
20110198737 | QUAD FLAT NON-LEADED PACKAGE STRUCTURE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING FUNCTION AND METHOD FOR FABRICATING THE SAME - A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed. | 08-18-2011 |
20110177643 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING MEMS ELEMENT - A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process. | 07-21-2011 |
20110175210 | EMI SHIELDING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques. | 07-21-2011 |
20110175179 | PACKAGE STRUCTURE HAVING MEMS ELEMENT - A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect. | 07-21-2011 |
20110159643 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging. | 06-30-2011 |
20110157851 | PACKAGE STRUCTURE - A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted. | 06-30-2011 |
20110156252 | SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 06-30-2011 |
20110156227 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques. | 06-30-2011 |
20110156180 | PACKAGE STRUCTURE HAVING MICRO-ELECTROMECHANICAL ELEMENT AND FABRICATION METHOD THEREOF - Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above. | 06-30-2011 |
20110143498 | SEMICONDUCTOR PACKAGE WITH A SUPPORT STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions. | 06-16-2011 |
20110129966 | SEMICONDUCTOR DEVICE HAS ENCAPSULANT WITH CHAMFER SUCH THAT PORTION OF SUBSTRATE AND CHAMFER ARE EXPOSED FROM ENCAPSULANT AND REMAINING PORTION OF SURFACE OF SUBSTRATE IS COVERED BY ENCAPSULANT - A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device. | 06-02-2011 |
20110070728 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS - A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers. | 03-24-2011 |
20110070697 | METHOD FOR FABRICATING STACK STRUCTURE OF SEMICONDUCTOR PACKAGES - A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages. | 03-24-2011 |
20100323513 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS - A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect. | 12-23-2010 |
20100297842 | CONDUCTIVE BUMP STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump. | 11-25-2010 |
20100267202 | METHOD OF FABRICATING STACKED SEMICONDUCTOR STRUCTURE - A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash. | 10-21-2010 |
20100233855 | METHOD FOR FABRICATING CHIP SCALE PACKAGE STRUCTURE WITH METAL PADS EXPOSED FROM AN ENCAPSULANT - A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures. | 09-16-2010 |
20100170709 | ELECTRONIC CARRIER BOARD AND PACKAGE STRUCTURE THEREOF - An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence. | 07-08-2010 |
20100151631 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION DEVICE - A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package. | 06-17-2010 |
20100052146 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product. | 03-04-2010 |
20100041181 | HEAT DISSIPATING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure. | 02-18-2010 |