SILICON MOTION, INC. Patent applications |
Patent application number | Title | Published |
20160132432 | Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same - A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected. | 05-12-2016 |
20160132253 | Data Storage Device and Operating Method - A data storage device includes a FLASH memory and a controller. The FLASH memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the FLASH memory and utilized to execute a garbage-collection process on the FLASH memory according to a number of spare blocks in the FLASH memory and a number of inefficient blocks where most of the pages are spare in the FLASH memory. The garbage-collection process is utilized for merging at least two inefficient blocks to release at least one spare block from the inefficient blocks. | 05-12-2016 |
20160132249 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A storage-unit access interface is directed to program data into the nth wordline of a storage unit. The storage-unit access interface is directed to program the same data into the (n−1)th wordline of the storage unit after the storage unit completes the data programming of the nth wordline of the storage unit. The storage-unit access interface is directed to program the same data into the (n−2)th wordline of the storage unit after the storage unit completes the data programming of the (n−1)th wordline of the storage unit, where n is an integer greater than 2. | 05-12-2016 |
20160124845 | Data Storage Device and Flash Memory Control Method - A flash memory control technology with high efficiency, which records a logical page table in a random access memory. The logical pages that have been collected from a data-interspersed block into a destination block of a flash memory are recorded in the logical page table. Without accessing a logical-to-physical address mapping table stored in the flash memory, the physical pages in the data-interspersed block corresponding to the logical pages recorded in the logical page table are regarded as containing invalid data. | 05-05-2016 |
20160124844 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A flash memory control technology with high performance efficiency. A logical block table is managed on a random access memory to record logical blocks of breakpoints of sequential write operations issued from a host to write a flash memory. It is prohibited from performing garbage collection on the logical blocks recorded in the logical block table. In this manner, the system resources are no longer wasted by hastily organizing incomplete sequential write data. | 05-05-2016 |
20160124820 | Data Storage Device and Flash Memory Control Method - A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a run-time write block of a flash memory and thereby generate a duplicated page in the run-time write block. The microcontroller is further configured use the mapping information accessed from the duplicated page in rebuilding a physical-to-logical address mapping table rather than the mapping information accessed from the last write page. The microcontroller is configured to maintain the physical-to-logical address mapping table on a random access memory for the run-time write block and is further configured to use the physical-to-logical address mapping table to update a logical-to-physical address mapping table maintained in the flash memory. | 05-05-2016 |
20160124806 | Data Storage Device and Flash Memory Control Method - A flash memory control method with high reliability. A control unit coupled between a host and a flash memory gathers statistics about commands performed on the flash memory. Based on the statistical result, the control unit is triggered to perform a sample check and correction procedure on the flash memory. The data within an endangered block failing to pass the sample check and correction procedure may be entirely moved to a spare block in the flash memory. | 05-05-2016 |
20160124650 | Data Storage Device and Flash Memory Control Method - A flash memory control technology with high performance efficiency is provided. A microcontroller is configured to build an ending logical address table in a random access memory to record ending logical addresses of a plurality of old write commands issued from a host. The microcontroller is further configured to compare a starting address of a current write command issued from the host and information in the ending logical address table, to determine whether any of the plurality of old write commands is a former string write command with respect to the current write command that the former string write command and the current write command combined together form sequential data writing. The microcontroller is further configured to overwrite an ending logical address of the current write command onto a column in the ending logical address table recording the ending logical address of the former string write command. | 05-05-2016 |
20160103734 | Data Storage Device and Data Maintenance Method Thereof - A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read. | 04-14-2016 |
20160070653 | Methods for Scheduling Read Commands and Apparatuses using the Same - A method for scheduling read commands, performed by a processing unit, including at least the following steps. Logical read commands are received from a master device via a first access interface, where each logical read command requests to read data of a logical address. First physical storage locations of mapping segments associated with the logical addresses are obtained from a high-level mapping table, and a second access interface is directed to read the mapping segments from the first physical storage locations of a storage unit. Second physical storage locations associated with the logical addresses are obtained from the mapping segments, and the second access interface is directed to read data from the second physical storage locations of the storage unit. The first access interface is directed to clock the data of the logical addresses out to the master device. | 03-10-2016 |
20160062908 | Methods for Maintaining a Storage Mapping Table and Apparatuses using the Same - A method for maintaining a storage mapping table. An access interface is directed to read a group mapping table from the last page of a block of a storage unit. The block is allocated to store data of a plurality of groups, each group stores information indicating which location in the storage unit stores data of an LBA (Logical Block Address) range, and the group mapping table stores information indicating which unit of the block stores the latest data of each group. The group mapping table is stored in a DRAM (Dynamic Random Access Memory). The access interface is directed to read data of each group from the storage unit according to the group mapping table. The data of each group is stored in a specified location of a storage mapping table of the DRAM. | 03-03-2016 |
20150332779 | Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof - A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution. | 11-19-2015 |
20150188575 | Data Storage Device and Error Correction Method Thereof - A data storage device including a flash memory and a controller. The controller is configured to perform a first error correction on at least one first data sector of a first page of the flash memory when a predetermined condition is satisfied, obtain a data-sector read voltage of the first data sector through the first error correction, retrieve data of a first meta-data sector of the first page by the data-sector read voltage, and perform a second error correction on the retrieved data of the first meta-data sector read by the data-sector read voltage. | 07-02-2015 |
20150185264 | PHASE DETECTOR WITH METASTABLE PREVENTION STAGE - A phase detector, arranged for comparing a phase of a first clock with a phase of a second clock. The phase detector includes a phase detection stage and a metastable prevention stage. The phase detection stage is arranged to receive the first clock and the second clock, and to output a phase comparison result in accordance with the phase of the first clock and the phase of the second clock. The metastable prevention stage is arranged to receive the phase comparison result, and to output a stable phase comparison result in accordance with the phase comparison result. | 07-02-2015 |
20150178001 | Data Storage Device and Data Maintenance Method Thereof - A data storage device including a flash memory, a temperature sensor, and a controller. The temperature sensor detects surrounding ambient temperature. The controller reads the temperature sensor to obtain a current temperature parameter at a predetermined time, compares a plurality of write temperatures of the blocks with the current temperature parameter one by one, and writes data stored in at least one first block of the blocks into at least one third block of the blocks, wherein the first block corresponds to at least one first write temperature of the write temperatures, and the difference between the first write temperature and the current temperature parameter is greater than a predetermined value. | 06-25-2015 |
20150160688 | Data Storage Device and Mode-Detection Method Thereof - A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode. | 06-11-2015 |
20150146486 | Data Storage Device and Flash Memory Control Method - A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block. | 05-28-2015 |
20150127888 | Data Storage Device and Error Correction Method Thereof - A firmware loading system including a first memory device and a calculation unit. The first memory device includes a first firmware code, wherein the first firmware code has a predetermined code and a plurality of parameter tables, and the parameter tables are arranged to set up a plurality of registers of a second memory device. The calculation unit is arranged to perform a firmware insertion procedure, wherein, during the firmware insertion procedure, the calculation unit selects one of the parameter tables according to a selection signal, compiles the selected parameter table and the predetermined code into a second firmware code, and writes the second firmware code in a flash memory of the second memory device. | 05-07-2015 |
20150097540 | LOW-DROP REGULATOR APPARATUS AND BUFFER STAGE CIRCUIT HAVING HIGHER VOLTAGE TRANSITION RATE - A low-drop regulator (LDO) apparatus includes an operational amplifier, a buffer stage circuit, and a power transistor. The operational amplifier is used for receiving a reference voltage and a feedback voltage to generate a first voltage. The buffer stage circuit is coupled to the power transistor and the operational amplifier and used for buffering the first voltage to generate a second voltage. The power transistor is coupled to the buffer stage circuit and used for generating an output voltage according to the second voltage wherein the output voltage is proportional to the feedback voltage. In addition, the buffer stage circuit is arranged to determine whether to mirror and generate a mirrored current according to the first voltage and to generate the second voltage for providing the second voltage to the power transistor to control on/off state of the power transistor when the mirrored current is generated. | 04-09-2015 |
20150067239 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks. | 03-05-2015 |
20150067233 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H | 03-05-2015 |
20150058700 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit. | 02-26-2015 |
20150058699 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch. | 02-26-2015 |
20150058662 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, includes at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch. | 02-26-2015 |
20150058661 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After a notification indicating that errors presented in a message of a sector within a RAID (Redundant Array of Independent Disk) group cannot be fixed by an error correction algorithm with a horizontal ECC (Error Correction Code) of the sector is received, addresses of the other sectors within the RAID group are determined Information is provided to a sector-decoding unit and a RAID-decoding unit, which indicates that a vertical correction procedure has been activated. Storage-unit access interfaces are directed to read content from the determined addresses of the storage unit, thereby enabling the RAID-decoding unit to recover the message of the sector by using the read content. | 02-26-2015 |
20150046762 | Data Storage Device and Method for Restricting Access Thereof - A data storage device including a flash memory, a temperature sensor and a controller. The flash memory has a plurality of blocks, and each of the blocks has a plurality of pages. The temperature sensor detects surrounding ambient temperature and to produce a temperature parameter accordingly. The controller is arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on. The controller reads the temperature sensor to obtain a first temperature parameter in the first maintenance procedure and determines a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition includes the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished. | 02-12-2015 |
20150043280 | Data Storage Device and Voltage Protection Method Thereof - A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode. | 02-12-2015 |
20150032944 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks and some blocks are pushed into a jail queue to be inaccessible. When the jail queue is full and any block within the spare queue has an erase count greater than any block within the jail queue, for wear leveling between the different blocks within the FLASH memory, the controller releases a first block selected from the jail queue and pushes a second block selected from the spare queue into the jail queue. | 01-29-2015 |
20150026540 | FLASH DEVICE AND OPERATING METHOD THEREOF - A flash device is provided. A flash memory includes a plurality of pages. A controller coupled to the flash memory includes an operating unit, an error correction code (ECC) decoder and a processing unit. The operating unit receives a plurality of bytes of the page which are from the flash memory and corresponding to a read command, and obtains an operating result according to a logic level of each bit of each of the bytes. The ECC decoder decodes the bytes of the page according to an ECC code. The processing unit determines whether the page is valid data according to the decoded bytes, and determines whether the page is an empty page according to the operating result when the page is not the valid data. | 01-22-2015 |
20140380026 | CONTROL DEVICE AND ACCESS SYSTEM UTILIZING THE SAME - A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit. | 12-25-2014 |
20140380000 | MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME - A memory controller is coupled to a memory device including a first block and a second block and includes a first register module, a first execution unit and a second register module. The first register module includes a plurality of set registers to store a first configuration file and a second configuration file. The first execution unit computes data stored in the first block simultaneously according to the first and the second configuration files to generate a first computation result and a computation operation result. The second register module includes a plurality of result registers to store the first and the second computation results. | 12-25-2014 |
20140359346 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - The present invention provides a data storage device including a flash memory and a controller. The flash memory is capable of operating in a SLC mode and a non-SLC mode. The controller is configured to perform a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page. | 12-04-2014 |
20140359345 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure. | 12-04-2014 |
20140304458 | MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME - A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level. | 10-09-2014 |
20140297912 | STATUS SWITCHING METHOD - The present invention provides a status switching method applied to a slave device. The status switching method includes: receiving a command wrapper from a host device; receiving a status query command corresponding to the command wrapper from the host device; transmitting a status wrapper to the host device in response to the status query command; and refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper is transmitted. | 10-02-2014 |
20140285165 | LOW-DROPOUT VOLTAGE REGULATOR APPARATUS CAPABLE OF ADAPTIVELY ADJUSTING CURRENT PASSING THROUGH OUTPUT TRANSISTOR TO REDUCE TRANSIENT RESPONSE TIME AND RELATED METHOD THEREOF - A low-dropout voltage regulator apparatus includes a voltage source circuit, an error amplifier, an output transistor, a resistor-capacitor circuit, a detection circuit, and a current adjusting circuit. The voltage source circuit generates a reference voltage signal and at least one threshold voltage signal. The error amplifier receives the reference voltage signal and a feedback voltage signal to generate an output control signal. The output transistor provides an output current for the output terminal according to the output control signal. The resistor-capacitor circuit generates the feedback voltage signal using voltage dividing according to a voltage corresponding to the output current. The detection circuit compares at least one threshold voltage signal with the output voltage to generate at least one control voltage signal. The current adjusting circuit adaptively adjusts the current passing though the output transistor to decrease the transient response time according to the at least one control voltage signal. | 09-25-2014 |
20140281826 | ERROR CORRECTION METHOD AND MEMORY DEVICE - The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved. | 09-18-2014 |
20140266124 | SWITCHING-CAPACITOR REGULATOR WITH CHARGE INJECTION MODE FOR HIGH LOADING CURRENT - A switching-capacitor regulator with a charge injection mode for a high loading current is provided, where the switching-capacitor regulator is used to generate an output voltage at an output node, and the switching-capacitor regulator includes a storage capacitor, a switch module, a current source and a control unit. The switch module is coupled between the storage capacitor, a first supply voltage, a second supply voltage and the output node. The current source is coupled to the output node, and is used for selectively providing a current to the output node. The control unit is coupled to the switch module and the output node, and is used for controlling the switch module to selectively charge or discharge the storage capacitor, and for controlling the current source to selectively provide the current to the output node, to adjust a voltage level of the output voltage. | 09-18-2014 |
20140250259 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to. | 09-04-2014 |
20140250258 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method. The control method includes the following steps: dividing a plurality of blocks of the FLASH memory into groups to be accessed via different channels; allocating at least one set of cache spaces in a random access memory for temporary write data storage for the different channels; separating write data issued from a host to correspond to the plurality of channels; and, when data arrangement for every channel has been completed in one set of cache spaces, writing the data that has been arranged in the set of cache spaces to the FLASH memory via the plurality of channels corresponding to the different cache spaces of the set of cache spaces. | 09-04-2014 |
20140244992 | Extensible Firmware Interface External Graphic Card, Mainframe System, and Extensible Firmware Interface BIOS Booting Method - A central processing unit of a mainframe system is configured to load a physical graphic card driver into a memory of the mainframe system for performing a display function when the mainframe system is not connected to an Extensible Firmware Interface (EFI) external graphic card. The central processing unit is further configured to load a virtual graphic card driver into the memory of the mainframe system for performing the display function when the mainframe system is connected to the EFI external display card. | 08-28-2014 |
20140241067 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 08-28-2014 |
20140189222 | METHOD FOR PERFORMING DATA SHAPING, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data. | 07-03-2014 |
20140157067 | APPARATUS AND METHOD FOR APPLYING AT-SPEED FUNCTIONAL TEST WITH LOWER-SPEED TESTER - A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result. | 06-05-2014 |
20140146605 | REFRESH METHOD FOR FLASH MEMORY AND RELATED MEMORY CONTROLLER THEREOF - A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space. | 05-29-2014 |
20140136929 | STORAGE MEDIUM, SYSTEM AND METHOD UTILIZING THE SAME - A storage medium receiving write data provided by a host device, providing read data to the host and including a first module and a second module is disclosed. The first module includes a first memory cell and a first controller. The first memory cell stores the write data. The first controller reads the first memory cell to generate a first accessing result. The second module includes a second memory cell and a second controller. The second memory cell stores the write data. The second controller reads the second memory cell. When the first accessing result has an error and the error cannot be corrected by the first controller, the first controller requests the second controller to read the second memory cell to generate a second accessing result, and the second controller serves the second accessing result as the read data and provides the read data to the host. | 05-15-2014 |
20140119116 | DATA WRITING METHOD AND DATA STORAGE DEVICE FOR ADJUSTING PROGRAMMING VOLTAGE VALUES - A data storage device and method including a controller configured to adjust a plurality of programming voltage values for programming most significant bits (MSB) of a plurality of stored data patterns of the memory cells of the flash memory to obtain a plurality of adjusted programming voltage values, wherein the controller is configured to determine a plurality of neighboring data pairs having the stored data patterns corresponding to the programming voltage values neighboring to each other, determine a plurality of difference bits between the stored data patterns of the neighboring data pairs, determine a plurality of target neighboring data pairs with the difference bits corresponding to the most significant bits from the neighboring data pairs, and adjust the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns of the target neighboring data pairs. | 05-01-2014 |
20140112069 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method and device for a flash memory. According to the method, the flash memory obtains write data to be written to the flash memory, directs the flash memory to write a data page of the write data to a strong page of a target pair page of a target block, and directs the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page. | 04-24-2014 |
20140082265 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H2F update technique for a FLASH memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the FLASH memory in accordance with a group count of a buffer block of the FLASH memory. The group count reflects a logical address distribution of write data buffered in the buffer block and with non-updated logical-to-physical address mapping information. The higher the group count, the more dispersed the logical address distribution. In this manner, each update of the logical-to-physical address mapping table just takes a short time. | 03-20-2014 |
20140082225 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined Whether the target memory is in a busy state is then determined When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 03-20-2014 |
20140078825 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module. The controller erases at least one Xblock for space release and moves data on Xblocks for wear leveling. | 03-20-2014 |
20140068158 | FLASH STORAGE DEVICE AND CONTROL METHOD FOR FLASH MEMORY - A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged. | 03-06-2014 |
20140068147 | Flash Memory Devices and Controlling Methods Therefor - A flash memory controller is provided. The flash memory controller includes a read/write unit, a state machine, a processing unit, and a reserve unit. The read/write unit is coupled to a flash memory. The read/write unit is configured to perform a write command or a read command. The state machine is configured to determine a state of the flash memory controller. The processing unit is coupled to the read/write unit and the state machine. The processing unit is configured to control the read/write unit. The reserve unit is coupled to a first data line, a second data line, and the read/write unit. When the flash memory controller is operating abnormally, the reserve unit receives an external signal via the first data line and the second data line and controls the read/write unit according to the external signal. | 03-06-2014 |
20140055469 | PROCESSING METHOD OF AN EXTERNAL-IMAGE DEVICE - A processing method of an external-image device includes the following steps. A first number of basic area-updating requests are received, wherein each of the basic area-updating requests corresponds to an image-updating area. The first number of basic area-updating requests are generated by an electrical device and correspond to an updating content of a displayed image. The image-updating areas corresponding to the first number of basic area-updating requests are calculated to integrate the image-updating areas to a second number of transmission-image areas. The second number of transmission-image areas are transmitted to the external-image device through an external video adaptor. | 02-27-2014 |
20140055321 | IMAGE PROCESSING APPARATUSES AND EXTERNAL IMAGE APPRATUS - An apparatus includes at least an image drawing request reception unit, an instruction generation unit, an encoding unit and a transmission unit. The image drawing request reception unit is configured to receive an image drawing request. The instruction generation unit is configured to connect to the image drawing request reception unit and generate at least one hardware instruction according to the image drawing request. The encoding unit is configured to convert the at least one hardware instruction into a transmission data. The transmission unit is configured to transmit the transmission data to the external image device through a transmission interface. The external image device obtains the at least one hardware instruction by decoding the transmission data and drives an image processing hardware of the external image device to generate a display image according to the hardware instruction. | 02-27-2014 |
20140040413 | Storage Medium, Transmittal System and Control Method Thereof - A storage medium including a first transmittal module and a control module. The first transmittal module includes a plurality of first transmittal pads. The control module determines whether a level state of the first transmittal module is equal to a pre-determined state. When the level state is equal to the pre-determined state, the control module operates in a secure digital (SD) mode. When the level state is not equal to the pre-determined state, the control module operates in an embedded multimedia card (eMMC) mode. | 02-06-2014 |
20140032993 | METHOD FOR MANAGING DATA STORED IN FLASH MEMORY AND ASSOCIATED MEMORY DEVICE AND CONTROLLER - A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result. | 01-30-2014 |
20140019671 | Flash Memory Controllers and Error Detection Methods - A flash memory controller includes a read/write unit, a state machine, a processing unit, and an auxiliary unit. The read/write unit is connected to a flash memory and performs a writing command or a reading command. The state machine is configured to determine a state of the flash memory controller. The processing unit is connected to the read/write unit and the state machine and configured to control the read/write unit. The auxiliary unit is connected to a first data line and a second data line and the processing unit and configured to receive and store a string output from the processing unit. The auxiliary unit outputs the string through the first and second data lines when the flash memory controller completes a writing data transmission. | 01-16-2014 |
20140013063 | Memory Devices and Memory Control Methods - A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block. | 01-09-2014 |
20130339575 | DATA STORAGE DEVICE AND DATA TRIMMING METHOD - A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern. | 12-19-2013 |
20130326121 | DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table. | 12-05-2013 |
20130326120 | DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY - A data storage device and operating method for a FLASH memory are disclosed. The data storage device includes a FLASH memory and a controller. The FLASH memory includes a first block and a second block. The first and second blocks each includes a plurality of pages. The controller executes a firmware to determine whether a data segment from a host is a complete page segment. When the data segment is a complete page segment, the controller stores the data segment into the first block. When the data segment is an incomplete page segment, the controller stores the data into segment the second block. | 12-05-2013 |
20130326118 | Data Storage Device and Flash Memory Control Method - A data storage device and a Flash memory control method. A data storage device comprises a Flash memory and a controller. The controller controls the Flash memory in accordance with firmware. When the firmware is available for at least a predetermined time period without being requested by a host, the controller, driven according to the firmware, performs a garbage-collection operation on the Flash memory without a request from the host. | 12-05-2013 |
20130318284 | Data Storage Device and Flash Memory Control Method - A data storage device and a flash memory control method. The disclosed data storage device includes a random access memory, a flash memory and a controller. The flash memory provides a data space for data storage and an in-system-program (ISP) space stored with ISP codes. One of the ISP codes is a permanent-ISP code. The permanent-ISP code contains a look-up table showing how the ISP codes stored in the flash memory map to the random access memory. By the controller, the permanent-ISP code obtained from the flash memory is loaded into the random access memory. Based on the look-up table contained in the permanent-ISP code and loaded in the random access memory with the permanent-ISP code, subsequently requested ISP codes are obtained from the ISP codes of the flash memory and are loaded into the random access memory. | 11-28-2013 |
20130312123 | EMBEDDED MULTIMEDIACARD AND ELECTRONIC DEVICE USING THE SAME, AND ENERGINING BOARD FOR EMBEDDED MULTIMEDIACARD - An embedded MultiMediaCard (eMMC), an electronic device equipped with an eMMC and an eMMC engineering board are disclosed. The eMMC includes an eMMC substrate plate, a plurality of solder balls and an eMMC chip. The solder balls are soldered to the eMMC substrate plate, and, one of the solder balls is designed as a security protection enable/disable solder ball. The eMMC chip is bound to the eMMC substrate plate, and, the eMMC chip has a security protection enable/disable pin electrically connected to the security protection enable/disable solder ball. The security protection enable/disable pin is internally pulled high by the eMMC chip when the security protection enable/disable solder ball is floating. When the security protection enable/disable solder ball is coupled to ground, the eMMC is protected from software-based attacks. | 11-21-2013 |
20130311813 | METHOD AND APPARATUS FOR PERFORMING CLOCK EXTRACTION - A method and apparatus for performing clock extraction are provided. The method includes: performing edge analysis on a Training Sequence Equalization (TSEQ) pattern carried by a set of received signals that are received from a Universal Serial Bus (USB) port of an electronic device, to dynamically generate a plurality of analysis results; and performing frequency calibration on a frequency of an output clock of a Numerically Controlled Oscillator (NCO) according to a frequency that different types of analysis results within the plurality of analysis results alternatively occur, to utilize the output clock as a reference clock after completing the frequency calibration. More particularly, the method further includes: generating a set of de-multiplexed signals respectively corresponding to a plurality of bits, to perform the edge analysis by comparing respective voltage levels of de-multiplexed signals corresponding to every two adjacent bits of the plurality of bits within the set of de-multiplexed signals. | 11-21-2013 |
20130311705 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a plurality of flash memory areas and a controller. Each of the flash memory areas comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, selects a target memory area to which the target data is to be written from the flash memory areas, sets a physical address range parameter according to the target memory area, sets a spare block pool parameter according to the target memory area, and writes the target data to a current data block of the target memory area. | 11-21-2013 |
20130311704 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current programming data block, determines whether a current programming page is a first page of the current programming data block, determines whether data move information is set when the current page is not the first page, and when the data move information is set, perform a data move process according to the data move information within a limited time period. | 11-21-2013 |
20130311703 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the hot spare block count is greater than zero when the current programming page is the first page, and sets data move information for a wear-leveling process when the hot spare block count is greater than zero. | 11-21-2013 |
20130311702 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage device is coupled to a host and includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein a spare block count indicates a total number of the spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the spare block count is less than a spare block count threshold when the current programming page is the first page, and sets data move information for a data merge process when the spare block count is less than the spare block count threshold. | 11-21-2013 |
20130311701 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current data block, and determines whether the current data block is full. When the current data block is full, the controller updates at least one table according to the information of the current data block. | 11-21-2013 |
20130311698 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller determines a minimum erase count from the erase counts of the spare blocks and the data blocks, adds a first difference to the minimum erase count to obtain a jail threshold, compares the erase counts of the spare blocks with the jail threshold to obtain a plurality of jail blocks with the erase counts greater than the jail threshold, and confines the jail blocks to a jail pool. | 11-21-2013 |
20130305061 | DATA STORAGE DEVICE AND DATA PROTECTION METHOD - A flash memory includes a plurality of blocks. A controller encrypts a first file to produce a first encrypted file and stores the first encrypted file to the flash memory, wherein the controller further comprises a key generation module, an encryption/decryption module and a key eliminating module. The key generation module produces a first key according to a first write command of a host device, wherein the first key is stored in a first block of the blocks. The encryption/decryption module encrypts the first file according to the first key to produce a first encrypted file, wherein the first encrypted file is stored in at least one second block of the blocks. The key eliminating module deletes the first key stored in the first block according to a first eliminating command in order to invalidate the first encrypted file stored in the second block. | 11-14-2013 |
20130304977 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access management includes: with regard to a same Flash cell of a Flash memory, receiving a first digital value outputted by the Flash memory, requesting the Flash memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the Flash cell, and a number of various possible states of the Flash cell correspond to a possible number of bit(s) stored in the Flash cell; based upon the second digital value, generating/obtaining soft information of the Flash cell, for use of performing soft decoding; and controlling the Flash memory to perform sensing operations by respectively utilizing a plurality of sensing voltages that are not all the same, in order to generate the first digital value and the second digital value. | 11-14-2013 |
20130300755 | ELECTRONIC APPARATUS AND METHOD FOR DATA TRANSMISSION FROM AN ELECTRONIC APPARATUS TO A DISPLAY DEVICE - The invention provides an electronic apparatus. In one embodiment, the electronic apparatus is coupled to a display device, and comprises a memory, a data transmission interface, and a control module. The memory comprises a virtual frame buffer for storing data to be transmitted to the display device. The data transmission interface performs data transmission between the electronic apparatus and the display device. The control module stores a current character image corresponding to a current character in the virtual frame buffer when users input the current character to an input device, determines whether a prior image which has not been transmitted to the display device exists in the virtual frame buffer, determines whether the current character image matches the prior image, and combines the prior image with the current character image to obtain a combined image in place of the prior image when the current character image matches the prior image. | 11-14-2013 |
20130276130 | Secure Digital Card, and Secure Digital Card Operating System and Operating Method - A Secure Digital (SD) card, and an operating system and an operating method for the SD card are disclosed. The disclosed SD card has a Flash memory and a controller. The Flash memory contains a data storage space and a Content Protection Recorded Media (CPRM) support space. The controller executes a firmware of the SD card, such that read/write commands provided from a host for the CPRM support space are regarded and executed as security commands and a CPRM mechanism is operated over the data storage space. | 10-17-2013 |
20130250709 | TESTING SYSTEM AND TESTING METHOD THEREOF - A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data. | 09-26-2013 |
20130235162 | 3D IMAGE-CAPTURING METHOD, 3D CAMERA AND LEVEL-ALIGNMENT MACHINE FOR 3D CAMERA - A 3D image-capturing method, a 3D camera and a level-alignment machine for a 3D camera are disclosed. The method includes the following steps: capturing a left- and a right-eye image by a left- and a right-eye camera, respectively; comparing the left- and right-eye images to observe similar columns between the left- and right-eye images; comparing the left- and right-eye images once again over the similar columns to observe similar rows between the left- and right-eye images; and, referring to the similar columns between the left- and right-eye images, vertically shifting the left- and right-eye images to horizontally align the left- and right-eye images to generate a 3D image. | 09-12-2013 |
20130219249 | METHOD FOR DETERMINING PARITY CHECK MATRIX UTILIZED IN FLASH MEMORY SYSTEM AND RELATED FLASH MEMORY SYSTEM THEREOF - A method for determining a parity check matrix utilized in a flash memory system is disclosed. The parity check matrix comprises M×N blocks. The method comprises generating a first set of candidate blocks as candidates of a first set of blocks of the M×N blocks; calculating a plurality of first estimated results corresponding to the first set of candidate blocks; determining content of a first block of the M×N blocks according to a best result of the first estimated results; generating a second set of candidate blocks as candidates of a second set of blocks of the M×N blocks; calculating a plurality of second estimated results corresponding to the second set of candidate blocks by considering the content of the first block; determining content a second block of the M×N blocks according to the second estimated results. | 08-22-2013 |
20130219247 | Method for Accessing Flash Memory and Associated Flash Memory Controller - An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory. | 08-22-2013 |
20130219108 | Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values. | 08-22-2013 |
20130215682 | Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof - A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution. | 08-22-2013 |
20130215678 | Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method comprises: controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data; performing an error correction hard decode according to the first binary digit; controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result; and performing an error correction soft decode according to the first binary digit and the second binary digit. | 08-22-2013 |
20130203466 | SECURE DIGITAL CARD - The invention provides a secure digital card. In one embodiment, the secure digital card is coupled to a cell phone, and comprises a smart card, a secure digital card controller (SDC), a first power control circuit, and a second power control circuit. When the cell phone wants to perform a near-end payment process, the SDC controls the first power control circuit to supply a first voltage generated by a first power supply pin of a near field communication (NFC) controller to a power receive pin of the smart card. When the cell phone wants to perform a far-end payment process, the SDC controls a second power control circuit to supply a second voltage generated by a second power supply pin of the SDC to the power receive pin of the smart card. | 08-08-2013 |
20130201763 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 08-08-2013 |
20130187799 | SERIALIZER AND DATA SERIALIZING METHOD - The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data. | 07-25-2013 |
20130182503 | METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY - An exemplary method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states. The method includes: controlling the flash memory to perform at least one read operation upon the memory cell to obtain at least one binary digit for representing a bit of the N bits data; generating a codeword for representing the bit of the N bits data according to the at least one binary digit, wherein the codeword is different from the at least one binary digit; providing the codeword to an error correction decoder for performing an error correction operation. | 07-18-2013 |
20130176785 | METHOD FOR ACCESSING A FLASH MEMORY, AND ASSOCIATED FLASH MEMORY SYSTEM - A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided. | 07-11-2013 |
20130154861 | TESTING APPARATUS AND METHOD FOR TESTING ANALOG-TO-DIGITAL CONVERTER - The invention provides a testing apparatus. In one embodiment, the testing apparatus receives a plurality of bit signals output by an analog-to-digital converter, and comprises a plurality of frequency counters and a comparison module. The frequency counters respectively calculate a plurality of transition frequencies of the values of the bit signals. The comparison module respectively compares the transition frequencies with a plurality of ideal transition frequencies to obtain a plurality of error frequencies. The performance analysis module estimates a performance value of the analog-to-digital converter according to the error frequencies. | 06-20-2013 |
20130145078 | METHOD FOR CONTROLLING MEMORY ARRAY OF FLASH MEMORY, AND FLASH MEMORY USING THE SAME - A control method for a Flash memory array and a Flash memory is disclosed. The Flash memory array includes a plurality of blocks which are classified into groups and each group includes at least one block. The control method includes the steps of: recognizing an attribute of data transferred from a host, obtaining a storage group selected from the groups based on the attribute of the data, and storing the data into the blocks of the storage group and thereby the blocks of a same group store data of a same attribute; and performing a valid data collection, restricted to the blocks belonging to a same group, to release blocks of space. | 06-06-2013 |
20130138871 | Flash Memory Device and Data Access Method for Same - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory, a controller, and a random access memory. The flash memory comprises a plurality of blocks for data storage. The random access memory stores a read count table for recording read counts of the blocks. When the read counts of a plurality of original blocks are greater than a threshold according to the read count table, the controller obtains a plurality of spare blocks from the flash memory as mirror blocks respectively corresponding to the original blocks, and copies a portion of a plurality of data pages of the original blocks to the mirror blocks whenever the original blocks are read until all of the data pages of the original blocks have been copied to the mirror blocks. | 05-30-2013 |
20130132772 | EMBEDDED MEMORY WITH SYSTEM REPAIR DATA AND SYSTEM REPAIR METHOD THEREFOR - An embedded memory with system repair data is provided. The embedded memory includes a flash memory unit, a storage unit, and a control unit. The flash memory unit stores an in-system programming (ISP) code. The storage unit stores a system repair code. The system repair code is used for rebuilding the ISP code. The control unit is electrically connected to the flash memory unit and the storage unit. The control unit determines whether the ISP code has been broken and reads the system repair code to rebuild the ISP code when the ISP code has been broken. A system repair method for the embedded memory is also provided, which comprises the steps of determining that the ISP code stored in the flash memory unit has been broken, reading the system repair code stored in the memory unit, and rebuilding the ISP code according to the system repair code. | 05-23-2013 |
20130132654 | METHOD FOR CONTROLLING ACCESS OPERATIONS OF A FLASH MEMORY, AND ASSOCIATED FLASH MEMORY DEVICE AND FLASH MEMORY CONTROLLER - A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided. | 05-23-2013 |
20130132649 | Flash Memory Controller and Method for Generating a Driving Current for Flash Memories - The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories. | 05-23-2013 |
20130124940 | MEMORY CONTROLLER WITH LOW DENSITY PARITY CHECK CODE DECODING CAPABILITY AND RELEVANT MEMORY CONTROLLING METHOD - A memory controller is disclosed, having a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word. | 05-16-2013 |
20130113959 | ANTI-FLICKER CAMERA AND IMAGE CAPTURE METHOD THEREOF - Anti-flicker camera and image capture method are disclosed. According to the disclosed method, exposure integrals of different lines of an image sensed by a camera device are calculated. The exposure integrals are compared with reference exposure integrals of the plurality of lines, respectively, to calculate exposure integral offsets for the lines. The reference exposure integrals are estimated from at least one reference image. The positive and negative changes of the exposure integral offsets are statistically analyzed and, accordingly, it is determined whether there is light flicker from background illumination and an auto-exposure control module of the camera device is controlled based on the determination. | 05-09-2013 |
20130107625 | Flash Memory Apparatus and Method for Controlling Flash Memory Apparatus | 05-02-2013 |
20130103992 | Burn-In Method for Embedded Multi Media Card, and Test Board Using the Same, and Embedded Multi Media Card Tested by the Same - A burn-in method for an embedded Multi Media Card (eMMC), and a test board using the same, and an eMMC tested by the same. The disclosed burn-in method comprises the steps as below: writing a test pattern to a flash memory of the eMMC; electrically connecting a command line of the eMMC to ground to operate the eMMC in a boot state; performing a burn-in procedure on the flash memory when the eMMC is in the boot state and the test pattern is recognized as being contained in the flash memory; and collecting a test report during the burn-in procedure, wherein the test report is stored in the flash memory. | 04-25-2013 |
20130024610 | Method for Operating Non-Volatile Memory and Data Storage System Using the Same - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks having a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 01-24-2013 |
20120324154 | DATA PROGRAMMING METHODS AND DEVICES - A data programming method for a data programming device having a non-volatile memory and a volatile memory, the method comprising determining whether data exceeds one page; if the data does not exceed one page and is insufficient for one page, storing the data into the volatile memory; determining whether next data is to be programmed into the same page as the data stored in the volatile memory; if the next data is to be programmed into the same page as the data stored in the volatile memory, programming the data and the next data into the non-volatile memory. | 12-20-2012 |
20120303879 | Memory Device and Method for Programming Flash Memory Utilizing Spare Blocks - An access method for use in a memory device. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 11-29-2012 |
20120271986 | Flash Memory Device and Data Protection Method Thereof - A data protection method for a flash memory device. In one embodiment, the flash memory device comprises a flash memory for storing protected data. After the flash memory device is coupled to a host, a plurality of current read addresses of a plurality of read commands sent from the host to the flash memory device are recorded. The current read addresses are then compared with a plurality of predetermined read addresses. When the current read addresses are not identical to the predetermined read addresses, the flash memory device is made to enter a data protection mode. When the flash memory device is in the data protection mode, if the flash memory device receives a plurality of data access commands, the data access commands are processed according to a protection mode setting parameter to prevent the protected data from being accessed by the host. | 10-25-2012 |
20120268998 | Flash Memory Device and Method for Handling Power Failure Thereof - A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered. | 10-25-2012 |
20120268991 | DATA STORAGE DEVICE AND BLOCK SELECTION METHOD FOR A FLASH MEMORY - The invention provides a block selection method for a flash memory. First, a flash memory is divided into a plurality of great block groups. Each of the great block groups is then divided into a plurality of block groups. Scores corresponding to the blocks of the flash memory are then recorded in a score table. When the score of a target block selected from the blocks of the flash memory has been amended, the amended score of the target block is compared with a first extreme value and a second extreme value corresponding to the block group and the great block group comprising the target block and the total extreme value. A victim block is then determined from the blocks of the flash memory according to an extreme value table. | 10-25-2012 |
20120246394 | Flash Memory Device and Data Writing Method for a Flash Memory - A data writing method for a flash memory. First, a plurality of blocks of a flash memory is classified into a plurality of block groups according to the erase counts of the blocks. A logical address range of a host is then divided into a plurality of logical address sections respectively corresponding to the block groups. Write data is then received from the host. A target logical address section to which the logical address of the write data belongs is then determined. A target block group corresponding to the target logical address section is then determined. A target block is then selected from the blocks of the target block group. The write data is then written to the target block. | 09-27-2012 |
20120233427 | Data Storage Device and Data Management Method Thereof - An embodiment of the invention provides a data storage device and data management method thereof. The data storage device is coupled to a host, and includes a storage media having data sectors for storing data and a controller. The controller is coupled to the storage media for sequentially receiving one or more read commands and corresponding one or more logical addresses thereto, reads a plurality of first data sectors from the storage media according to the read commands and the corresponding logical addresses, outputs data of the first data sectors to the host, calculates a valid duration required for the one or more read commands, calculates an average data throughput according to the number of the first data sectors and the valid duration, and determines whether the average data throughput exceeds a predetermined threshold. When the average data throughput exceeds the predetermined threshold, the controller performs a blocking procedure to prevent the storage media from being accessed. | 09-13-2012 |
20120233390 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - A flash memory apparatus includes a plurality of blocks comprising a first block, wherein the first block comprises a first page; and a memory controller receiving a first data to be written into the first page of the first block, and when the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records a number of the first block and a number of the first page into the first cache page, and when receiving a command for updating the first block, the memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page. A data update method for such a flash memory is also described. | 09-13-2012 |
20120166718 | Flash Storage Device and Data Writing Method Thereof - A flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks comprising a plurality of ordinary pages and a plurality of reserved pages. The controller receives a current write command and write data from a host, determines a mother block and an FAT block corresponding to the write command, divides data of the mother block and data of the FAT block into a plurality of original data segments and a plurality of updating data segments, integrates the original data segments with the updating data segments to obtain integrated data segments, writes the integrated data segments to an integrated block respectively in a plurality of processing periods of a plurality of subsequent write commands, and writes the subsequent write data to the reserved pages of a plurality of subsequent blocks. | 06-28-2012 |
20120166717 | Data Storage Device and Operation Method Thereof - In one embodiment, a data storage device comprises a first flash memory, a second flash memory, and a controller. The first flash memory stores a first data shaping driver, wherein the first data shaping driver performs a data shaping function. The second flash memory stores user data. The controller enables the first flash memory and disables the second flash memory after the data storage device is turned on, detects whether a second data shaping driver has been installed on a host when the host is connected to the data storage device, installs the first data shaping driver to the host as the second data shaping driver if the second data shaping driver has not been installed on the host, and disables the first flash memory and enables the second flash memory after the first data shaping driver has been installed to the host. | 06-28-2012 |
20120166710 | Flash Memory Device and Data Access Method Thereof - In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory and a controller. The flash memory is used for data storage. The controller receives write data and a write logical address from the host, calculates a running sum value according to the write data, determines whether target data with a running sum equal to the running sum value is stored in the flash memory, reads the target data from the flash memory when the target data is stored in the flash memory, determines whether the target data is identical to the write data, and records a mapping relationship between an original logical address of the target data and a write logical address of the write data in a remapping table without writing the write data to the flash memory when the target data is identical to the write data. | 06-28-2012 |
20120105592 | 3D IMAGE CAPTURING DEVICE AND CONTROLLER CHIP THEREOF - A 3D image capturing device and a controller chip thereof. The controller chip includes a first and a second sensor interface, a pixel data synchronization module, a 3D image generator and an output interface. The first and second sensor interfaces are coupled to a first and a second 2D image capturing device, respectively, to receive a first and a second image. The pixel data synchronization module synchronizes the pixel data of the first and second images. Based on the synchronized first and second images, the 3D image generator generates a 3D-image. By the output interface, the 3D-image capturing device transmits the generated 3D image to be received by a host. | 05-03-2012 |
20120099786 | ELECTRONIC SYSTEMS AND METHODS FOR REPAIRING SCAR IMAGES - A method for repairing scar images is provided, in which a facial region of an image is detected, a first average skin tone value is subtracted from an original pixel value of at least one pixel to generate a first mask value, the first mask value is divided by a constant to generate a first modified mask value; and the first modified mask value is added to the first average skin tone value to generate a first pixel value to serve as a compensated scar pixel value of the pixel. | 04-26-2012 |
20120066437 | DATA PROGRAMMING CIRCUIT AND METHOD FOR OTP MEMORY - A data programming circuit is provided. A one-time-programmable (OTP) stores a first version of encoding data corresponding to a first version of a read-only memory (ROM) code. A control unit stores a second version of the ROM code into the OTP memory, wherein the control unit obtains a matching table according to the first version of the encoding data and the second version of the ROM code. The control unit obtains a first data segment of the first version of the encoding data and a second data segment of the second version of the ROM code that have the same content, according to the matching table. The control unit encodes the second data segment as a specific address, and the specific address points to the first data segment of the first version of the encoding data in the OTP memory. | 03-15-2012 |
20120033492 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values. The adjusted programming voltage values are then sent to the flash memory. The flash memory is then directed to perform data programming according to the adjusted programming voltage values, wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values. | 02-09-2012 |
20120023283 | Flash Memory Device and Method for Managing Flash memory Device - A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller. | 01-26-2012 |
20110289255 | APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE - A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses. | 11-24-2011 |
20110280074 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a pair page record table, wherein the pair page comprises a strong page and a weak page. The flash memory is then directed to write a data page of the write data to the strong page of the target pair page. The flash memory is then also directed to write first predetermined data to the weak page of the target pair page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target pair page, writing of the data page, and writing of the first predetermined data are repeated until all of the write data are written to the target block. | 11-17-2011 |
20110264847 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the memory is received from a host. The spare blocks of the spare area are then sorted according to the erase counts of the spare blocks. A first spare block with the least erase counts is then selected from the spare blocks of the spare area. The write data is then written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-27-2011 |
20110258369 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the flash memory is received from a host. A first spare block with the earliest erase time index is then selected from the spare area. Whether an erase count of the first spare block is less than a first threshold is then determined When the erase count of the first spare block is less than the first threshold, the write data is written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-20-2011 |
20110197107 | NON-VOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address. | 08-11-2011 |
20110179306 | Data Read Method for Flash Memory - The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code. | 07-21-2011 |
20110179249 | Data Storage Device and Method for Handling Data Read Out from Memory - The invention provides a method for handling data read out from a memory. In one embodiment, a controller corresponding to the memory comprises a ping-pong buffer. First, a first sector read time period required by the memory to read and output a data sector to the ping-pong buffer is calculated. A second sector read time period required by a host to read a data sector from the ping-pong buffer is calculated. A page switch time period required by the memory to switch a target read page is obtained. A total sector number is determined according to the first sector read time period, the second sector read time period, and the page switch time period. When the memory outputs data to the ping-pong buffer, a first buffer and a second buffer of the ping-pong buffer are switched to receive the data output by the memory according to the total sector number. | 07-21-2011 |
20110179217 | Flash Storage Device and Data Access Method of Flash Memory - The invention provides a data access method of a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined from the flash memory. Whether a storage space corresponding to the write address in the target block has stored data therein is then determined When the storage space of the target block does not have stored data therein, the target data is written into the storage space of the target block. When the storage space of the target block does have stored data therein, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists in the flash memory, the target data is written into the child block. | 07-21-2011 |
20110179216 | Data Storage Device and Data Access Method - The invention provides a data access method for a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined. Whether a storage space with the write address in the target block stores data is then determined. When the storage space does not store data, the target data is written to the storage space of the target block. When the storage space stores data, whether a file allocation table (FAT) block mapped to the target block exists in the flash memory is then determined. When the FAT block exists, the target data is written to the FAT block. When the FAT block does not exist, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists, the target data is written to the child block. | 07-21-2011 |
20110164490 | FAST FOURIER TRANSFORM AND INVERSE FAST FOURIER TRANSFORM (FFT/IFFT) OPERATING CORE - An FFT/IFFT operating core capable of minimizing a required memory depth during operation is disclosed. The FFT/IFFT operating core includes an inputting buffer, a first multiplexer, an operating module, and a controlling module. The inputting buffer stores and outputs a first FFT input sequence. The first multiplexer is utilized to multiplex the first FFT input sequence and a third input sequence. The controlling module generates a process indicating signal and a bypass indicating signal. The operating module has a plurality of operating stages in series. The operating module transforms the first and third FFT input sequences into a first and third FFT output sequences, respectively, and it transforms a second IFFT input sequence into a second IFFT output sequence. | 07-07-2011 |
20110161566 | WRITE TIMEOUT CONTROL METHODS FOR FLASH MEMORY AND MEMORY DEVICES USING THE SAME - A write timeout control method for a flash memory having a plurality of spare blocks and data blocks including a plurality of mother blocks is disclosed. The method includes the steps of: receiving a write command and a starting logical block address; determining an update mode according to a target mother block linked to the starting logical block address; determining whether a pre-clean operation is performed on a first mother block; if so, performing a post-clean operation on the first mother block during a first time period; re-configuring the first mother block as a spare block; performing a programming process to write data on the target mother block; determining whether the number of mother blocks exceeds a first threshold; and if so, performing the pre-clean operation on a second mother block. The first and second mother blocks are configured as blocks to be cleaned. | 06-30-2011 |
20110153918 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method for a flash memory. First, a write command, a write address, and write data are received from a host. When a total number of block pairs in the flash memory is equal to a threshold value, and execution of the write command increases the total number of block pairs, the write data is written to a data buffer block of the flash memory, and the write address is stored in an address storage table. A target block pair comprising a target mother block and a target child block is then selected from the block pairs for integration. The target mother block and the target child block are integrated into an integrated block during receiving intervals of a plurality of subsequent write commands. Finally, the write command is executed according to the write data stored in the data buffer block and the write address stored in the address storage table. | 06-23-2011 |
20110141030 | Touch Control Apparatus and Touch Point Detection Method - A touch control apparatus, having a touch pad receiving contact from at least one object is provided. Four edges form a rectangle that encircles the touch pad. All the edges are surfaced with geometric textures. A first camera is deposited on a corner of the first edge and the fourth edge of the rectangle, having a field of view sufficient to collect a first image including the second edge and third edge of the rectangle. A second camera is deposited on a corner of the second edge and the fourth edge of the rectangle, having a field of view sufficient to collect a second image including the first edge and third edge of the rectangle. A calculation unit performs a characteristic extraction process on the geometric textures of the first and second images to determine whether an object has touched the touch pad, and if so, coordinates thereof are determined. | 06-16-2011 |
20110134281 | CAMERA DEVICE AND IMAGE PROCESSING METHOD - The invention provides a camera device. In one embodiment, the camera device comprises a sensor and a controller. The sensor detects an image to generate a first image signal with an RGB format. The controller comprises an image processor and a subsequent processor. The image processor converts the first image signal to a second image signal with a YUY2 format. The subsequent processor adjusts a plurality of luma components, a plurality of first chroma components, and a plurality of second chroma components of the second image signal to obtain a plurality of adjusted luma components, a plurality of first adjusted chroma components, and a plurality of second adjusted chroma components of a third image signal. A host receives the third image signal output by the camera, and uses a Direct Show module to convert the third image signal to a fourth image signal with an RGB format. | 06-09-2011 |
20110125955 | FLASH STORAGE DEVICE, DATA STORAGE SYSTEM, AND DATA WRITING METHOD - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of storage units for data storage, wherein the total capacity of each of the storage units is equal to a storage unit capacity. When the flash storage device receives a read capacity command from a host, the controller determines the size of a logical block to be a specific multiple of the storage unit capacity, and sends information about the logical block size to the host in response to the read capacity command, wherein the specific multiple is a natural number. After the host receives the information from the flash storage device, the host retrieves the logical block size from the information, and sends only write data with an amount equal to a multiple of the logical block size to the flash storage device. | 05-26-2011 |
20110119430 | METHODS FOR MEASURING USABLE LIFESPAN AND REPLACING AN IN-SYSTEM PROGRAMMING CODE OF A MEMORY DEVICE, AND DATA STORAGE SYSEM USING THE SAME - A data storage system comprises a host and a flash memory device having a non-non-volatile memory. A controller of the flash memory device calculates an average erase count of the flash memory to obtaining a remaining period of time indicating usable lifespan of the flash memory device. The host obtains an index by comparing the average erase count with a first threshold and determines a performance capability status for the flash memory device. The performance capability status is set to a first status when the average erase count exceeds the first threshold. The host generates an indication based on the performance capability status and performs a limp function responsive to the first status. The limp function loads a predetermined in-system programming code for replacing an original one to configure a minimum number of at least some spare blocks of the flash memory reserved and used for data update operations. | 05-19-2011 |
20110107141 | DATA STORAGE DEVICE, CONTROLLER, AND DATA ACCESS METHOD FOR A DOWNGRADE MEMORY - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses. | 05-05-2011 |
20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 04-21-2011 |
20110087829 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address. | 04-14-2011 |
20110084938 | TOUCH DETECTION APPARATUS AND TOUCH POINT DETECTION METHOD - A touch detection apparatus is provided, in which a touch panel is implemented with four surrounding edges. Three of the edges are embedded with retro-reflection materials. Light sources and pinholes are deployed on both corners of the touch panel, allowing reflections from the three edges to be projected on light sensors through the pinhole. The images projected on the light sensors are analyzed to determine coordinates of one or more contact points on the touch panel. | 04-14-2011 |
20110078393 | MEMORY DEVICE AND DATA ACCESS METHOD - The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands. | 03-31-2011 |
20110078365 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 03-31-2011 |
20110035645 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals. | 02-10-2011 |
20110035636 | DATA STORAGE DEVICE AND METHOD FOR WRITING TEST DATA TO A MEMORY - The invention provides a method for writing test data to a memory. In one embodiment, the memory comprises a data register. First, test data is written to a memory space of the memory. A read-back command and a read-back address of the memory space are then sent to the memory to direct the memory to read the test data from the memory space to the data register. A copy-back command and a copy-back command in a test range of the memory are then sent to the memory to direct the memory to write the test data stored in the data register to the copy-back address. Finally, when the test range of the memory has not been filled with the test data, the step of sending the read-back command and the read-back address is repeated, and the step of sending the copy-back command and the copy-back address is repeated. | 02-10-2011 |
20110032418 | IMAGE PROCESSING DEVICE AND DEINTERLACING METHOD THEREOF - An image processing device and a deinterlacing process thereof are provided. The deinterlacing process reads a memory to retrieve ten pixels of an image field that are temporarily stored in the memory, wherein the ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image filed. Then, the deinterlacing process estimates the data of an interpolated pixel according to the data of the ten pixels. The interpolated pixel is inserted between the first and second rows of the image field on the third column to form a deinterlaced image frame. | 02-10-2011 |
20110029741 | DATA MANAGEMENT METHOD AND MEMORY DEIVCE - The invention provides a data management method for a memory device. In one embodiment, the memory device comprises a plurality of memories for data storage. First, write data and a write logical address is received from a host. The write logical address is then converted to a write physical address. A target memory corresponding to the write physical address is then determined. Whether the target memory is in a busy state is then checked. When the target memory is in the busy state, the write data is written to a buffer area of a substitute memory of the target memory. | 02-03-2011 |
20110029720 | Flash Storage Device and Operation Method Thereof - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table. | 02-03-2011 |
20110022886 | DATA STORAGE DEVICE AND DATA READ METHOD - The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted. | 01-27-2011 |
20110010603 | METHOD FOR PREVENTING DATA SHIFT ERRORS AND CONTROLLER USING THE SAME - A method for preventing a data storage device from data shift errors is provided. First, data is encoded into an error correction code. The error correction code is then scrambled to obtain a scrambled code to be stored in a memory. The scrambled code is then retrieved from the memory to obtain first read-out data. The first read-out data is then descrambled to obtain a first descrambled error correction code. The first descrambled error correction code is then decoded to determine whether the first descrambled error correction code has uncorrectable errors. When the first descrambled error correction code has uncorrectable errors, the scrambled code stored in the memory is read again to output second read-out data without shift errors. Following, the second read-out data is then descrambled to obtain a second descrambled error correction code, and the second descrambled error correction code is then decoded to recover the data. | 01-13-2011 |
20110004812 | CODER-DECODER AND METHOD FOR ENCODING AND DECODING AN ERROR CORRECTION CODE - The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data. | 01-06-2011 |
20100332731 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command. | 12-30-2010 |
20100318840 | MEMORY CARD, NONVOLATILE MEMORY, CONTROLLER, AND METHOD FOR MANAGING WRITING ERRORS FOR NONVOLATILE MEMORIES - The invention provides a method for managing writing errors for a nonvolatile memory. In one embodiment, the nonvolatile memory is coupled to a controller. First, data received from the controller is stored in a data register of the nonvolatile memory. The data stored in the data register is then written to a first memory space with a first write address according to instructions from the controller. The data stored in the data register is kept from being changed after the data is written to the first write address. When an error occurs in writing of the data to the first memory space, a rewrite command is sent from the controller to the nonvolatile memory. After the nonvolatile memory receives the rewrite command, the data stored in the data register is written to a second memory space with a second write address according to the rewrite command. | 12-16-2010 |
20100308789 | BAND GAP REFERENCE VOLTAGE GENERATOR - A band gap reference voltage generator with low working voltage is disclosed. The band gap reference voltage generator can stably operates that the unexpected balance status does not occur due to the manufacturing process inaccuracy or the offset voltage. The band gap reference voltage generator comprises a thermal voltage generation circuit, a voltage level optimizing circuit and a band gap reference voltage generating circuit. The thermal voltage generating circuit provides a first voltage and a second voltage. The first voltage is for generating a current component increased with temperature rising. The second voltage is for generating a current component decreased with temperature rising. The voltage level optimizing circuit optimizes the voltage level of the second voltage to generate a third voltage. The band gap reference voltage generating circuit generates the reference voltage with a specific voltage level corresponding to the first voltage and the third voltage irrelevant with the temperature. | 12-09-2010 |
20100308470 | SEMICONDUCTOR DEVICE AND INDUCTOR - A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (M | 12-09-2010 |
20100306619 | CONTROLLER AND DATA ACCESS METHOD FOR FLASH MEMORIES - The invention provides a controller. In one embodiment, the controller is coupled to a flash memory and a host, and comprises a selective mapper and an error correction code encoder. The selective mapper receives first source data, processes the first source data according to a plurality of pseudo random sequences to obtain a plurality of first mapped data segments, calculates a plurality of cross correlation values between prior data and the first mapped data segments, selects an optimal mapped data segment from the first mapped data segments according to the cross correlation values, and generates output mapped data according to the optimal mapped data segment. The error correction code encoder encodes a first error correction code to be stored in the flash memory according to the output mapped data. | 12-02-2010 |
20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
20100289481 | APPARATUS AND METHOD FOR DC VOLTAGE MEASUREMENT - The invention provides a method for DC voltage measurement. First, an input DC voltage is received. A temporary disturbance signal is then added to the input DC voltage to obtain a disturbed signal, wherein an amplitude of the temporary disturbance signal is greater than precision level of an analog-to-digital converter. The disturbed signal is then converted from analog to digital with the analog-to-digital converter to obtain a plurality of samples with different values. An average value is then derived from the samples. Finally, the average value is output as a measurement value of the input DC voltage. | 11-18-2010 |
20100268868 | FLASH STORAGE DEVICE AND OPERATING METHOD THEREOF - The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory stores a plurality of link tables therein, wherein each of the link tables corresponds to one of a plurality of management units of at least one flash memory, and the link tables store corresponding relationships between logical addresses and physical addresses of the corresponding management units. The controller receives an access logical address from the host, determines an access physical address corresponding to the access logical address according to the link tables stored in the random access memory, and accesses data from the flash memory according to the access physical address. | 10-21-2010 |
20100217918 | DATA STORAGE DEVICE AND METHOD FOR ACCESSING FLASH MEMORY - The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address. | 08-26-2010 |
20100211722 | METHOD FOR TRANSMITTING SPECIAL COMMANDS TO FLASH STORAGE DEVICE - The invention provides a data storage system. In one embodiment, the data storage system comprises a host and a flash storage device. The host sends a series of first access commands for accessing a plurality of special files to the flash storage device. The flash storage device having the stored plurality of special files and a command-symbol mapping table, sequentially generates a plurality of first digits respectively corresponding to the special files accessed by the first access commands to obtain a first data stream, converts the first data stream to a plurality of first special commands according to the command-symbol mapping table, and performs operations according to the first special commands. Each of the special files corresponds to a digit, the command-symbol mapping table records a corresponding relationship between a plurality of symbols and a plurality of special commands, and each of the symbols comprises a plurality of digits. | 08-19-2010 |
20100199156 | Method And Circuit For Encoding An Error Correction Code - The invention provides a method for decoding an error correction code. First, an error syndrome of the error correction code is calculated. A plurality of coefficients of an error locator polynomial of the error correction code is then sequentially determined according to the error syndrome. When a new coefficient of the error locator polynomial is determined, it is also determined whether the new determined coefficient is equal to zero. When the new determined coefficient is equal to zero, a speculated error locator polynomial is built according to a plurality of low-order-term coefficients of the error locator polynomial, wherein the orders of the low-order-term coefficients are lower than that of the new determined coefficient. A Chien search is then performed to determine a plurality of roots of the speculated error locator polynomial. The error correction code is then corrected according to the roots of the speculated error locator polynomial. | 08-05-2010 |
20100174852 | METHOD FOR OPERATING NON-VOLATILE MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks haing a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 07-08-2010 |
20100169547 | METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME - The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data. | 07-01-2010 |
20100153624 | DATA MANAGING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A data managing method for non-volatile memory which comprises a step for receiving a first logical block address and updated data, and a step for merging data in a plurality of physical blocks which have lowest usage rates according to usage parameters in a reference table when the first logical address doesn't exist in the reference table in a buffer memory and a number of pair blocks reaches a determined number. | 06-17-2010 |
20100153623 | Data Managing Method for Flash Memory and Flash Memory Device Using the Same - A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address. | 06-17-2010 |
20100106892 | Access Methods For Memory Devices And Memory Devices Thereof - An access method for use in a memory device is provided. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 04-29-2010 |
20100100665 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - The invention discloses a flash memory apparatus, including a plurality of blocks and a memory controller. The blocks include a first block, wherein the first block includes a first page. The memory controller receives a first data to be written into the first page of the first block. When the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records the number of the first block and the number of the first page into the first cache page. The memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page when receiving an update command. | 04-22-2010 |
20100095148 | LINK TABLE RECOVERY METHOD - A link table recovery method for a flash memory having a plurality of blocks is provided. The method includes: selecting one block from the blocks; selecting a last page containing data of the selected block; checking the last page to determine whether the last page has errors; moving the correct data in the selected block to one of the spare blocks when the last page of the selected block detects errors; and updating a link table of the flash memory. | 04-15-2010 |
20100091132 | IMAGE CAPTURING DEVICE AND IMAGE PREPROCESSING METHOD THEREOF - An image capturing device and the image preprocessing method thereof. The image preprocessing technique receives digital image consisting of luma data and chrominance data, integrates the chrominance data of adjacent rows to generate integrated chrominance data, buffers the luma data and the integrated chrominance data in a group of line buffers, and generates pre-processed chrominance data by making adjacent rows share the same integrated chrominance data. The luma data from the line buffer group form an image with the pre-processed chrominance. The image may be displayed on a display. | 04-15-2010 |
20100088462 | METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes. | 04-08-2010 |
20100085450 | Cameras And Defective Pixel Compensation Methods For Image Sensors Thereof - A camera with defective pixel compensation is provided. The camera comprises a register and a compensating unit. The compensating unit receives an image datum and a plurality of adjacent image data relating to the image datum and, according to the value installed in the register, the compensator selects a reference datum from the plurality of adjacent image data. When the image datum is greater than the reference datum by a threshold value, the compensating unit modifies the image datum according to the reference datum. | 04-08-2010 |
20100077132 | MEMORY DEVICES AND ACCESS METHODS THEREOF - Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable. | 03-25-2010 |
20100070688 | FLASH MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data. | 03-18-2010 |
20100067811 | IMAGE DECODING APPARATUS AND METHOD - An image decoding apparatus is provided, including a parser and an AC decoder. The parser is provided for parsing a bit stream to acquire a first unit. The first unit includes a DC code and a plurality of AC codes respectively corresponding to a DC coefficient and AC coefficients for a first block of the image. The AC decoder generates a plurality of first AC coefficients for the first block by decoding the plurality of AC codes of the first unit, and determines whether the number of the plurality of first AC coefficients exceeds a predetermined parameter. If so, the AC decoder obtains a second unit of the bit stream corresponding to a second block following the first block by performing an AC bypassing process on the first unit. Each AC code comprises a Huffman code and a VLI code. | 03-18-2010 |
20100066848 | IMAGE PROCESSING DEVICE AND METHOD - An image processing device including a camera, a discrete signal processor (DSP) and an output device is disclosed. The camera provides image data for the DSP to process. The DSP samples sub-image data to generate a first image processing signal, discrete cosine transforms the first image processing signal to generate a second image processing signal, uses a quantization table to quantize the second image processing signal to generate a third image processing signal, zig-zag scans the third image processing signal to generate a fourth image processing signal, and Huffman codes the fourth image processing signal to generate an output image signal. The DSP adjusts a cut point of a next fourth image processing signal according to the size of the fourth image processing signal so as to control the size of a next output image signal. The output device outputs the output image signal. | 03-18-2010 |
20100011173 | Downgrade Memory Apparatus, and Method for Accessing a Downgrade Memory - A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information. | 01-14-2010 |
20100011152 | DATA PROGRAMMING METHODS AND DEVICES - A data programming device is provided and comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data is programmed into the non-volatile memory or stored into the volatile memory. If the data exceeds one page, the memory control unit programs a first portion of the data into the non-volatile memory and stores a second portion of the data, which is insufficient for one page, into the volatile memory. | 01-14-2010 |
20100005230 | DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block. | 01-07-2010 |
20100005229 | FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery. | 01-07-2010 |
20090327586 | MEMORY DEVICE AND DATA STORING METHOD - A memory device is provided, comprising a single-level memory unit, a multi-level memory unit and a control unit. The single-level memory unit comprises a first link table and stores data according to the first link table. The multi-level memory unit comprises a second link table and stores data according to the second link table. The control unit directs data which normally belongs to the single-level memory unit to the multi-level memory unit or directs data which normally belongs to the multi-level memory unit to the single-level memory unit according to a control signal. | 12-31-2009 |
20090327550 | EMBEDDED SYSTEM AND HARDWARE SETTING METHOD - An embedded system is provided, comprising a non-volatile memory, at least one slave unit and a master controller. The non-volatile memory comprises at least one hardware setting value and at least one identification number. All of the non-volatile memory, slave unit and the master controller are coupled to a bus. The master controller broadcasts an identification number through the bus to identify the non-volatile memory. Then, the master controller retrieves the slave identification numbers and the hardware setting values through the bus from the non-volatile memory. | 12-31-2009 |
20090319721 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for operating a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a single-level-cell memory and a multiple-level-cell memory. First, new data for updating a logical block address is received from a host. An update count corresponding to the logical block address is then compared with a threshold value. When the update count is greater than the threshold value, it is determined whether a first physical block address corresponding to the logical block address is pointing to a multiple-level-cell block of the multiple-level-cell memory. When the first physical block address is pointing to the multiple-level-cell block, a target single-level-cell block is then selected from the single-level-cell memory. A corresponding relationship between the logical block address and a second physical block address of the target single-level-cell block is then built. The new data is then written to the target single-level-cell block with the second physical block address. | 12-24-2009 |
20090313512 | APPARATUS AND METHOD FOR MEMORY CARD TESTING - The invention provides a memory card testing apparatus for performing automated operations on memory cards. The memory card testing apparatus comprises a host device, a database, a processing unit and an interface. The host device is provided for accessing a memory card. The database maintains a plurality of test script files to be processed. The processing unit is coupled to the database for selecting a test item from one of the plurality of test script files according to a device identification number corresponding to a target device to be tested and a communication protocol associated with the memory card. The interface is connected to the processing unit and the host device for enabling the host device to execute at least one card command on the memory card according to the test item. | 12-17-2009 |
20090300753 | METHOD FOR PREVENTING DATA IN A COMPUTER SYSTEM FROM BEING ACCESSED BY UNAUTHORIZED USER - A computer system is provided comprising a non-volatile storage medium and a processor. The processor acquires authentication information from a first removable storage device, stores the authentication information into the non-volatile storage medium, and forbids data access of the computer system when detecting that a second removable storage device has been inserted and identification data of the second removable storage device is different from the authentication information. | 12-03-2009 |
20090287875 | MEMORY MODULE AND METHOD FOR PERFORMING WEAR-LEVELING OF MEMORY MODULE - The invention comprises a memory module capable of wear-leveling. In one embodiment, the memory module comprises a flash memory and a controller. The flash memory comprises a plurality of management units, wherein each of the management units comprises a plurality of blocks. The controller receives new data with a logical address managed by a first management unit selected from the management units, pops a first spare block from a spare area of the first management unit, determines whether an erase count of the first spare block is greater than a first threshold value, searches a second management unit selected from the management units for a replacing block with an erase count lower than a second threshold value when the erase count of the first spare block is greater than the first threshold value, and directs the first management unit and the second management unit to exchange the first spare block with the replacing block. | 11-19-2009 |
20090285507 | METHOD AND DEVICE FOR SCALING-UP OR SCALING-DOWN IMAGES WITH THE SAME HARDWARE - An image processing device is provided, which scales-up or scales-down images with the same hardware. The device of this invention comprises a line buffer, a first variable, a second variable and a scaler. The scaler practices a scaling-down procedure to scale-down images or scaling-up procedure to scale-up images. | 11-19-2009 |
20090283918 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE - A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region on the top of the first chip. A first power ring and a second power ring are disposed on the first chip, wherein the first and second power rings are respectively electrically connected to the first and second power bonding pads. A second chip, which is operated through a second power connection, is mounted on the central region of the first chip, wherein the second chip comprises a plurality of power bonding pads thereon. A plurality of second bonding wires are electrically connected to the power bonding pads and the second power bonding pads, respectively. | 11-19-2009 |
20090265503 | Non-Volatile Memory Apparatus and Method for Accessing a Non-Volatile Memory Apparatus - A non-volatile memory apparatus and a method for accessing the non-volatile memory apparatus are provided. The non-volatile memory apparatus comprises a management unit, a look-up table and a controller. The management unit comprises a plurality of data blocks and a plurality of spare blocks. The look-up table is adapted to record the read status of the management unit. The controller is configured to read the management unit and then generate the read status denoting the times that the management unit has been read to the look-up table, and to replace one of the data blocks by one of the spare blocks in response to the read status when the times that the management unit has been read exceeds a reference value. | 10-22-2009 |
20090214087 | METHOD AND COMPUTER SYSTEM USING A WEBCAM FOR PROTECING DIGITAL DATA - A method and computer system for digital data protection by using a webcam, comprising: generating a user's biometric feature image; comparing the biometric feature image with identification data; concealing specific data in the computer when the biometric feature image does not conform to the identification data. | 08-27-2009 |
20090209221 | RECEIVER WITH LOW POWER CONSUMPTION - The present invention provides a receiver with low power consumption. The receiver with low power consumption adjusts the gain of the programmable gain amplifier based on the automatic gain controller and further optimizes the gain bandwidth product by current-adjusting unit. The current-adjusting unit thus adjusts the current provided for the programmable gain amplifier, e.g. operational amplifier. Therefore, the gain bandwidth product of the programmable gain amplifier is optimized and the power consumption of the receiver is effectively decreased. | 08-20-2009 |
20090209220 | RECEIVER HAVING LOW POWER CONSUMPTION AND METHOD THEREOF - The present invention provides a receiver having low power consumption and method thereof. The receiver with low power consumption adjusts the gain based on the automatic gain control information. The receiver acquires the signal peaks both after and before a channel selection filter and further analyzes the wanted signal and interference signal with respect to the signal peaks. The receiver determines the magnitude of the wanted signal and determines whether the interference signal exists. The receiver provides the signals with optimal current correspondingly in order to effectively decrease the power consumption of the receiver. | 08-20-2009 |
20090195316 | RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS - A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure. | 08-06-2009 |
20090157947 | Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory - A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly. | 06-18-2009 |
20090144488 | MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY - The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block. | 06-04-2009 |
20090119448 | Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks. | 05-07-2009 |
20090113154 | Non-Volatile Memory Apparatus and Method of Accessing the Same - A non-volatile memory apparatus and an accessing method thereof are provided. A host accesses the non-volatile memory apparatus and gets the accessing result according to the predetermined protocol. Therefore, the host can identify whether the non-volatile memory apparatus has a data area or not and switch to access the data area. The host can then access the non-volatile memory apparatus with high capacity without changing the hardware of the host. | 04-30-2009 |
20090106519 | Storage Device and Method of Accessing a Status Thereof - A storage device and a method of accessing a status thereof are provided. The storage device is disposed in a host. The device data structure field of the storage device is adapted to record the status of the non-volatile memory. The control module is adapted to access the status according to a control signal from the host. Therefore, the operating system or the application of the host is capable of getting the status of the non-volatile memory to ensure the safety of the stored data. | 04-23-2009 |
20090070655 | Method for Generating an ECC Code for a Memory Device - A method for generating an ECC for a flash memory device is provided. The flash memory device only supports flash memories with low-level ECC technology, such as SLC (single-level cell) flash memories. By using a controller with an ECC engine, the flash memory device can directly generate a correct ECC for itself when it reads data from flash memories with high-level ECC technology, such as MLC (multi-layer cell) flash memories. Thus the flash memory device can also support flash memories with high-level ECC technology and reduce the time of reading data. | 03-12-2009 |
20090049233 | Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained. | 02-19-2009 |
20080315854 | Input/Output Regulating Circuitry with Self-Electrostatic-Discharge Protection - An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof. | 12-25-2008 |
20080313390 | Method and System for Presenting an Executing Status of a Memory Card - A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The processing apparatus sends a reading command to the memory card via the access device. The memory card sends executing information in reply after receiving the reading command. Finally, the processing apparatus analyzes the executing information of the memory card and presents a corresponding icon through the application program in association with the analytic result. | 12-18-2008 |
20080301497 | Testing Apparatus, System, and Method for Testing at Least One Device with a Connection Interface - A system, a testing apparatus, and a method for testing at least one device with a connection interface are provided. The system comprises a host, a testing apparatus, and a power supply. The testing apparatus further comprises a microprocessor and at least one current limit module. The host sending a test signal. The power supply provides a voltage to the testing apparatus. The at least one current limit module of the testing apparatus, which is electrically connected to the microprocessor, the at least one device, and the power supply, provides the voltage to the at least one device. When the current passing through the at least one device is greater than the predetermined value, the at least one current limit module of the testing apparatus stops providing the voltage to the at least one device and sends an over current signal to the host via the microprocessor. | 12-04-2008 |
20080256629 | Management Apparatus, System, and Method for Protecting a Memory Storage Card - A management apparatus, system, and method for protecting a memory storage card are provided. The management apparatus comprises an access unit and a check unit. The access unit is configured to read a first security message, and a second security message of the memory storage card. The check unit is configured to check the first and second security messages to generate a check result. The management apparatus makes the memory storage card available according to the check result and efficiently prevents the memory storage card from theft. | 10-16-2008 |