Silicon Image, Inc. Patent applications |
Patent application number | Title | Published |
20160119302 | Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures - A system for receiving and decrypting media content encrypted according to the HDCP protocol is described herein. A receiving device coupled to a plurality of content channels includes an authentication engine to authenticate each content channel and to generate an initial session key associated with each authenticated content channel. The content channels can be, for example, an HDMI channel or an MHL3 channel. A session key indicator indicating a session key used to encrypt media content is received, and an updated session key is generated. The receiving device also includes a stream cipher engine configured to decrypt received encrypted media content using the updated session key. Decrypted media content can then be displayed, for instance on a display of the receiving device. | 04-28-2016 |
20160020779 | Frequency Response Compensation in a Digital to Analog Converter - A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current. | 01-21-2016 |
20150326884 | Error Detection and Mitigation in Video Channels - A system for detecting and mitigating bit errors in transmitted media is described herein. A source device encodes a frame of video, and generates an error code representative of a portion of the encoded frame of video. The portion of encoded frame and the error code are provided to a sink device via a communication channel, such as an HDMI or MHL3 channel. A second error code is generated by the sink device based on the portion of encoded frame, and the error code and second error code are compared to determine if the portion of encoded frame includes an error. If no error is detected, the portion of encoded frame is decoded and outputted. If an error is detected, the portion is replaced with frame data based on at least one other portion of encoded frame to produce a mitigated frame, and the mitigated frame is outputted. | 11-12-2015 |
20150295978 | Communication of Multimedia Data Streams over Multiple Communication Lanes - A transmitter and receiver for communication of multimedia streams across a multi-lane communications link. The transmitter packetizes multimedia streams according to a link layer protocol and distributes the packets across multiple lanes of a communications link. The entire packet, including the header and payload, can be distributed across the lanes in an ordered sequence to increase utilization of the communication lanes. The transmitter may also packetize multiple multimedia streams and intermix the packets across the lanes of the communication lane. The receiver extracts the packets that are distributed across the multiple lanes and decodes the packets into the multimedia streams. | 10-15-2015 |
20150215105 | APPARATUS, METHOD AND SYSTEM FOR ASYMMETRIC, FULL-DUPLEX COMMUNICATION - Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver. | 07-30-2015 |
20150215058 | MECHANISM FOR FACILITATING DYNAMIC COUNTER SYNCHRONIZATION AND PACKETIZATION IN HIGH-DEFINITION MULTIMEDIA INTERFACE AND MOBILE HIGH-DEFINITION LINK - A mechanism for facilitating dynamic counter synchronization and packetization for data streams being communicated over communication devices is described. In one embodiment, a method includes detecting an audio/video (A/V) data stream being encrypted and/or decrypted using one or more high-bandwidth digital content protection (HDCP) engines, where the A/V data stream is communicated between a source device and a sink device. The method may further include dividing a video stream portion of the A/V data stream into a plurality of frames if the A/V data stream relates to a high-definition multimedia interface (HDMI), and synchronizing counter values with indicators within the plurality of frames. | 07-30-2015 |
20150214943 | APPARATUS, SYSTEM AND METHOD FOR PROVIDING SWITCHING WITH A T-COIL CIRCUIT - Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration. | 07-30-2015 |
20150181157 | APPARATUS, SYSTEM AND METHOD FOR FORMATTING AUDIO-VIDEO INFORMATION - Techniques and mechanisms for formatting digital audio-video (“AV”) information. In an embodiment, interface logic includes circuitry to receive digital AV information which, in one or more respects, is according to or otherwise compatible with a first interface specification. The interface logic changes a format of the digital AV information to allow for subsequent physical layer processing which is according to a second interface specification. In another embodiment, conversion logic receives analog signals according to the second interface specification and, based on such analog signals, performs digital information processing for subsequent generation of other analog signals to be transmitted according to the first interface specification. | 06-25-2015 |
20140340579 | Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding - The present disclosure is related to a hardware component for communications over a multimedia communication interface. In one embodiment, a hardware component includes a disparity circuit that stores a disparity value. The disparity value indicates the disparity between the number of “1”s and the number of “0”s previously transmitted by the hardware component. The hardware component also includes circuitry for receiving multimedia data to be scrambled, encoded and transmitted by the hardware component. In one embodiment, the multimedia data includes video data and data island data. In one embodiment, the hardware component generates transition minimized intermediate codes based on values in the guard band data included within the video data and data island data. The hardware component generates encoded guard band codes that are transition minimized as well as direct current balanced. The hardware component transmits the encoded guard band codes over a differential pair of the multimedia communication device. | 11-20-2014 |
20140266450 | METHOD AND APPARATUS FOR IMPLEMENTING WIDE DATA RANGE AND WIDE COMMON-MODE RECEIVERS - Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency. | 09-18-2014 |
20140259050 | MECHANISM FOR FACILITATING SYNCHRONIZATION OF AUDIO AND VIDEO BETWEEN MULTIPLE MEDIA DEVICES - A mechanism for facilitating dynamic synchronization of audio and video for multiple media devices is described. In one embodiment, an apparatus includes first logic to insert a signature in an audio portion of an audio/video data stream. The signature represents uniquely identifiable data and is to be transmitted to a second media device having a display device. The apparatus may include second logic to detect the signature in the audio portion of the audio/video data stream, third logic to calculate latency of the display device using an audio output of the display device, and fourth logic to synchronize the audio output to a corresponding video display based on a feedback loop generated using the audio portion of the audio/video data stream transmitted to the display device and the audio output of the display device. | 09-11-2014 |
20140253208 | Calibration of Single-Ended High-Speed Interfaces - A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage. | 09-11-2014 |
20140253207 | Calibration of Single-Ended High-Speed Interfaces - A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage. | 09-11-2014 |
20140247889 | Transmission And Detection Of Multi-Channel Signals In Reduced Channel Format - Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency. | 09-04-2014 |
20140242834 | INTEGRATED CONNECTOR/FLEX CABLE - A method and apparatus is disclosed herein for providing a connection between a connector and a flex cable. In one embodiment, the connector scheme comprises: a flex ribbon having first and second sides, the first side being opposite the second site, where the flex ribbon has one or more traces on the first side and a ground plane on at least a portion of the second side; and a connector into which the flex ribbon is inserted to make an electrical connection thereto, where the connector has a metal shell in electrical contact with the ground plane while having contacts in electrical contact with the one or more traces. | 08-28-2014 |
20140241457 | APPARATUS, SYSTEM AND METHOD FOR PROVIDING CLOCK AND DATA SIGNALING - Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal. | 08-28-2014 |
20140204994 | AUXILIARY DATA ENCODING IN VIDEO DATA - Embodiments of the invention are generally directed to character data encoding in video data. An embodiment of an apparatus includes a port for connection of the apparatus to a second apparatus; and a transmitter for the transmission of video data and auxiliary data to the second apparatus, wherein the apparatus is to encode the auxiliary data into a portion of the video data and to transmit the encoded data to the second apparatus, the auxiliary data being encoded into unused bits of the portion of video data. | 07-24-2014 |
20140204222 | MECHANISM FOR FACILITATING DYNAMIC PHASE DETECTION WITH HIGH JITTER TOLERANCE FOR IMAGES OF MEDIA STREAMS - A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image. The best phase may represent the image such that the image is displayed in a manner in accordance with human vision perceptions. | 07-24-2014 |
20140193165 | ELECTRONIC ALIGNMENT OF OPTICAL SIGNALS - Embodiments of the invention are generally directed to electronic alignment of optical signals. An embodiment of an apparatus includes an array of photo sensors; a bus coupled with the array, the bus including detection circuitry for each photo sensor to generate a signal in response to the photo sensor receiving an optical signal; and a processing component to process a group of signals, the group of signals being signals generated by the detection circuitry for a subset of the photo sensors in response to the photo sensors receiving the optical signal, to generate an output signal. | 07-10-2014 |
20140192264 | MECHANISM FOR FACILITATING DYNAMIC TIMESTAMP-LESS CLOCK GENERATION FOR TRANSMITTING MEDIA STEAMS OVER SHARED CHANNELS - A mechanism for facilitating dynamic timestamp-less clock generation for transmitting media streams over shared channels is described. In one embodiment, a method includes periodically counting and producing, at a first media device, a number of audio/video (“A/V”) samples, generating a pace clock based on the number of A/V samples, generating a target clock based on the pace clock, and transmitting an A/V media stream based on a frequency difference between a pace frequency relating to the pace clock and a target frequency relating to the target clock. | 07-10-2014 |
20140191813 | Test Solution for a Random Number Generator - A random number generator and method for testing the same are described. In one embodiment, the random number generator comprises one or more ring oscillator structures, each of the one or more ring oscillator structures having a ring oscillator for use in generating random numbers and having a test structure to reconfigure the ring oscillator into a testable structure. | 07-10-2014 |
20140184341 | INTEGRATION OF SIGNAL SAMPLING WITHIN TRANSISTOR AMPLIFIER STAGE - Embodiments of the invention are generally directed to integration of signal sampling within a transistor amplifier stage. An embodiment of an apparatus includes a amplifier stage including a transistor to receive a source signal and produce an output signal, wherein the transistor includes multiple fingers for at least a first electrode of the transistor. The amplifier stage uses connections to some of the fingers of the first electrode for production of the output signal, and uses one or more other fingers for the first electrode of the transistor for a separate function from the production of the output signal. | 07-03-2014 |
20140173680 | FULL-FRAME BUFFER TO IMPROVE VIDEO PERFORMANCE IN LOW-LATENCY VIDEO COMMUNICATION SYSTEMS - Embodiments of apparatuses and methods to decrease a size of a memory in a low-latency video communication system are described. A control unit is configured to monitor a condition associated with at the communication link. The control unit is configured to receive the video content over a link based on monitoring. A memory comprising a full-frame buffer is coupled to the control unit. The full-frame buffer is configured as a history buffer to store a full frame of the video in a coding format that matches the coding format of the video content received over the link. A display unit is coupled to the history buffer. A portion of the full-frame buffer is configured as a network streaming buffer. | 06-19-2014 |
20140168514 | Video Frame Synchronization - Embodiments of the invention are generally directed to video frame synchronization. An embodiment of a method includes receiving a first video data stream from a first source at a first port of a multi-port device, a first video frame of the first video data stream arriving at the first port at a first arrival time, and receiving a second video data stream from a second source at a second port of the multi-port device, a second video frame of the second video data stream arriving at the second port at a second arrival time. The method further includes determining an offset between the first arrival time and the second arrival time, determining one or more correction factors based at least in part on the offset, the one or more correction factors including a first correction factor for the first source, and sending a first command to the first source to modify a time of transmission by the first source of a third video frame following the first frame using the correction factor. | 06-19-2014 |
20140159477 | Power Delivery Over Digital Interaction Interface for Video and Audio (DiiVA) - A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector. | 06-12-2014 |
20140152891 | Method and Apparatus for Reducing Digital Video Image Data - A method and apparatus is disclosed herein for reducing digital video image data. In one embodiment, the method comprises comparing a signature for one or more regions of a current frame of the image data to a signature of a corresponding region of one or more previous frames; and for a region of the one or more regions, sending the region to the data sink if comparing the signature results in determining that the signature of the region does not match a signature of a corresponding region of a previous frame available at the data sink. | 06-05-2014 |
20140126863 | METHODS AND APPARATUSES TO PROVIDE AN ELECTRO-OPTICAL ALIGNMENT - Exemplary embodiments of methods and apparatuses to provide an electro-optical alignment are described. An electrical connector is formed on a printed circuit board substrate that extends onto a side surface of the substrate to form an electrical turn. An optoelectronic die is placed onto the printed circuit board substrate. The optoelectronic die on the printed circuit board substrate is erected over a mounting board to provide optical coupling substantially parallel to the mounting board. | 05-08-2014 |
20140115414 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 04-24-2014 |
20140115110 | MESSAGING TO PROVIDE DATA LINK INTEGRITY - Embodiments of the invention are generally directed to messaging to provide data link integrity. An embodiment of a method includes transmitting a data stream over a data link from a first device to a second device, the data stream including multiple frames, the data stream being transmitted in a first mode. The method further includes determining a data transmission mode change from the first mode to a second mode for the transmission of the data stream from the first device to the second device, generating mode packets, each mode packet including fields to define a plurality of mode elements, the fields of the mode packet being set to indicate the data transmission mode change, and transmitting the mode packets to the second device prior to implementing the data transmission mode change. | 04-24-2014 |
20140111691 | MECHANISM FOR MEMORY REDUCTION IN PICTURE-IN-PICTURE VIDEO GENERATION - A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video. | 04-24-2014 |
20140105517 | SYSTEM, METHOD, AND APPARATUS FOR SMOOTHING OF EDGES IN IMAGES TO REMOVE IRREGULARITIES - System, method, and apparatus for smoothing of edges in images to remove irregularities are disclosed. In one aspect of the present disclosure, a method of image processing includes, identifying an edge in an image having an associated set of edge characteristics, determining the associated set of edge characteristics, and applying a low pass filter to a pixel of the edge based on the associated set of edge characteristics to generate a second image based on the image, wherein the edge in the image is smoothed in the second image. The method further includes generating a third image which is a blend of the original image and the second (edge-smoothed) image based on the associated set of edge characteristics. | 04-17-2014 |
20140085437 | MULTI-VIEW DISPLAY SYSTEM - Embodiments of the invention are generally directed to a multi-view display system. An embodiment of an apparatus includes a display screen to display multiple views simultaneously, and a controller to control the views presented on the display screen. The apparatus is configurable by the controller to provide multiple view settings, the view settings including a first setting in which the apparatus provides a single view to each viewer of the display screen and a second setting in which the apparatus provides a first view to a first viewer of the display screen and a second view to a second viewer of the display screen. A first filtering element filters views presented to viewers of the display screen such that an intended view is displayed to one or more viewers. | 03-27-2014 |
20140078838 | INTERFACING BETWEEN INTEGRATED CIRCUITS WITH ASYMMETRIC VOLTAGE SWING - Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing. An embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel. The first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal. | 03-20-2014 |
20140071271 | COMBINING VIDEO AND AUDIO STREAMS UTILIZING PIXEL REPETITION BANDWIDTH - Embodiments of the invention are generally directed to combining multiple video and audio streams utilizing pixel repetition bandwidth. An embodiment of an apparatus includes a buffer to receive pixel data and a clock of a first video data stream; and a multiplexer to remove pixel repetition of a second video data stream and combine the pixel data of the first and second video data streams to generate a merged data stream, the multiplexer to alternate between the pixel data of the first and second video data streams in the merged data stream. The merged data stream includes pixel data of the first and second video data streams in a line of data, the line of data including control information identifying the pixel data of the first and second video data streams. | 03-13-2014 |
20140059616 | ON SCREEN DISPLAYS ASSOCIATED WITH REMOTE VIDEO SOURCE DEVICES - In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed. | 02-27-2014 |
20140059295 | SMART SCALABLE STORAGE SWITCH ARCHITECTURE - A method and system for providing advanced storage features using commodity, consumer-level storage devices is provided. The advanced storage system is a component that is connected between the computer system and one or more physical disk drives. The host interface of the advanced storage system presents itself to the computer system as a virtual disk drive that implements the commands of consumer-level storage hardware that are familiar to the host controller of the computer system. Similarly, the storage device interface of the advanced storage system presents itself to one or more disk drives as a consumer-level host controller, regardless of the actual topology of the physical storage devices that are connected. This system provides a simple way for a user to combine low-cost, consumer-level hardware to add advanced storage features to a computer system. | 02-27-2014 |
20140032619 | NETWORK REPOSITORY FOR METADATA - A method and apparatus for a network repository for metadata. Embodiments of a data repository include a memory to store data including one or more data content items, where each data content item is associated with zero or more metadata items, and where each data content item is associated with a handle and each metadata item is associated with an attribute name. The data repository further includes a network interface configured to communicate with a client device, and a control unit configured to control the storage of data in the memory, where the control unit provides functions for writing data to and reading data from the memory and where the control unit is to transfer the data without interpretation. | 01-30-2014 |
20140026006 | MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS - A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. | 01-23-2014 |
20140019653 | TRANSMISSION OF MULTIPLE PROTOCOL DATA ELEMENTS VIA A CONNECTOR UTILIZING A DATA TUNNEL - Embodiments of the invention are generally directed to transmission of multiple protocol data elements via an interface utilizing a data tunnel over a control channel. An embodiment of an apparatus includes a transmitter or receiver for the transmission or reception of data; a processing element for handling the data of the apparatus; and a connector for the transfer of the data, the connector to connect to a data channel and to connect to a control channel. The processing element is to provide for transfer of data of a first protocol in the control channel, the transfer of data via the control channel including the use of one or more generic commands of the first protocol for the transfer of data of a second protocol. Data of the second protocol is optimized before the data of the second protocol is sent over the first protocol, and the data transfer in the data channel and data transfer in the control channel are simultaneous at least in part. | 01-16-2014 |
20130336334 | MULTIPLE PROTOCOL TUNNELING USING TIME DIVISION OPERATIONS - Embodiments of the invention are generally directed to multiple protocol tunneling using time division operations. An embodiment of an apparatus includes an interface for communication with a second apparatus, the interface including a shared communication link; and a multiplexer to multiplex data of each of multiple protocols into time slots for transmission, the protocols including a first protocol. The time slots are distributed among the protocols, where the distribution of the time slots among the protocols includes assigning one or more time slots to the first protocol to enable the data of the first protocol to meet one or more performance requirements for the first protocol. | 12-19-2013 |
20130329828 | SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL - Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel. | 12-12-2013 |
20130326030 | DISCOVERY OF ELECTRONIC DEVICES IN A COMBINED NETWORK - Embodiments of the invention are generally directed to discovery of electronic devices in a combined network. An embodiment of a method includes determining an identifier for a first device in a combined network according to a first network protocol, the combined network including a first network using the first network protocol and a second network using a second network protocol, where the identifier is determined based on a unique designation for the first device, and determining addressing information for the first device according to the second network protocol, where determining the addressing information includes establishing a physical address and a logical address for the first device. The method further includes broadcasting one or more messages containing identification information and capabilities of the first device to devices in the first network and to devices in the second network. The first device records and processes information from messages received by the first device, the messages being one or more messages under the first network protocol and one or more message under the second network protocol. | 12-05-2013 |
20130322778 | BLOCK NOISE DETECTION AND FILTERING - Systems and methods for block noise detection and filtering are disclosed. One embodiment includes, computing difference magnitudes in pixel values for adjacent pixels in the image. The difference magnitudes can include horizontal difference magnitudes for horizontally adjacent pixels and vertical difference magnitudes for vertically adjacent pixels. One embodiment further includes using normalized sums of the difference magnitudes to determine a set of noise characteristics of the block noise and a set of image characteristics of the image and configuring inputs to the block noise filter using the set of noise and image characteristics. | 12-05-2013 |
20130212309 | COMMUNICATION BRIDGING BETWEEN DEVICES VIA MULTIPLE BRIDGE ELEMENTS - Embodiments of the invention are generally directed to communication bridging between devices via multiple bridge elements. An embodiment of an apparatus includes a transmitter element to transmit data, and multiple bridge elements, the bridge elements including a first bridge element to receive data from the transmitter element and a second bridge element to provide data to a receiver. The bridge elements provide for one or more of translation of one or more commands for an operation from the transmitter element, wherein translation of commands includes handling of a command intended for the receiver, and pre-fetching of one or more data for the operation from the receiver. | 08-15-2013 |
20130191872 | VIDEO MANAGEMENT AND CONTROL IN HOME MULTIMEDIA NETWORK - A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link. | 07-25-2013 |
20130173974 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 07-04-2013 |
20130162901 | RINGING SUPPRESSION IN VIDEO SCALERS - Embodiments are generally directed to ringing suppression in video scalers. An embodiment of a method includes receiving a stream of video data, received video data including sets of video data values, and storing a first set of video data values in a memory. A first set of scaled values for the set of video data values is determined based on a scaling technology, and a second set based on linear interpolation. The method includes detecting rate of change in amplitude for received video data, generating a mixing control signal based at least in part on the rate of change, mixing first set of scaled values and second set of scaled values based at least in part on mixing control signal to generate blended set of coefficients, and generating scaled video data output using the set of blended values. | 06-27-2013 |
20130089202 | IDENTIFICATION AND HANDLING OF DATA STREAMS USING CODED PREAMBLES - Embodiments of the invention are generally directed to identification and handling of data streams using coded preambles. An embodiment of an apparatus includes an interface with a communication channel, transmitter coupled with the interface to transmit one or more data streams via the interface, and a processing element, the processing element to receive one or more data streams for transmission. Upon receiving multiple data streams for transmission of a first type of data, including a first data stream and a second data stream for transmission of the first type of data, the processing element is to select a first preamble for the first data stream and a second preamble for the second data stream, where the first preamble is distinguishable from the second preamble. | 04-11-2013 |
20120314753 | Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer - An adjustable equalizer that includes a first branch including a low pass filter (LPF) typically having a variable gain (β), and a second branch including a high pass filter (HPF) typically having another variable gain (α). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology and can be capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver. | 12-13-2012 |
20120296955 | AUTOMATED SERVICE DISCOVERY AND DYNAMIC CONNECTION MANAGEMENT - In some embodiments, an apparatus includes device functional circuitry to perform at least one service; and network interface control circuitry to control interaction between the apparatus and a network. The network interface control circuitry includes a service discovery module to (1) send a presence announcement message to be transmitted outside the device to let other devices outside the device know of services the device may perform and (2) to receive presence announcement messages from the other devices outside the device to learn what services to the other devices may perform. In some embodiments, the network interface control circuitry includes a dynamic connection management module. Other embodiments are described and claimed. | 11-22-2012 |
20120257699 | ADJUSTMENT OF CLOCK SIGNALS REGENERATED FROM A DATA STREAM - Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time. | 10-11-2012 |
20120236949 | CONVERSION OF MULTIMEDIA DATA STREAMS FOR USE BY CONNECTED DEVICES - Embodiments of the invention are generally directed to conversion of multimedia data streams for use by connected devices. An embodiment of a method for processing data includes receiving a data stream in a first multimedia data format at a first device, and inserting a replacement video portion into the received data stream to generate a modified multimedia data stream in a second multimedia data format. The modified data stream is provided to a second device coupled to the first device. | 09-20-2012 |
20120204048 | MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT - Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit. | 08-09-2012 |
20120188444 | CONVERSION AND PROCESSING OF DEEP COLOR VIDEO IN A SINGLE CLOCK DOMAIN - Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data. | 07-26-2012 |
20120173776 | ADAPTIVE INTERCONNECTION SCHEME FOR MULTIMEDIA DEVICES - Embodiments of the invention are generally directed to adaptive interconnection for multimedia devices. An embodiment of an apparatus includes an apparatus that includes one or more ports, the one or more ports including one or more adaptable ports, where each adaptable port includes a receptacle to accept a plug of a connector element, the receptacle including multiple electrical contacts. The apparatus further includes an adaptable port device to process data including multimedia data received at the one or more adaptable ports, where the adaptable port device is to detect a multimedia signal format for multimedia data received at each of the adaptable ports, and adapt each of the adaptable ports to be compatible with the detected multimedia signal format for the adaptable port. | 07-05-2012 |
20120158346 | IDDQ TESTING OF CMOS DEVICES - IDDQ testing of CMOS devices. An embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS (Complementary Metal-Oxide Semiconductor) transistors, and obtaining current measurements for the device, each of the current measurements being a measurement of a current after applying an input of the test pattern to the device. A filter function is applied to the current measurements, applying the filter function including separating defect current values from the current measurements. The method further includes determining whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value. | 06-21-2012 |
20120147271 | MULTIMEDIA I/O SYSTEM ARCHITECTURE FOR ADVANCED DIGITAL TELEVISION - Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip. | 06-14-2012 |
20120131245 | TRANSFER OF CONTROL BUS SIGNALING ON PACKET-SWITCHED NETWORK - Embodiments of the invention are generally directed to transfer of control bus signaling on a packet-switched network. An embodiment of a method includes sending control signals from a first device on a first control bus, the control signals being sent according to an interface protocol, the control signals being intended for a second device. The method further includes detecting a current state of the first control bus, where the current state is a control signal value driven by the first device; inserting a control signal representing the current state of the control bus into a data packet; and transmitting the data packet to the second device via a packet-switched network. | 05-24-2012 |
20120131153 | DISCOVERY OF ELECTRONIC DEVICES IN A COMBINED NETWORK - Embodiments of the invention are generally directed to discovery of electronic devices in a combined network. An embodiment of a method includes determining an identifier for a first device in a combined network according to a first network protocol, the combined network including a first network using the first network protocol and a second network using a second network protocol, where the identifier is determined based on a unique designation for the first device, and determining addressing information for the first device according to the second network protocol, where determining the addressing information includes establishing a physical address and a logical address for the first device. The method further includes broadcasting one or more messages containing identification information and capabilities of the first device to devices in the first network and to devices in the second network. The first device records and processes information from messages received by the first device, the messages being one or more messages under the first network protocol and one or more message under the second network protocol. | 05-24-2012 |
20120092450 | COMBINING VIDEO DATA STREAMS OF DIFFERING DIMENSIONALITY FOR CONCURRENT DISPLAY - Embodiments of the invention are generally directed to combining video data streams of differing dimensionality for concurrent display. An embodiment of an apparatus includes an interface to receive multiple video data streams, a dimensionality of each video stream being either two-dimensional (2D) or three-dimensional (3D). The apparatus further includes a processing module to process a first video data stream as a main video image and one or more video data streams as video sub-images, the processing module including a video combiner to combine the main video data stream and the sub-video data streams to generate a combined video output. The processing module is configured to modify a dimensionality of each of the video sub-images to match a dimensionality of the main video image. | 04-19-2012 |
20120081138 | TESTING OF HIGH-SPEED INPUT-OUTPUT DEVICES - Embodiments of the invention are generally directed to testing of high-speed input-output devices. An embodiment of a high-speed input-output apparatus includes a transmitter and a receiver, and a loop-back connection from an output of the transmitter to an input of the receiver, the loop-back connection including a first connector and a second connector for transmission of differential signals. The apparatus further includes a first inductor having a first terminal and a second terminal and second inductor having a first terminal and a second terminal, the first terminal of the first inductor being connected to the first connector and the first terminal of the second inductor being connected to the second connector, the second terminal of the first inductor and the second terminal of the second inductor providing a test access port for direct current testing of the apparatus. | 04-05-2012 |
20120026157 | MULTI-VIEW DISPLAY SYSTEM - Embodiments of the invention are generally directed to a multi-view display system. An embodiment of an apparatus includes a display screen to display multiple views simultaneously, and a controller to control the views presented on the display screen. The apparatus is configurable by the controller to provide multiple view settings, the view settings including a first setting in which the apparatus provides a single view to each viewer of the display screen and a second setting in which the apparatus provides a first view to a first viewer of the display screen and a second view to a second viewer of the display screen. A first filtering element filters views presented to viewers of the display screen such that an intended view is displayed to one or more viewers. | 02-02-2012 |
20110249179 | EDGE DETECTION - A technique for deinterlacing an interlaced video stream is disclosed. A embodiment of a method includes calculating a pixel using edge detection, calculating a pixel using vertical interpolation, calculating a pixel using weaving, calculating a confidence level, calculating a motion value, blending the edge pixel calculation with the vertical interpolation calculation to generate a first output pixel calculation, the blending being based on the confidence level, and blending the first output pixel calculation with the weaving calculation to generate a second output pixel calculation, the blending being based on the motion value. | 10-13-2011 |
20110209027 | ERROR DETECTION IN PHYSICAL INTERFACES FOR POINT-TO-POINT COMMUNICATIONS BETWEEN INTEGRATED CIRCUITS - An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports. | 08-25-2011 |
20110193579 | DETERMINATION OF PHYSICAL CONNECTIVITY STATUS OF DEVICES BASED ON ELECTRICAL MEASUREMENT - Embodiments of the invention are generally directed to determination of physical connectivity status of devices based on electrical measurement. An embodiment of a method includes discovering a connection of a first device with a second device, and performing an electrical measurement of the second device by the first device via the connection between the first device and the second device, where performing the electrical measurement includes sensing by the first device of an element of the second device. The method further includes, if the sensing by the first device fails to detect the element of the second device and a predetermined condition for the electrical measurement is enabled, then determining by the first device that the connection with the second device has been lost. | 08-11-2011 |
20110170011 | TRANSMISSION AND DETECTION OF MULTI-CHANNEL SIGNALS IN REDUCED CHANNEL FORMAT - Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency. | 07-14-2011 |
20110150006 | DE-ENCAPSULATION OF DATA STREAMS INTO MULTIPLE LINKS - Embodiments of the invention are generally directed to de-encapsulation of data streams into multiple links. An embodiment of a method includes receiving a data stream including multiple data frames, the data stream being in a first mode having a multiple channels of content data including a first channel sent in a first position in each data frame and a second channel sent in a second position in each data frame following the first position, with each data frame including a synchronization signal to indicate a start of the content data. The method further includes transforming the data stream into data sub-streams in a second mode, the data sub-streams including a first data sub-stream to carry data for the first channel in the second mode and a second data sub-stream to carry data for the second channel in the second mode. Transforming the data stream into in the plurality of data sub-streams includes generating the first data sub-stream by stripping the second channel from each frame of data, and generating the second data sub-stream by stripping the first channel and the synchronization signal from each frame and inserting a substitute synchronization signal before the second channel data in each data frame. The method further includes transmitting the first data sub-stream via a first link in the second mode and the second data sub-stream via a second link in the second mode. | 06-23-2011 |
20110149032 | TRANSMISSION AND HANDLING OF THREE-DIMENSIONAL VIDEO CONTENT - Embodiments of the invention are generally directed to transmission and handling of three-dimensional video content. An embodiment of a method includes receiving a multimedia data stream including video data utilizing an interface protocol and determining that the received video data includes three-dimensional (3D) video data, where each frame of the video data includes a first vertical synchronization (Vsync) signal prior to an active data region, the active data region including a first data region and a second data region. The method further includes converting the 3D video data from a 3D data format to a two-dimensional (2D) video format, where converting the 3D video data includes identifying a region between the first data region and the second data region, inserting a second Vsync signal between the first data region and the second data region, and providing an identifier to distinguish between the first data region and the second data region. | 06-23-2011 |
20100142419 | BI-DIRECTIONAL BRIDGE CIRCUIT HAVING HIGH COMMON MODE REJECTION AND HIGH INPUT SENSITIVITY - A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver. | 06-10-2010 |
20090274218 | Method and System for Transmitting or Receiving N-Bit Video Data over a Serial Link - A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system. | 11-05-2009 |
20090150621 | BANK SHARING AND REFRESH IN A SHARED MULTI-PORT MEMORY DEVICE - A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory. | 06-11-2009 |
20080235526 | POWER-SAVING CLOCKING TECHNIQUE - A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit. | 09-25-2008 |