SILEX MICROSYSTEMS AB Patent applications |
Patent application number | Title | Published |
20150076677 | CTE MATCHED INTERPOSER AND METHOD OF MAKING - The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1. | 03-19-2015 |
20150054136 | METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE - A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 μm. | 02-26-2015 |
20140378804 | INSULATION OF MICRO STRUCTURES - A method of providing a metal coating on a substrate ( | 12-25-2014 |
20140346657 | THIN FILM CAPPING - A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material. | 11-27-2014 |
20140063580 | VIA STRUCTURE AND METHOD THEREOF - A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro- mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided. | 03-06-2014 |
20140042498 | STARTING SUBSTRATE FOR SEMICONDUCTOR ENGINEERING HAVING SUBSTRATE-THROUGH CONNECTIONS AND A METHOD FOR MAKING SAME - A substrate-through electrical connection ( | 02-13-2014 |
20120292736 | BARRIER STRUCTURE - A starting substrate in the form of a semiconductor wafer ( | 11-22-2012 |
20120288422 | GLASS MICRO FLUIDIC DEVICE - A method of making a microfluidic device, includes: providing an optically transparent bottom substrate and an optically transparent top substrate, each made of glass. Recesses are made in the top substrate and the top and bottom substrates are bonded together. Then, material is removed from the top substrate to expose the recesses, and a lid is attached to the top substrate so as to cover the recesses whereby channels are formed. At least that surface of the lid facing towards the recesses in the top substrate has a surface roughness of <5 nm, preferably <2 nm. A microfluidic device, including a body of an optically transparent material, and at least one channel extending inside the body, the channels having a bottom surface, a top surface and side walls is also described. The top and bottom surfaces both exhibit surface a roughness <5 nm, preferably <2 nm. | 11-15-2012 |
20120267773 | Functional Capping - A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices. | 10-25-2012 |
20120126392 | Methods for Making Micro Needles and Applications Thereof - The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry. | 05-24-2012 |
20120112335 | NOVEL BONDING PROCESS AND BONDED STRUCTURES - A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described. | 05-10-2012 |
20120097733 | NOVEL BONDING PROCESS AND BONDED STRUCTURES - A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described. | 04-26-2012 |
20120076715 | NOVEL BONDING PROCESS AND BONDED STRUCTURES - A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described. | 03-29-2012 |
20120019886 | VIA STRUCTURE AND METHOD THEREOF - A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided. | 01-26-2012 |
20120018898 | VIA STRUCTURE AND METHOD THEREOF - The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided. | 01-26-2012 |
20120018852 | VIA STRUCTURE AND METHOD THEREOF - A vent hole precursor structure ( | 01-26-2012 |
20100053922 | MICROPACKAGING METHOD AND DEVICES - A method of micro-packaging a component wherein at least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of the substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. A micro-packaged electronic or micromechanic device, including a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing is also disclosed. An electronic or micromechanic component is attached to the electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box. | 03-04-2010 |
20100052107 | VIAS AND METHOD OF MAKING - The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias. | 03-04-2010 |
20090302414 | TRENCH ISOLATION FOR REDUCED CROSS TALK - A starting substrate in the form of a semiconductor wafer ( | 12-10-2009 |
20080308884 | Fabrication of Inlet and Outlet Connections for Microfluidic Chips - A method of making a fluid communication channel between a micro mechanical structure provided on a front side of a device and the back side of said device is described. It includes making the required structural components by lithographic and etching processes on said front side. Holes are then drilled from the back side of said device in precise alignment with the structures on said front side, to provide inlets and/or outlets to and/or from the micromechanical structure. | 12-18-2008 |