SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD Patent applications |
Patent application number | Title | Published |
20150207312 | Low Capacitance Transient Voltage Suppressor - A low capacitance transient voltage suppressor is disclosed. The transient voltage suppressor comprises a first diode with a first anode thereof coupled to an I/O port. A first cathode of the first diode and a second cathode of a second diode are respectively coupled to two ends of a resistor. A second anode of the second diode is coupled to a low-voltage terminal. A third anode and a third cathode of a third diode are respectively coupled to the second cathode and the resistor. The third diode induces a third parasitic capacitance smaller than a first capacitance of the first diode and a second parasitic capacitance of the second diode, and the third parasitic capacitance in series with the first and second parasitic capacitances dominate a small capacitance in a path during normal operation. | 07-23-2015 |
20140355312 | ISOLATED POWER SUPPLY, CONTROL SIGNAL TRANSMISSION CIRCUIT AND METHOD THEREOF - In one embodiment, method of generating a control signal for an isolated power supply, can include: (i) generating a first ground noise component with a first predetermined proportionality to a ground noise signal; (ii) generating a first peak signal based on a first control signal having the ground noise signal, where the first peak signal comprises a second ground noise component with a second predetermined proportionality to the ground noise signal; (iii) generating a second control signal based on a difference between the first peak signal and the first ground noise component; and (iv) controlling, by the second control signal, a switch of the isolated power supply. | 12-04-2014 |
20140354166 | DIMMING CIRCUIT AND METHOD FOR LEDS - The present disclosure relates to dimming circuit and method for LEDs. The dimming circuit obtains a DC voltage from an external AC power supply by using a TRIAC, an electronic transformer, and a rectifier bridge sequentially. The dimming circuit comprises a first power stage circuit, a second power stage, a first control circuit, and a second control circuit. The first power stage circuit has an input terminal configured to receive the DC voltage. The second power stage has an input terminal coupled to an output terminal of the first power stage and an output terminal coupled to an LED load. The first control circuit is configured to generate a first control signal in accordance with a first output voltage generated at the output terminal of the first power stage circuit, a first reference voltage and an upper threshold voltage to maintain an average value of the first output voltage to be consistent with the first reference voltage. The second control circuit is configured to generate a dimming signal in accordance with a first current and the first output voltage to control an operation of the second power stage circuit to maintain an output current of the second power stage circuit to be consistent with an expected driving current represented by the dimming signal. The first current is no less than a holding current of the electronic transformer. An input current of the first power stage circuit is maintained to be consistent with the first current by the first control signal when the first output voltage is in a continuously increasing state and is lower than the upper threshold voltage. The first output voltage decreases continuously and the input current is maintained to be consistent with a second current after the first output voltage reaches the upper threshold voltage. | 12-04-2014 |
20140346598 | HIGH VOLTAGE PMOS (HVPMOS) TRANSISTOR WITH A COMPOSITE DRIFT REGION AND MANUFACTURE METHOD THEREOF - In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well. | 11-27-2014 |
20140334205 | SYNCHRONOUS RECTIFICATION CONTROLLING CIRCUIT AND SYNCHRONOUS RECTIFICATION CONTROLLING METHOD - In one embodiment, a synchronous rectification circuit can include: (i) a sampling circuit configured to sample a voltage across first and second power terminals of a synchronous rectifier, and to generate a first sampling voltage; (ii) an enable controlling circuit configured to delay the first sampling voltage, and to generate a second sampling voltage, and to activate a ramp voltage when the first sampling voltage is higher than the second sampling voltage; (iii) the enable controlling circuit being configured to generate an enable controlling signal in response to a comparison of the ramp voltage against a reference voltage that represents a predetermined light load condition; and (iv) a driving circuit configured to activate a driving signal to turn on the synchronous rectifier when the enable controlling signal and a synchronous rectification open signal are active. | 11-13-2014 |
20140313786 | CONTROLLING CIRCUIT AND AC/DC CONVERTER THEREOF - In one embodiment, a controlling circuit configured for an AC/DC converter that receives an AC voltage supply, can include: (i) a compensation signal generator configured to generate a compensation signal that follows an error between an output signal from the AC/DC converter and an expected converter output signal during a first time interval of a half period of the AC voltage supply, the compensation signal being substantially constant during a remaining time interval of the half period; and (ii) a controlling signal generator configured to generate a controlling signal based on the compensation signal to maintain the output signal as substantially consistent with the expected converter output signal. | 10-23-2014 |
20140307486 | CAPACITOR DISCHARGING METHOD AND DISCHARGING CIRCUIT THEREOF - In one embodiment, a method of controlling a capacitor discharge for a switching power supply, can include: (i) generating a first voltage signal from a voltage at an X capacitor that is coupled between input terminals of the switching power supply; (ii) activating a detection signal in response to the first voltage signal being inactive for a duration of a predetermined time interval, where the detection signal being activated indicates a cut-off of the input terminals; and (iii) at least partially discharging the X capacitor after the cut-off and in response to activation of the detection signal. | 10-16-2014 |
20140307485 | TRANSMISSION VOLTAGE LOSS COMPENSATION CIRCUIT, COMPENSATION METHOD, CONTROLLING CHIP AND SWITCHING POWER SUPPLY - In one embodiment, a method of compensating for transmission voltage loss from a switching power supply, can include: (i) receiving a sampling signal that represents an output current of the switching power supply; (ii) delaying the sampling signal to generate a delayed sampling signal; (iii) converting the delayed sampling signal to generate a compensation signal; and (iv) regulating an output voltage of the switching power supply based on the compensation signal to compensate for the transmission voltage loss from the output voltage transmission to a load such that a voltage at the load is maintained as substantially consistent with an expected voltage at the load. | 10-16-2014 |
20140306677 | CURRENT DETECTION CIRCUIT AND SWITCHING REGULATOR THEREOF - In one embodiment, a current detection circuit configured for a switching regulator can include: (i) a feedback controlling circuit configured to control a feedback signal to be consistent with a reference signal, and to generate a feedback control signal; and (ii) a feedback signal generator configured to receive a rise time and a fall time of inductor current of the switching regulator, and to generate the feedback signal in direct proportion with the feedback control signal. | 10-16-2014 |
20140306318 | TRENCH FORMATION METHOD AND A SEMICONDUCTOR STRUCTURE THEREOF - In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about 400 nm; and (iii) using the patterned hard mask layer as a mask, and etching the semiconductor substrate to form the trench in the semiconductor substrate. | 10-16-2014 |
20140300333 | CURRENT DETECTION CIRCUIT AND SWITCH REGULATOR USING THE SAME - In one embodiment, a current detection circuit configured to determine an input current and an output current of a switching regulator, can include: (i) a mirror circuit configured to mirror a current flowing through a main power transistor of the switching regulator to generate a sampling signal that is in proportion to the main power transistor current; (ii) a current generating circuit configured to perform a first average value calculation of the sampling signal based on a switching cycle of the switching regulator to determine the input current; and (iii) the current generating circuit being configured to perform a second average value calculation of the sampling signal based on a conduction duty cycle of the main power transistor to determine the output current. | 10-09-2014 |
20140286058 | UNDERVOLTAGE PROTECTION CIRCUIT, UNDERVOLTAGE PROTECTION METHOD AND SWITCHING POWER SUPPLY - In one embodiment, an undervoltage protection circuit for a switching power supply can include: (i) an undervoltage detection circuit that determines whether an input voltage of the switching power supply is in an undervoltage state; (ii) a selection circuit configured to select a first or a second control signal to be provided as a main control signal to a control circuit; (iii) the control circuit being configured, in response to the main control signal being the first control signal, to control a switching operation of a power transistor in the switching power supply such that an output voltage of the switching power supply is maintained as substantially stable; and (iv) the control circuit being configured, in response to the main control signal being the second control signal, to control the switching operation of the power transistor to reduce an input power of the switching power supply. | 09-25-2014 |
20140285110 | HIGH-EFFICIENCY BIAS VOLTAGE GENERATING CIRCUIT - Disclosed are bias voltage generating circuits and methods for a switching power supply. In one embodiment, a switching power supply can include: (i) a driver circuit configured to receive a bias voltage, and to drive a switch in a power stage of the switching power supply; (ii) where a ratio of an output voltage of the switching power supply to an expected bias voltage of the driver circuit is configured as a proportionality coefficient; (iii) a bias voltage generating circuit configured to generate the bias voltage for the driver circuit based on a first voltage; and (iv) an H-shaped inductor coupled to an input of the bias voltage generating circuit, where the first voltage is configured to be generated based on a number of turns of the H-shaped inductor and the proportionality coefficient. | 09-25-2014 |
20140284703 | VERTICAL DOUBLE-DIFFUSION MOS AND MANUFACTURING TECHNIQUE FOR THE SAME - In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii) injecting and diffusing a first dopant into the active region to form a doping region; (iii) forming a gate oxide layer on the active region; (iv) depositing polysilicon on the gate oxide layer, and etching the polysilicon to form a gate; (v) injecting a second dopant at an end of the gate to form a source, where the first and second dopants have opposite types; (vi) forming a contact hole adjacent to the gate, and injecting a third dopant into the contact hole, where the first and third dopants have a same type; (vii) depositing and etching aluminum on a chip surface; and (viii) coating the aluminum and chip surface with a passivation layer. | 09-25-2014 |
20140253098 | VOLTAGE PEAK DETECTION CIRCUIT AND DETECTION METHOD - In one embodiment, a voltage peak detection circuit can include: (i) a voltage coupling circuit configured to inductively couple an input inductor voltage of a switching power supply, and to generate a first voltage that represents a DC input voltage of the switching power supply; (ii) a voltage conversion circuit configured to receive the first voltage, and to generate a second voltage that is proportional to the first voltage; and (iii) a holding circuit configured to hold a peak of the second voltage to generate a peak voltage signal that represents peak information of the DC input voltage. | 09-11-2014 |
20140252554 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator. | 09-11-2014 |
20140252553 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures. | 09-11-2014 |
20140252456 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In one embodiment, a semiconductor device can include: (i) a first doped pillar region having a doping concentration that sequentially increases from bottom to top in a vertical direction; (ii) second doped pillar regions arranged on either side of the first doped pillar region in a horizontal direction; and (iii) where sidewalls of the second doped pillar regions form sides of an inverted trapezoidal structure. | 09-11-2014 |
20140246988 | CONTROLLING CIRCUIT FOR AN LED DRIVER AND CONTROLLING METHOD THEREOF - The present invention relates to a controlling circuit and controlling method for an LED driver implemented as a flyback topology. The controlling circuit may be at a primary side of a transformer of the LED driver, and include a sampling circuit, an on time sensing circuit of an output diode, a regulating signal generator, and a PWM controller. The sampling circuit may generate a sampling signal indicating output current by sampling at the primary transformer side. The on time sensing circuit can detect an on time of the output diode. The regulating signal generator can generate a regulating signal by regulating the sampling signal, a voltage reference, and the on time of the output diode. The PWM controller may generate a controlling signal to control operation of a switching device of the LED driver to maintain a substantially constant output current in accordance with the regulating signal. | 09-04-2014 |
20140246976 | CONTROLLING CIRCUIT FOR AN LED DRIVER AND CONTROLLING METHOD THEREOF - The present invention relates to a controlling circuit and controlling method for an LED driver implemented as a flyback topology. The controlling circuit may be at a primary side of a transformer of the LED driver, and include a sampling circuit, an on time sensing circuit of an output diode, a regulating signal generator, and a PWM controller. The sampling circuit may generate a sampling signal indicating output current by sampling at the primary transformer side. The on time sensing circuit can detect an on time of the output diode. The regulating signal generator can generate a regulating signal by regulating the sampling signal, a voltage reference, and the on time of the output diode. The PWM controller may generate a controlling signal to control operation of a switching device of the LED driver to maintain a substantially constant output current in accordance with the regulating signal. | 09-04-2014 |
20140239835 | SCR DIMMING CIRCUIT AND METHOD - The present invention relates to an SCR dimming circuit and method for regulating the luminance of an LED load. In one embodiment, an SCR dimming circuit can include: an SCR element that generates a lack-phase AC voltage based on a sinusoidal AC supply; a rectifier bridge that generates a lack-phase DC voltage based on the lack-phase AC voltage; a conduction angle generator that receives the lack-phase DC voltage, and generates a controlling signal representative of a conduction angle of the SCR element; and a dimming signal generator that generates a dimming signal to regulate luminance of the LED load, where the dimming signal generator receives the controlling signal, an adjustable signal, and a clamping voltage, an amplitude of a dimming phase angle range is selected by a fixed signal determined by the clamping voltage, and the dimming phase angle range may be shifted by regulating the adjustable signal. | 08-28-2014 |
20140232190 | MIXED MODE CONTROL FOR SWITCHING REGULATOR WITH FAST TRANSIENT RESPONSES - Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator controller can include: (i) a first feedback circuit for sensing an output of a switching regulator to compare against a regulation reference, and to generate a control signal suitable for matching the output of the switching regulator to the regulation reference during a steady state operation of the switching regulator; and (ii) a second feedback circuit for sensing a regulation difference between the output and the regulation reference, and to generate an adjustment signal in response to the regulation difference, where the adjustment signal adjusts the control signal under transient conditions to improve transient responses of said switching regulator. | 08-21-2014 |
20140210437 | EFFICIENT BOOST-BUCK CONVERTER AND CONTROL METHOD THEREOF - In one embodiment, a boost-buck converter can include: (i) first and second switches coupled in series between input and an output of the boost-buck converter; (ii) a first inductor coupled to the input and third and fourth switches, where the third switch is coupled to ground, and the fourth switch is coupled to the output; (iii) a second inductor coupled to the output and a common node of the first and second switches; and (iv) a control circuit configured to control switching of the first, second, third, and fourth switches according to the input and output voltages, such that the boost-buck converter operates in at least one of: a buck mode and a boost mode. | 07-31-2014 |
20140210353 | HIGH EFFICIENCY LED DRIVING CIRCUIT AND DRIVING METHOD - In one embodiment, an LED driving circuit can include: (i) a sense circuit configured to sense an inductor voltage, and to generate a sense voltage signal; (ii) a protection control circuit configured to activate a first protection control signal in response to a comparison of the sense voltage signal against a first reference voltage to indicate an LED device is in a first load state; (iii) the protection control circuit being configured to activate a second protection control signal in response to a comparison of the sense voltage signal against a second reference voltage to indicate the LED device is in a second load state; and (iv) a PWM control circuit configured to control a power switch according to the first protection control signal or the second protection control signal, based on the load state of the LED device. | 07-31-2014 |
20140207977 | USB DEVICE AND CONTROL METHOD THEREOF - In one embodiment, a universal serial bus (USB) device can include: (i) an interface module having a power supply port, a ground port, and first and second data ports, where the interface module is configured to connect to corresponding ports of a USB host at a USB interface; (ii) a property identification module coupled to the first and second data ports, where the property identification module is configured to determine properties of the USB interface; (iii) a data transmission module configured to exchange data between the USB device and the USB host according to the determined properties; and (iv) a charging module coupled to the power supply port and the ground port, where the charging module is configured to charge the USB device based on the determined properties. | 07-24-2014 |
20140203763 | STEP-UP BATTERY CHARGING MANAGEMENT SYSTEM AND CONTROL METHOD THEREOF - In one embodiment, a battery charger can include: (i) a step-up converter configured to generate an output signal by boosting a DC input voltage, where a threshold voltage is greater than the DC input voltage; (ii) a charging control circuit configured to receive the output signal from the step-up converter, and to control charging of a battery; (iii) the charging control circuit being configured to regulate the output signal to maintain a charging current for the battery charging as a trickle current when a battery voltage is less than the threshold voltage; and (iv) the charging control circuit being configured to charge the battery directly by the output signal when the battery voltage is greater than the threshold voltage. | 07-24-2014 |
20140203719 | MULTI-OUTPUT CURRENT-BALANCING CIRCUIT - The present invention relates to a multi-output current-balancing circuit, which in one embodiment can include: (i) a transformer having a primary winding and a plurality of secondary windings, where the primary winding receives an AC input current; (ii) a plurality of first and second rectifier circuits and a plurality of first current balancing components, where each of the first and second rectifier circuits and the first current balancing components is coupled to a corresponding secondary winding, where each the first current balancing component is configured for current balancing between each of the first and second rectifier circuits of the corresponding secondary winding; and (iii) at least one second current balancing component, where each second current balancing component is coupled to a pair of the second rectifier circuits that correspond to different secondary windings, where the second current balancing components are configured for current balancing between different the secondary windings. | 07-24-2014 |
20140198546 | MASTER-SLAVE INTERLEAVED BCM PFC CONTROLLER AND CONTROL METHOD THEREOF - The present invention relates to a master-slave interleaved BCM PFC controller for controlling a PFC circuit with master and slave channels. In one embodiment, the PFC controller can include: a master channel controller that generates a master channel control signal and an inverted master channel control signal; a first phase shifter that provides a first phase shift for the master channel control signal, and generates a delayed opening signal therefrom; a second phase shifter that provides a second phase shift for the inverted master channel control signal, and generates a delayed shutdown signal therefrom; a slave channel controller that receives the delayed opening signal, the delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and generates a slave channel control signal therefrom. | 07-17-2014 |
20140198540 | INTEGRATED SWITCH MODE POWER SUPPLY CONTROLLER AND SWITCH MODE POWER SUPPLY USING THE SAME - In one embodiment, an integrated switch mode power supply controller can include: a multiplexing pin that receives a detection voltage signal; a switch mode power supply that receives a DC input voltage, and operates in a switching cycle having first, second, and third time intervals; during the first time interval, the detection voltage signal is proportional to the DC input voltage, and a current compensation signal is generated according to the detection voltage signal to obtain a peak inductor current; during the second time interval, the detection voltage signal is proportional to an output voltage of the switch mode power supply, and a discharging duration of current through the inductor is determined based on the detection voltage signal; and during the third time interval, the detection voltage signal is proportional to a voltage across a power transistor of the switch mode power supply. | 07-17-2014 |
20140183975 | BROWNOUT RECOVERY CIRCUIT FOR BOOTSTRAP CAPACITOR AND SWITCH POWER SUPPLY CIRCUIT - In one embodiment, a brownout recovery circuit configured for a switch power supply circuit with a first switch, can include: (i) an under-voltage detection circuit that activates a detection signal when a bootstrap capacitor is not in an under-voltage state, and deactivates the detection signal when the bootstrap capacitor is in the under-voltage state; (ii) a logic circuit that generates a first control signal according to a main control signal from the switch power supply circuit and a second switch state; (iii) a first control circuit that generates a first switch signal according to the detection signal, and controls the first switch thereby; and (iv) a second control circuit that receives the first control signal, and generates a second switch signal to control the second switch thereby. | 07-03-2014 |
20140169043 | BIAS VOLTAGE GENERATING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF - Disclosed herein are bias voltage generating circuits configured for switching power supplies, and associated control methods. In one embodiment, a bias voltage generating circuit can include: (i) a first control circuit configured to compare a drain-source voltage of a switch against a bias voltage; (ii) a capacitor, with the bias voltage across the capacitor; (iii) a second control circuit configured to control the switch, and that is enabled when the bias voltage is at least as high as an expected bias voltage; (iv) the first control circuit being configured to control the capacitor to charge when the drain-source voltage of the switch is greater than the bias voltage; and (v) the bias voltage being less than an overvoltage protection voltage when the capacitor charges, and where the overvoltage protection voltage comprises a voltage that is a predetermined amount higher than the expected bias voltage. | 06-19-2014 |
20140167724 | SELF-POWERED SOURCE DRIVING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF - In one embodiment, a source driving circuit configured for a switching power circuit, can include: (i) a source transistor coupled between a source of a main power transistor and ground, where the source transistor can be controlled by a PWM control signal; (ii) the main power transistor being on when the source transistor is on and a gate-source voltage of the main power transistor exceeds a conduction threshold voltage; (iii) a source diode having an anode coupled to the main power transistor source, and a cathode coupled to a delay circuit and a power supply capacitor; and (iv) the delay circuit controlling the main power transistor to turn off a delay time after the source transistor is turned off, where the delay time allows charging of the power supply capacitor such that a voltage across the power supply capacitor is at least a level of a reference voltage. | 06-19-2014 |
20140167256 | FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF - Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer. | 06-19-2014 |
20140163910 | BATTERY POWER MEASURING METHOD, MEASURING DEVICE AND BATTERY-POWERED EQUIPMENT - Disclosed herein are various battery power measurement devices, methods, and related apparatuses. In one embodiment, a method of measuring a battery power can include: (i) detecting a voltage and a temperature at an output terminal of a battery; (ii) obtaining a first correction coefficient based on a battery open-circuit voltage at a previous sample time; (iii) obtaining a second correction coefficient based on the battery temperature; (iv) calculating a real-time battery open-circuit voltage by using the voltage at the output terminal of the battery, the first and second correction coefficients, the battery open-circuit voltage at the previous sample time, and a time interval between the previous sample time and a present sample time; and (v) converting the real-time battery open-circuit voltage into a battery power measurement for display. | 06-12-2014 |
20140159695 | SWITCH POWER SUPPLY CONTROLLER AND CONTROL METHOD - In one embodiment, a switch power supply controller can include: (i) a switch configured to operate in first and second states during each switch cycle; (ii) a switch time regulating circuit that compares a duration of the first state in a present switch cycle against an expected first state duration; (iii) the switch time regulating circuit decreasing a duration of the second state in the present switch cycle when the first state duration is greater than the expected first state duration, to decrease a first state duration for a next switch cycle; and (iv) the switch time regulating circuit being increasing the second state duration in the present switch cycle when the first state duration is less than the expected first state duration, to increase a first state duration for a next switch cycle. | 06-12-2014 |
20140159689 | CONSTANT TIME CONTROL METHOD, CONTROL CIRCUIT AND SWITCH REGULATOR USING THE SAME - In one embodiment, a method of controlling a switching regulator can include: obtaining a voltage feedback signal by detecting an output voltage; generating a triangle wave signal by detecting a current flowing through an inductor; generating a first control signal by superimposing the triangle wave signal and the voltage feedback signal; calculating an error between the voltage feedback signal and a first reference voltage, and compensating for the error to obtain a compensation signal; generating a second control signal by comparing the first control signal against the compensation signal; and controlling switching of a power switch in the switching regulator based on the second control signal and a constant time control signal, where an output signal of the switching regulator is maintained as substantially constant. | 06-12-2014 |
20140159605 | AC-DC POWER CONVERTER - In one embodiment, an AC-DC power converter can include: (i) a rectifier bridge and filter to convert an external AC voltage to a DC input voltage; (ii) a first energy storage element to store energy from the DC input voltage via a first current through a first conductive path when in a first operation mode; (iii) a second energy storage element configured to store energy from a second DC voltage via a second current through a second conductive path when in the first operation mode; (iv) a transistor configured to share the first and second conductive paths; (v) the first energy storage element releasing energy to a third energy storage element and a load through a third conductive path when in a second operation mode; and (vi) the second energy storage element releasing energy to the load through a fourth conductive path during the second operation mode. | 06-12-2014 |
20140159219 | MULTI-COMPONENT CHIP PACKAGING STRUCTURE - Disclosed herein are various chip packaging structures and arrangements. In one embodiment, a multiple-component chip packaging structure can include: (i) a first component arranged on a bottom layer; (ii) at least one second component arranged on the first component, where the at least one the second component is electrically connected to the first component by a plurality of protruding structures; (iii) at least one third component on the at least one second component; (iv) at least one extension structure arranged on at least one side of the at least one third component, where the at least one extension structure is configured to lead out electric polarities of the at least one third component; and (v) a plurality of bonding wires that electrically connect the at least one extension structure to the first component. | 06-12-2014 |
20140159218 | CHIP PACKAGING STRUCTURE OF A PLURALITY OF ASSEMBLIES - Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is electrically connected to the first assembly by a plurality of first protruding structures located under the second assembly; (iii) at least one third assembly located above the second assembly, where the third assembly is electrically connected to the first assembly by a plurality of second protruding structures located outside of the second assembly; and (iv) where a first portion of the third assembly and the plurality of second protruding structures form a bent structure substantially perpendicular to a second portion of the third assembly. | 06-12-2014 |
20140152239 | SELF-ADAPTIVE INPUT POWER CHARGER AND METHOD FOR CONTROLLING INPUT CURRENT OF CHARGER - Disclosed herein are circuits and methods for limiting a charger input current. In one embodiment, a self-adaptive input power charger for charging a battery, can include: (i) a power stage circuit configured to receive an external input power supply that supplies an input voltage and an input current to the charger; (ii) a comparison circuit configured to generate a comparison result indicating that the input power supply has entered a current-limiting state when the input voltage is less than a first reference voltage; (iii) a current regulation circuit configured to generate a first control signal in response to the comparison result; and (iv) a driving control circuit configured to limit the input current by the first control signal. | 06-05-2014 |
20140145679 | HIGH EFFICIENCY BI-DIRECTIONAL DC CONVERTER AND CONTROL METHOD THEREOF - Disclosed herein are bi-directional DC converter circuits and control methods. In one embodiment, a method of controlling a bi-directional DC converter, can include: (i) detecting whether there is an input power supply at an input port, where the bi-directional DC converter comprises a single magnetic element; (ii) operating the bi-directional DC converter in a first operation mode to charge a battery when the input power supply is detected at the input port; (iii) operating the bi-directional DC converter in a second operation mode to transfer power from the battery to an output port for a load when the input power supply is not detected at the input port; and (iv) transferring power through the single magnetic element in both the first operation mode and the second operation mode. | 05-29-2014 |
20140140105 | HIGH EFFICIENCY AND FAST RESPONSE AC-DC VOLTAGE CONVERTERS - The present invention discloses circuits and methods for high efficiency and fast response AC-DC voltage converters. In one embodiment, an AC-DC voltage converter can include: (i) a first stage voltage converter having an isolated topology with a power factor correction function, where the first stage voltage converter is configured to convert an AC input voltage to a series-connected N branches of first stage voltages, where N is a positive integer of at least two; (ii) a second stage voltage converter having a non-isolated topology, where the second stage voltage converter is configured to convert one of the N branches of the first stage voltages to a second stage voltage; and (iii) where the second stage voltage and a remaining of the N branches of the first stage voltages are configured to be series-connected and converted to a DC output voltage. | 05-22-2014 |
20140139196 | LOW-NOISE MULTI-OUTPUT POWER SUPPLY CIRCUIT AND CONTROL METHOD THEREOF - Disclosed herein are low-noise multi-output power supply circuits and methods. In one embodiment, a method of controlling a low-noise multi-output power supply circuit, can include: (i) detecting operation states of each of a plurality of switch mode power supplies; (ii) generating a frequency modulation signal to control an operating frequency of a switch mode power supply to be substantially equal to a main frequency signal when the switch mode power supply is detected to operate in a heavy-load steady state; and (iii) controlling the operating frequency of the switch mode power supply to be independent of the main frequency signal when the switch mode power supply is detected to operate in a light-load or a dynamic state. | 05-22-2014 |
20140139134 | REFERENCE VOLTAGE REGULATING METHOD AND CIRCUIT FOR CONSTANT CURRENT DRIVER - The present invention relates to reference voltage regulating methods and circuits for a constant current driver. In one embodiment, a method can include: setting a reference voltage circuit matching with a current output channel of a constant current source; setting a first resistor of the reference voltage circuit to follow an ideal equivalent resistor of the current output channel, and maintaining a proportion of the first resistor and the ideal equivalent resistor to be no less than a predetermined value M; setting a first current of the reference voltage circuit to follow an ideal output current of the current output channel, and maintaining a proportion of the first current and the ideal output current to be no less than 1/M; and setting a product of the first current and the first resistor to be a reference voltage of the reference voltage circuit. | 05-22-2014 |
20140139129 | THYRISTOR DIMMING CIRCUIT WITH LOSSLESS DISCHARGING CIRCUIT AND METHOD THEREOF - Thyristor dimming circuits and methods are disclosed herein. In one embodiment, a thyristor dimming circuit can include: (i) a thyristor and a rectifier bridge configured to receive a sinusoidal AC voltage, and to generate a phase-loss input voltage; (ii) a power stage circuit configured to have the phase-loss input voltage applied thereto, the power stage circuit having a main switch and being configured to drive a lamp load through electrical conversion; and (iii) a discharging circuit configured, during a first predetermined time interval, to control the main switch to operate with a fixed duty cycle at a fixed frequency, where the first predetermined time interval begins prior to an absolute value of the sinusoidal AC voltage being reduced to zero, the first predetermined time interval ending when the phase-loss input voltage is again applied to the power stage circuit. | 05-22-2014 |
20140132176 | HIGH-PRECISION LED CONTROL CIRCUIT, METHOD AND LED DRIVER THEREOF - In one embodiment, a light-emitting diode (LED) driver can include: (i) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal; (ii) a current control circuit configured to control an output current of the LED driver in response to the reference voltage signal; and (iii) the LED driver being configured to drive an LED load when the enable signal is active. | 05-15-2014 |
20140120661 | FLIP CHIP PACKAGING METHOD - Disclosed are various flip chip packaging methods. In one embodiment, a method can include: (i) arranging a plurality of pads on a chip; (ii) arranging a plurality of first connecting structures on the plurality of pads, where each of the first connecting structures comprises a first metal; (iii) arranging a plurality of second connecting structures on the plurality of first connecting structures, where each second connecting structure comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal; and (iv) flipping the chip with the first and second connecting structures and arranging corresponding of the second connecting structures on pads of a substrate to form electrical connection between the chip and the substrate via the first and second connecting structures. | 05-01-2014 |
20140117865 | AC/DC POWER CONVERTER - In one embodiment, an AC/DC power converter can include: a rectifier bridge and a filter capacitor for converting an external AC voltage to a half-sinusoid DC input voltage; a first storage component, where during each switching cycle in a first operation mode, a first path receives the half-sinusoid DC input voltage to store energy in the first storage component, and a first current through the first storage component increases; a second storage component, where a second path receives a second DC voltage to store energy in the second storage component, and a second current through the second storage component increases; and a third storage component, where in a second operation mode, the first current decreases to release energy from the first to the third storage component, where the second DC voltage includes a voltage across the third storage component through a third path. | 05-01-2014 |
20140117520 | LEAD FRAME AND FLIP PACKAGING DEVICE THEREOF - Disclosed are various lead frame and flip chip package structures. In one embodiment, a method can include: (i) a plurality of pins, wherein each of the plurality of pins includes an intermediate portion and an extension portion that are connected to each other; (ii) where the intermediate portion is located at an interior region of the lead frame, the intermediate portion extending to a first side edge of the lead frame; and (iii) where the extension portion is located at a peripheral region of the lead frame, the peripheral region being different than the first side edge. | 05-01-2014 |
20140112031 | CONTROL AND DRIVE CIRCUIT AND METHOD - Disclosed herein are control and drive circuits and methods for synchronous rectification switching power supply bias voltage generating circuits configured for a switching power supply. In one embodiment, a control and drive circuit can include: (i) a primary side switch controller configured to generate a primary side switch control signal; (ii) a logic circuit configured to generate a first control signal based on the primary side switch control signal; (iii) a converting circuit configured to generate a second control signal based on the first control signal; and (iv) a synchronous rectifier switch controller configured to generate a synchronous rectifier switch control signal based on the second control signal such that phases of the primary side switch control signal and the synchronous rectifier switch control signal are the same or inverse based on a topology of the synchronous rectification switching power supply. | 04-24-2014 |
20140103895 | COMPENSATION CIRCUIT AND SWITCHING POWER SUPPLY THEREOF - Disclosed are compensation circuits for a switching power supply. In one embodiment, a compensation circuit can include: (i) a transconductance amplifier configured to receive a reference signal and a feedback signal, and to generate an amplifier output signal according to a difference between the reference signal and the feedback signal; (ii) a switching circuit configured to receive the amplifier output signal, where the switching circuit is controllable by a control signal from a switch control circuit; and (iii) a charging circuit coupled to the switching circuit, where the charging circuit is configured to be charged by the amplifier output signal in response to the control signal, and to generate a compensation signal therefrom. | 04-17-2014 |
20140097542 | FLIP PACKAGING DEVICE - Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal. | 04-10-2014 |
20140078788 | SYNCHRONOUS RECTIFYING CONTROL METHOD AND CIRCUIT FOR ISOLATED SWITCHING POWER SUPPLY - Disclosed are synchronous rectifying control methods and circuits for an isolated switching power supply. In one embodiment, a method can include: (i) generating a ramp voltage based on a power terminal voltage, where the power terminal voltage includes a voltage between first and second power terminals of a synchronous rectifier in the isolated switching power supply; (ii) determining whether the power terminal voltage starts declining; (iii) comparing the ramp voltage to a threshold voltage when the power terminal voltage starts to decline, where the threshold voltage substantially matches a minimum conduction time of the synchronous rectifier; (iv) reducing the ramp voltage and controlling the synchronous rectifier in an off state when the ramp voltage is lower than the threshold voltage; and (v) reducing the ramp voltage and controlling the synchronous rectifier in on state when the ramp voltage is higher than the threshold voltage. | 03-20-2014 |
20140077867 | BIAS VOLTAGE GENERATING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF - Disclosed herein are bias voltage generating circuits configured for switching power supplies, and associated control methods. In one embodiment, a bias voltage generating circuit can include: (i) a first control circuit configured to compare a drain-source voltage of a switch against a bias voltage; (ii) a capacitor, with the bias voltage across the capacitor; (iii) a second control circuit configured to control the switch, and that is enabled when the bias voltage is at least as high as an expected bias voltage; (iv) the first control circuit being configured to control the capacitor to charge when the drain-source voltage of the switch is greater than the bias voltage; and (v) the bias voltage being less than an overvoltage protection voltage when the capacitor charges, and where the overvoltage protection voltage comprises a voltage that is a predetermined amount higher than the expected bias voltage. | 03-20-2014 |
20140070390 | MULTI-CHIP PACKAGING STRUCTURE AND METHOD - Disclosed are multi-chip packaging structures and methods. In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip comprises a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads configured to connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads configured to connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure. | 03-13-2014 |
20140070385 | FLIP-CHIP PACKAGE STRUCTURE AND METHOD FOR AN INTEGRATED SWITCHING POWER SUPPLY - Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB. | 03-13-2014 |
20140063861 | AC-DC VOLTAGE CONVERTER WITH LOW STANDBY POWER CONSUMPTION AND CONTROL METHOD THEREOF - Disclosed are AC-DC voltage converter circuits and methods for low standby power consumption. In one embodiment, a method can include: (i) detecting operating states of an input power supply, where the input power supply is received by a safety capacitor and provided to a switching power supply circuit after being rectified and filtered; (ii) removing a phantom load when the input power supply operates in a normal operating state; (iii) loading the phantom load when the input power supply operates in an under voltage lock out state; and (iv) when the input power supply operates in the under voltage lock out state, using energy stored in the safety capacitor to supply power to a load of the switching power supply circuit and the phantom load, and disabling a power stage circuit until a voltage of the safety capacitor is reduced to less than a safety threshold value. | 03-06-2014 |
20140056047 | HIGH-EFFICIENCY BIAS VOLTAGE GENERATING CIRCUIT - Disclosed are bias voltage generating circuits and methods for a switching power supply. In one embodiment, a switching power supply can include: (i) a driver circuit configured to receive a bias voltage, and to drive a switch in a power stage of the switching power supply; (ii) where a ratio of an output voltage of the switching power supply to an expected bias voltage of the driver circuit is configured as a proportionality coefficient; (iii) a bias voltage generating circuit configured to generate the bias voltage for the driver circuit based on a first voltage; and (iv) an H-shaped inductor coupled to an input of the bias voltage generating circuit, where the first voltage is configured to be generated based on a number of turns of the H-shaped inductor and the proportionality coefficient. | 02-27-2014 |
20140055168 | SOURCE-ELECTRODE DRIVING CONTROL CIRCUIT AND CONTROL METHOD THEREOF - Disclosed are driving control methods and circuits for quasi-resonant control of a main power switch of a switching power supply. In one embodiment, a driving control circuit can include: (i) a clamp circuit coupled to a gate of the main power switch, where the clamp circuit is configured to clamp a voltage of the gate to a clamping voltage that is greater than a threshold voltage of the main power switch; (ii) a valley voltage detection circuit configured to activate a valley control signal when a drain-source voltage of the main power switch is at a resonance valley level; and (iii) a source voltage control circuit configured to reduce a voltage of a source of the main power switch to turn on the main power switch in response to the valley control signal being activated. | 02-27-2014 |
20140032008 | HYBRID CONTROLLING AND DRIVING CIRCUIT AND METHOD THEREOF - Methods, circuits, apparatus, and systems related to a hybrid driving and controlling circuit are disclosed. In one embodiment, a hybrid driving and controlling circuit in a double power supply system includes first and second power supplies and at least one load, and the circuit can include: (i) a controller coupled to a hybrid switcher that enables energy transfer from the first and second power supplies; (ii) when a determined energy of the first power supply is sufficient, the controller can control the hybrid switcher to transfer energy from the first power supply to the second power supply; and (iii) when the determined energy of the first power supply is insufficient, the controller can control the hybrid switcher to transfer energy from the second power supply to the at least one load. | 01-30-2014 |
20140003096 | SYNCHRONOUS RECTIFICATION CONTROL CIRCUIT AND POWER SUPPLY THEREOF | 01-02-2014 |
20140002051 | ADAPTIVE CASCODE CIRCUIT USING MOS TRANSISTORS | 01-02-2014 |
20130342243 | POWER SWITCH DRIVING CIRCUITS AND POWER CONVERTERS THEREOF - In one embodiment, a power switch driving circuit can include: (i) an upper switch having a first power terminal coupled to a voltage source, and a second power terminal coupled to a driving signal; (ii) a lower switch having a first power terminal coupled to the driving signal, and a second power terminal coupled to a first voltage level, where the first voltage level is higher than a first ground potential; (iii) an upper switch driving sub circuit configured to receive a control signal, and to drive the upper switch in response thereto; and (iii) a lower switch driving sub circuit configured to receive the control signal, and to drive the lower switch in response thereto, where the upper and lower switch driving sub circuits are coupled to a second ground potential. | 12-26-2013 |
20130329463 | HIGH EFFICIENCY AND FAST RESPONSE AC-DC VOLTAGE CONVERTERS - The present invention discloses circuits and methods for high efficiency and fast response AC-DC voltage converters. In one embodiment, an AC-DC voltage converter can include: (i) a first stage voltage converter having an isolated topology with a power factor correction function, where the first stage voltage converter is configured to convert an AC input voltage to a series-connected N branches of first stage voltages, where N is a positive integer of at least two; (ii) a second stage voltage converter having a non-isolated topology, where the second stage voltage converter is configured to convert one of the N branches of the first stage voltages to a second stage voltage; and (iii) where the second stage voltage and a remaining of the N branches of the first stage voltages are configured to be series-connected and converted to a DC output voltage. | 12-12-2013 |
20130313989 | HIGH EFFICIENCY LED DRIVERS WITH HIGH POWER FACTOR - The present invention relates to a high efficiency, high power factor LED driver for driving an LED device. In one embodiment, an LED driver can include: an LED current detection circuit coupled to the LED device, and configured to generate a feedback signal that represents an error between a driving current and an expected driving current of the LED device; a power stage circuit, where a first power switch terminal is coupled to a first input voltage, and a second power switch terminal is coupled to ground; and a control circuit configured to generate a control signal according to the feedback signal and a drain-source voltage of the power switch, where the control signal, in each switch period, turns on the power switch when the drain-source voltage reaches a low level, and turns off the power switch after a fixed time interval based on the feedback signal. | 11-28-2013 |
20130313974 | LED DRIVER ADAPTED TO ELECTRONIC TRANSFORMER - Disclosed is an LED driver adapted to an electronic transformer, where the LED driver can ensure that the electronic transformer meets minimum load current requirements, and operates during an entire AC period by clamping the minimum inductor current. By controlling the LED load current through a current stabilization control circuit, the LED load can operate with relatively high control accuracy and fast response speed. In addition, the LED driver can match various electronic transformers based on traditional circuit structures, and the LED load can operate without flicking. | 11-28-2013 |
20130301309 | CONTROL CIRCUITS AND CONTROL METHODS FOR FLYBACK CONVERTERS AND AC-DC POWER CONVERTERS THEREOF - The present invention relates to control circuits and methods for a flyback converter and AC-DC power converters thereof. In one embodiment, a control circuit can include: (i) a turn-on signal generating circuit that is configured, in each switching cycle, to receive a drain-source voltage of a power switch of the flyback converter, and to activate a turn-on signal to turn on the power switch when the drain-source voltage reaches a valley value; (ii) a turn-off signal generating circuit that is configured, in each switching cycle, to activate a turn-off signal to turn off the power switch based on a power switch feedback error signal after a power switch conducting time interval has elapsed; and (iii) where input current and voltages of the flyback converter can be maintained as substantially in phase, and an output electrical signal of the flyback converter can be maintained as substantially constant. | 11-14-2013 |
20130300461 | POWER SWITCH DRIVING CIRCUITS AND SWITCHING MODE POWER SUPPLY CIRCUITS THEREOF - In one embodiment, a power switch driving circuit can include: (i) a first circuit configured receiving a control signal, and controlling a first transistor gate, where a first transistor source is coupled to a power supply, and a first transistor drain is coupled to a driving signal configured to control a power switch; (ii) a second circuit configured to receive the control signal, and to control a second transistor gate, where a second transistor source is coupled to ground, and a second transistor drain is coupled to the driving signal; and (iii) a driving enhancement circuit having a third transistor and a first inverter that is configured to invert an output of the first circuit to control a third transistor gate, where a third transistor source is coupled to the driving signal, and a third transistor drain is coupled to the power supply. | 11-14-2013 |
20130278239 | PRECHARGE CIRCUITS AND METHODS FOR DC-DC BOOST CONVERTERS - The present invention discloses precharge circuits and methods for DC-DC boost converters. In one embodiment, a precharge method for a DC-DC boost converter having a current mirror circuit that includes a reference transistor and a power transistor, can include: (i) maintaining a reference current flowing through the reference transistor as substantially constant; (ii) maintaining a drain-source voltage of the reference transistor and a drain-source voltage of the power transistor as substantially equal; and (iii) obtaining a substantially constant mirror current by reflecting the reference current through the power transistor to operate as a precharging current of a precharge circuit. | 10-24-2013 |
20130250629 | CONSTANT VOLTAGE CONSTANT CURRENT CONTROL CIRCUITS AND METHODS WITH IMPROVED LOAD REGULATION - The present invention discloses CVCC circuits and methods with improved load regulation for an SMPS. In one embodiment, the CVCC can include: a voltage feedback circuit to generate an output voltage feedback signal; a current feedback circuit to generate an output current feedback signal; a control signal generating circuit that receives the output voltage feedback signal and the output current feedback signal, and generates a constant voltage/constant current control signal; a first enable signal generating circuit that compares a first reference voltage and the constant voltage/constant current control signal to generate a first enable signal; and a PWM controller that generates a PWM control signal based on the constant voltage/constant current control signal to control a main switch of the flyback SMPS. | 09-26-2013 |
20130241461 | SINUSOIDAL MODULATION CONTROL METHODS AND CIRCUITS FOR PERMANENT MAGNET SYNCHRONOUS MOTORS - Disclosed herein are sinusoidal modulation control methods and circuits for PMSM. In one embodiment, a method can include: detecting rotor position information of the PMSM to obtain a rotor position signal and a rotor rotating speed measured value; comparing the rotating speed measured value against a reference rotating speed value to generate an error signal, and generating a first regulating voltage signal based on the error signal using a PI regulator; receiving the rotor position signal and the first regulating voltage signal, and generating a full-wave U-shaped modulation wave by using the rotor position signal as a time reference; generating a second U-shaped modulation wave by multiplying the full-wave U-shaped modulation wave with the first regulating voltage signal; comparing the second U-shaped modulation wave against a triangular wave to generate a PWM control signal that controls a switch of an inverter to regulate a current of the PMSM. | 09-19-2013 |
20130234612 | BLEND DIMMING CIRCUITS AND RELEVANT METHODS - The present disclosure relates to blend dimming circuits and methods for driving light loads. In one embodiment, a method can include: converting an external sinusoidal AC power supply to a phase-missing DC voltage signal; detecting a conduction angle of the phase-missing DC voltage signal to generate a first control signal representing the conduction angle; generating an analog dimming signal based on the first control signal; generating, by a PWM dimming circuit, a PWM dimming signal based on the analog dimming signal and a light load feedback signal; regulating light load brightness by PWM dimming when the conduction angle is greater than a threshold angle; regulating the light load brightness by PWM and analog dimming when the conduction angle is less than the threshold angle; and enabling a power stage circuit when the first control signal is active to regulate the brightness of the light load. | 09-12-2013 |
20130223119 | BOOST PFC CONTROLLER - The present invention pertains to a boost power factor correction (PFC) controller. In one embodiment, a boost PFC controller for an AC/DC converter can include: an off signal generator that compares an inductor current sample signal against a first control signal, where the inductor current sample signal increases during an on time of a power switch of the AC/DC converter, and the off signal generator generates an off signal when the inductor current sample signal reaches the first control signal level; and an on signal generator that compares a second control signal against a third control signal, where the second control signal increases during the off time of the power switch, and the on signal generator generates an on signal when the second control signal reaches the third control signal level. | 08-29-2013 |
20130223108 | CONSTANT VOLTAGE CONSTANT CURRENT CONTROLLER AND CONTROL METHOD THEREOF - The present invention relates to a constant voltage constant current (CVCC) controller, and associated control methods. In one embodiment, a CVCC controller for a flyback converter can include: (i) a current controller configured to generate an error signal by comparing an output current feedback signal against a reference current; (ii) a voltage controller configured to receive an output voltage feedback signal and a reference voltage, and to generate a control signal; (iii) a selector configured to control the flyback converter to operate in a first or a second operation mode based on the control signal, and to further generate a constant voltage or a constant current control signal based on the error signal; and (iv) a pulse-width modulation (PWM) controller configured to generate a PWM control signal to control a main switch, and to maintain the output voltage and/or current of the flyback converter as substantially constant. | 08-29-2013 |
20130207560 | MULTI-OUTPUT CURRENT-BALANCING CIRCUIT - The present invention relates to a multi-output current-balancing circuit, which in one embodiment can include: (i) a transformer having a primary winding and a plurality of secondary windings, where the primary winding receives an AC input current; (ii) a plurality of first and second rectifier circuits and a plurality of first current balancing components, where each of the first and second rectifier circuits and the first current balancing components is coupled to a corresponding secondary winding, where each the first current balancing component is configured for current balancing between each of the first and second rectifier circuits of the corresponding secondary winding; and (iii) at least one second current balancing component, where each second current balancing component is coupled to a pair of the second rectifier circuits that correspond to different secondary windings, where the second current balancing components are configured for current balancing between different the secondary windings. | 08-15-2013 |
20130181626 | HIGH EFFICIENCY LED DRIVER AND DRIVING METHOD THEREOF - The present invention relates to a high efficiency LED driver, and driving methods thereof. In one embodiment, a high efficiency LED driving method can include: (i) receiving an AC input voltage to obtain an absolute value thereof; (ii) receiving a DC bus voltage, and driving the LED device through a power switch; (iii) generating a first reference voltage according to a driving current and an expected driving current; (iv) comparing the absolute value against a sum of a driving voltage and the first reference voltage; (v) when the absolute value is greater than the sum of the driving voltage and the first reference voltage, turning off the power switch; and (vi) when the absolute value is greater than the driving voltage but less than the sum of the driving voltage and the first reference voltage, turning on the power switch to generate an output current. | 07-18-2013 |
20130181620 | MULTI-OUTPUT SELF-BALANCING POWER CIRCUIT - The present invention relates to a multi-output self-balancing power circuit. In one embodiment, a multi-output self-balancing power circuit can include: a transformer formed by a primary winding and n (e.g., greater than 2) series connected secondary windings; n output circuits corresponding to the n secondary windings, where each of the n output circuits can include a rectifier diode and a filter capacitor, and a load can be parallel coupled with the filter capacitor; n output circuits series coupled between a first output terminal of a first secondary winding and a second output terminal of an n | 07-18-2013 |
20130175936 | HIGH EFFICIENCY LED DRIVER AND DRIVING METHOD THEREOF - The present invention relates to a high efficiency LED driver and driving method thereof. In one embodiment, a high efficiency LED driving method configured for a LED device can include: (i) receiving a DC bus voltage and generating a driving voltage for the LED device through a power switch; (ii) comparing the DC bus voltage against a sum of the driving voltage and a first reference voltage; (iii) where when the DC bus voltage is greater than the sum of the driving voltage and the first reference voltage, generating a first output current; (iv) where when the DC bus voltage is greater than the driving voltage and less than the sum of the driving voltage and the first reference voltage, generating a second output current; and (v) matching an average current of the first output current and the second output current with a corresponding driving current. | 07-11-2013 |
20130163300 | BOOST POWER FACTOR CORRECTION CONTROLLER - The present invention relates to a power factor correction (PFC) controller. In one embodiment, a boost PFC controller configured in an AC/DC converter can include: (i) a conductive signal generator configured to receive a first sampling signal, and to generate a conductive signal according to the first sampling signal and a first control signal; (ii) a shutdown signal generator configured to compare a second control signal against a third control signal, and to generate a shutdown signal when the second control signal reaches a level of the third control signal; and (iii) a logic controller coupled to the conductive signal generator and the shutdown signal generator to control a switching state of a power switch in AC/DC converter. | 06-27-2013 |
20130154710 | ADAPTIVE CASCODE CIRCUIT USING MOS TRANSISTORS - The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors. | 06-20-2013 |
20130134568 | LEAD FRAME AND FLIP CHIP PACKAGE DEVICE THEREOF - The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps. | 05-30-2013 |
20130134567 | LEAD FRAME AND SEMICONDUCTOR PACKAGE STRUCTURE THEREOF - The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame. | 05-30-2013 |
20130127496 | DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF - Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. | 05-23-2013 |
20130107592 | REFERENCE VOLTAGE REGULATING METHOD AND CIRCUIT FOR CONSTANT CURRENT DRIVER | 05-02-2013 |
20130105938 | DEVICE MATCHING LAYOUT AND METHOD FOR IC | 05-02-2013 |
20130093406 | POWER REGULATOR AND CONTROLLING METHOD THEREOF - Methods and circuits related to power regulation are disclosed. In one embodiment, a power regulator for converting an input electrical signal to an output electrical signal to supply power to a load, can include: (i) a power stage having switching devices and a filter; (ii) a regulation signal generator for the switching devices that includes a feedback circuit and a PWM, the feedback circuit receiving an output signal from the power stage, the PWM receiving an output from the feedback circuit, and generating a PWM control signal; (iii) a constant time generator receiving the PWM control signal and generating a constant time signal based on the PWM control signal duty cycle; and (iv) a logic/driving circuit receiving the PWM control signal and the constant time signal, and controlling operation of the switching devices to modulate the output signal from the power stage, and maintaining a pseudo constant operation frequency. | 04-18-2013 |
20130063180 | MASTER-SLAVE INTERLEAVED BCM PFC CONTROLLER AND CONTROL METHOD THEREOF - The present invention relates to a master-slave interleaved BCM PFC controller for controlling a PFC circuit with master and slave channels. In one embodiment, the PFC controller can include: a master channel controller that generates a master channel control signal and an inverted master channel control signal; a first phase shifter that provides a first phase shift for the master channel control signal, and generates a delayed opening signal therefrom; a second phase shifter that provides a second phase shift for the inverted master channel control signal, and generates a delayed shutdown signal therefrom; a slave channel controller that receives the delayed opening signal, the delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and generates a slave channel control signal therefrom. | 03-14-2013 |
20130063102 | CONSTANT TIME CONTROLLER AND CONTROLLING METHOD FOR SWITCHING REGULATOR - The present invention relates to a constant time controller, controlling method thereof, and a switching regulator. In one embodiment, a controlling method for a switching regulator, can include: (i) detecting an output voltage and an inductor current of the switching regulator; (ii) determining if there is a transient change on a load of the switching regulator by using the output voltage and a first reference voltage; (iii) generating a control signal using the output voltage, the inductor current, and a second reference voltage; (iv) controlling a switch of the switching regulator to maintain the output voltage substantially constant when no transient change is determined on the load; and (v) deactivating the control signal to keep the inductor current changing along with a variation tendency of an output current of the switching regulator when a transient change is determined on the load. | 03-14-2013 |
20130009621 | LOW OFFSET, FAST RESPONSE VOLTAGE CONTROLLED CURRENT SOURCE AND CONTROLLING METHOD THEREOF - The present invention relates to a low offset and fast response voltage controlled current source, controlling method, and a power supply thereof. In one embodiment, a voltage controlled current source can include: a clock signal generator, a first operational amplifier, an input offset eliminator, a sampling and holding circuit, and an output circuit. The input offset eliminator can receive a clock signal, an input voltage, and a feedback voltage, and can (i) store and then eliminate an input offset of the first operation amplifier, and generate an error signal in accordance with an error between the input and feedback voltages when the clock signal is active, and (ii) generate the error signal in accordance with the stored input offset and the error between the input and feedback voltages when the clock signal is inactive. | 01-10-2013 |
20130009568 | HYBRID MULTI-OUTPUT POWER SUPPLY AND REGULATION METHOD THEREOF - The present invention relates to a hybrid multi-output power supply and regulation method thereof. In one embodiment, a power supply includes: a driving circuit that generates an error signal based on an expected driving voltage, the expected driving voltage being determined by an LED load driving current, and where the driving circuit regulates the driving current to be substantially constant and consistent with an expected driving current; a first stage voltage regulator receiving an input voltage and the error signal, and generating a first regulation voltage consistent with the expected driving voltage, where the first regulation voltage supplies power to the driving circuit, and provides driving voltage for the LED load, and where the first regulation voltage provides sufficient expected driving current; and a second stage voltage regulator that receives the first regulation voltage, and generates a substantially constant second regulation voltage to supply power to a first load. | 01-10-2013 |