SEOUL NATIONAL UNIVERSITY R&D FOUNDATION Patent applications |
Patent application number | Title | Published |
20150233810 | APPARATUS AND METHOD FOR MEASURING SURFACE TENSION - The present invention relates to an apparatus and method for measuring surface tension. More particularly, the present invention relates an apparatus and method for measuring surface tension through an electrical scheme which is simpler and has improved accuracy compared to a conventional optical scheme. | 08-20-2015 |
20130180344 | TRANSDUCER AND METHOD FOR MANUFACTURING SAME - The present invention relates to a transducer and a method for manufacturing same, and more particularly, to a transducer and to a method for manufacturing same, in which a first liquid and a second liquid are supplied such that, at the boundary therebetween, a deformation-generating part, including a perforated structure having one or more holes therein, is formed, and the effect of external pressure is negated by the action between the liquids. | 07-18-2013 |
20130057304 | CAPACITIVE ELEMENT SENSOR AND METHOD FOR MANUFACTURING SAME - The present disclosure relates to a capacitive element sensor and to a method for manufacturing same. More particularly, the present disclosure relates to a change in total capacitance brought about by the electrical charge of biomolecules attached to an electrode and to a sensor for measuring the change. | 03-07-2013 |
20120139584 | DOMINO LOGIC CIRCUITS AND PIPELINED DOMINO LOGIC CIRCUITS - A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node. | 06-07-2012 |