SANDISK CORPORATION Patent applications |
Patent application number | Title | Published |
20150179563 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first conductive line and a second conductive line including a first extension region in which the first conductive line and the second conductive line extend in a first direction, and a bend region in which the first conductive line and the second conductive line bend with respect to the first direction, a first dummy pattern and a second dummy pattern arranged on extension regions beyond the bend region of the first conductive line and the second conductive line, respectively, in the first direction, a first contact pad and a second contact pad formed beyond the bend region in the first direction, and connected to the first conductive line and the second conductive line, respectively. | 06-25-2015 |
20150078092 | Non-Volatile Semiconductor Memory Adapted to Store a Multi-Valued Data in a Single Memory Cell - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 03-19-2015 |
20150073743 | TEMPERATURE SENSOR - According to one embodiment, a temperature sensor includes: a voltage generating part generating (2 | 03-12-2015 |
20140206182 | METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS - Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided. | 07-24-2014 |
20140183613 | ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES - Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation. | 07-03-2014 |
20140133234 | FLASH EEPROM SYSTEM WITH SIMULTANEOUS MULTIPLE DATA SECTOR PROGRAMMING AND STORAGE OF PHYSICAL BLOCK CHARACTERISTICS IN OTHER DESIGNATED BLOCKS - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 05-15-2014 |
20140063976 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 03-06-2014 |
20140035011 | METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided. | 02-06-2014 |
20140017396 | COMPOSITIONS AND METHODS FOR MODULATION OF NANOSTRUCTURE ENERGY LEVELS - Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure, for reversibly modifying nanostructures, and for manipulating the electronic properties of nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures. Ligands of the present invention are also useful for manipulating the electronic properties of nanostructure compositions (e.g., by modulating energy levels, creating internal bias fields, reducing charge transfer or leakage, etc.). | 01-16-2014 |
20130138846 | ENHANCED DATA STORAGE DEVICE - A data storage device includes one or more data paths through electrical contacts of the data storage device. The data paths are operably connected to allow bits to be transferred into and out of the data storage device. The data storage device stores an indication of a number of the one or more data paths in a configuration register. A method includes performing, while the data storage device is operatively coupled to a host device, receiving a command of the host device to read the configuration register and providing the indication via at least one of the one or more data paths. Providing the indication enables indicating to the host device the number of the one or more data paths. | 05-30-2013 |
20120258387 | METHOD AND MASK FOR ENHANCING THE RESOLUTION OF PATTERNING 2-ROW HOLES - A photolithography mask including a plurality of mask features. Adjacent mask features are separated by a gap and are offset from each other such that individual mask features have one-side dense portions and two-side dense portions. Also a photolithography method that includes a step of providing a substantially opaque mask having N stepped rows of offset, substantially transparent, rectangular mask features, where N is an integer and N≧2. The method also includes illuminating a photoresist layer located over an underlying material with dipole illumination through the substantially transparent, rectangular mask features in the substantially opaque mask to form 2N rows of exposed regions in the photoresist layer. The exposed regions have a substantially elliptical or substantially circular shape when viewed from above the photoresist layer. | 10-11-2012 |
20120256247 | 3D Vertical NAND and Method of Making Thereof by Front and Back Side Processing - Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel. | 10-11-2012 |
20120236657 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 09-20-2012 |
20120204077 | DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA - A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data. | 08-09-2012 |
20120153376 | STACKED METAL FIN CELL - A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins. | 06-21-2012 |
20120110417 | HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS - A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data. | 05-03-2012 |
20120102379 | SYSTEM AND METHOD OF INTERLEAVING DATA ACCORDING TO AN ADJUSTABLE PARAMETER - A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells. | 04-26-2012 |
20120083124 | Method of Patterning NAND Strings Using Perpendicular SRAF - A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate. | 04-05-2012 |
20120023384 | SYSTEM AND METHOD OF DISTRIBUTIVE ECC PROCESSING - Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation. | 01-26-2012 |
20120001252 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120001250 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120001249 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120001247 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20110280076 | JUNCTIONLESS TFT NAND FLASH MEMORY - A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm. | 11-17-2011 |
20110246844 | Test Mode Soft Reset Circuitry and Methods - A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern. | 10-06-2011 |
20110185251 | SYSTEM AND METHOD TO CORRECT DATA ERRORS USING A STORED COUNT OF BIT VALUES - In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine. | 07-28-2011 |
20110154160 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array. | 06-23-2011 |
20110154158 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion. | 06-23-2011 |
20110151636 | Method For Angular Doping Of Source And Drain Regions For Odd And Even NAND Blocks - A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles. | 06-23-2011 |
20110141816 | Tracking Cells For A Memory System - Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined. | 06-16-2011 |
20110134694 | High Voltage Generation And Control In Source-Side Injection Programming Of Non-Volatile Memory - Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used. | 06-09-2011 |
20110131473 | Method For Decoding Data In Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads - Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. | 06-02-2011 |
20110122691 | POWER MANAGEMENT OF MEMORY SYSTEMS - A memory system that includes a memory array and a memory controller manages power consumption by maintaining a variable credit value that reflects the amount of power available to the memory system. The variable credit value may be increased periodically up to a limit. When a power-consuming operation is performed, the variable credit value is reduced to reflect the power used. | 05-26-2011 |
20110113158 | ENHANCED DATA STORAGE DEVICE - A data storage device includes one or more electrical contacts and one or more data paths through the electrical contacts. The one or more electrical contacts enable bits to be transferred into and out of the data storage device via the one or more data paths. The data storage device also includes a memory that stores an indication of a number of the one or more data paths. The data storage device is configured to provide the indication via at least one of the one or more data paths while the data storage device is operatively coupled to a host device to indicate to the host device the number of the one or more data paths. | 05-12-2011 |
20110090741 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 04-21-2011 |
20110072328 | NONVOLATILE MEMORY CONTROLLER WITH SCALABLE PIPELINED ERROR CORRECTION - A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface. | 03-24-2011 |
20110066772 | CONTROLLING ACCESS TO DIGITAL CONTENT - Method for utilizing digital content is provided. The method includes controlling a throughput rate for utilizing the digital content by an accessing system, where the throughput rate is associated with information related to the digital content and is stored as a file. The throughput rate is controlled by a storage system that is operationally coupled to the accessing system. | 03-17-2011 |
20110061096 | CONTROLLING ACCESS TO DIGITAL CONTENT - Method for utilizing digital content is provided. The method includes controlling a throughput rate for utilizing the digital content by an accessing system, where the throughput rate is associated with information related to the digital content and is stored as a file. The throughput rate is controlled by a storage system that is operationally coupled to the accessing system. | 03-10-2011 |
20110024897 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package. | 02-03-2011 |
20110024891 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package. | 02-03-2011 |
20100332949 | SYSTEM AND METHOD OF TRACKING ERROR DATA WITHIN A STORAGE DEVICE - Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison. | 12-30-2010 |
20100332943 | METHOD AND DEVICE FOR SELECTIVELY REFRESHING A REGION OF A NON-VOLATILE MEMORY OF A DATA STORAGE DEVICE - A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non-volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region. | 12-30-2010 |
20100332923 | SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY - Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold. | 12-30-2010 |
20100332728 | SYSTEM AND METHOD OF SELECTING A FILE PATH OF A REMOVABLE STORAGE DEVICE - Systems and methods of identifying a file path of a removable storage device are disclosed. A method includes, at a host device that is coupled to the removable storage device, selecting a file path that is associated with the removable storage device by accessing a size associated with a root directory accessible to the host device, where the root directory corresponds to the removable storage device. The file path is selected based upon the size associated with the root directory. The selected file path is verified by initiating a memory access operation using the selected file path. | 12-30-2010 |
20100328493 | REMOVABLE DATA STORAGE DEVICE WITH INTERFACE TO RECEIVE IMAGE CONTENT FROM A CAMERA - Systems and methods of receiving image content in a first format and storing converted image content in a second format are disclosed. A method includes receiving image content in a first format from a camera at an interface of a data storage device that includes a controller coupled to a memory. The data storage device emulates a printer via the interface. The image content in the first format is converted to image content in a second format and stored at the memory of the data storage device. | 12-30-2010 |
20100318839 | DATA RECOVERY IN MULTI-LEVEL CELL NONVOLATILE MEMORY - In a nonvolatile memory array, data is stored in multi-level cells (MLC) as upper-page data and lower-page data. Safe copies of both upper-page and lower-page data are stored in on-chip cache during programming. If a write fail occurs, data is recovered from on-chip cache. The controller does not have to maintain safe copies of data. | 12-16-2010 |
20100318721 | PROGRAM FAILURE HANDLING IN NONVOLATILE MEMORY - In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array. | 12-16-2010 |
20100289465 | TRANSIENT LOAD VOLTAGE REGULATOR - Systems and methods providing for improved voltage regulation of a supply voltage for an integrated circuit are described herein. The voltage regulator circuit includes a feedback circuit coupled to a first current path and adapted to maintain a gate voltage of a feedback transistor substantially constant. A pass device is coupled to a second current path and adapted to receive a signal with a magnitude based on first and second currents supplied by first and second current sources to the second current path. In an embodiment, the first current is a substantially constant current and the second current has a magnitude based on a magnitude of the voltage at the feedback transistor gate and a magnitude of a voltage at an output of the voltage regulator circuit coupled to the pass device. | 11-18-2010 |
20100240182 | Spacer Patterns Using Assist Layer For High Density Semiconductor Devices - High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers. | 09-23-2010 |
20100199032 | ENHANCED DATA COMMUNICATION BY A NON-VOLATILE MEMORY CARD - A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data lines is determined to be a plurality of data lines, the method includes switching, at the memory card, the data stream between one of the first number of data lines and another of the first number of data lines after each occurrence of a second number of one or more bits of the data stream having passed toward the host device. The method also includes, if the first number of data lines is determined to be one data line, transmitting, from the memory card, the stream of data bits over the one data line to the host device. | 08-05-2010 |
20100195397 | Controlled Boosting In Non-Volatile Memory Soft Programming - A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process. | 08-05-2010 |
20100191962 | FILE SYSTEM FILTER AUTHENTICATION - A method of accessing content includes installing a file system filter for a secure removable memory device on a host device. A challenge is sent from the file system filter to a software entity on the host device, and a software entity response is received at the file system filter in response to the challenge. A file system filter response is calculated at the file system filter using the challenge, and access to first content on the secure removable memory device is provided if the software entity response matches the file system filter response. | 07-29-2010 |
20100191955 | SYSTEM AND METHOD FOR DISTRIBUTING DIGITAL CONTENT - A method for distributing digital content is disclosed. The method includes receiving, at an operator of a wireless communications network, a request for digital content from a first mobile device. The method further includes determining, at the operator, that a second mobile device has the digital content. The method further includes receiving the digital content from the second mobile device at the operator of the wireless communications network and sending a message including a pointer related to the digital content to the first mobile device | 07-29-2010 |
20100153672 | CONTROLLED DATA ACCESS TO NON-VOLATILE MEMORY - A method of controlling data access to non-volatile memory is disclosed. The method includes storing a data file in a non-volatile memory. The non-volatile memory includes a memory array including a plurality of address ranges one or more of which corresponding to a protected portion of the memory array and one or more of which corresponding to an unprotected portion of the memory array. The method also includes communicating to a host device an indication that a memory request with respect to the protected portion of the memory array is denied. The indication is communicated for instructing the host device to avoid a timeout when the memory request is denied. | 06-17-2010 |
20100149876 | Reverse Reading In Non-Volatile Memory With Compensation For Coupling - Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information. | 06-17-2010 |
20100055889 | Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies - Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased. | 03-04-2010 |
20100023673 | AVOIDANCE OF SELF EVICTION CAUSED BY DYNAMIC MEMORY ALLOCATION IN A FLASH MEMORY STORAGE DEVICE - The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead space or unnecessarily separating functions that should be within one or a group of frequently accessed overlays. For an overlay having functions that require data allocation, the data allocation can cause eviction. This self eviction is avoided altogether or after initial runtime. | 01-28-2010 |
20090321530 | UNIVERSAL NON-VOLATILE MEMORY CARD USED WITH VARIOUS DIFFERENT STANDARD CARDS CONTAINING A MEMORY CONTROLLER - A mother/daughter card non-volatile memory system includes a daughter card containing the memory and a mother card containing the memory controller and host interface circuits. The daughter memory card contains as little more than the memory cell array as is practical, in order to minimize its cost, and has an interface for connecting with a variety of mother controller cards having physical attributes and host interfaces according to a number of different published or proprietary memory card standards. Different types of memory cards may be used when the operating parameters of the memory are stored within it in a protected location, the mother card controller then reading these parameters and adapting its operation accordingly. A radio frequency antenna may be included on a surface of the card along with its electrical contacts, in order to provide a radio frequency identification function. | 12-31-2009 |
20090307389 | SWITCHABLE ACCESS STATES FOR NON-VOLATILE STORAGE DEVICES - Techniques for switching access states for accessing non-volatile are disclosed. A plurality of non-volatile memory portions can be effectively presented as: (a) a single logical unit in a first access state (“single unit access state”) and (b) as multiple logical units in a second access state (“multi-unit access state”). An access switching system can be provided for a device that includes a plurality of non-volatile storage portions. As a result, the device can be operable to effectively switch between the first and second access states. In the first access state, the plurality of non-volatile storage portions can be effectively presented as a single logical unit for access by another device, thereby allowing the other device to effectively access the plurality of non-volatile storage portions from a single access point. However, the device can also be operable to switch to a second access state in which the plurality of the non-volatile storage portions can be effectively presented to the other device as multiple logical units, thereby allowing the other device to access the plurality of non-volatile storage portions individually by using multiple access points respectively associated with the multiple logical units presented to the other device. | 12-10-2009 |
20090296469 | Alternate Row-Based Reading And Writing For Non-Volatile Memory - A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines. | 12-03-2009 |
20090276570 | GUARANTEED MEMORY CARD PERFORMANCE TO END-OF-LIFE - In order to maintain a memory system's performance levels to its end-of-life, latency threshold level(s) are specified and associated with different memory system operating parameters. In one embodiment, the memory system monitors and gathers performance statistics in real time, and in accordance with specific memory transfer sizes. A current latency level can be dynamically calculated using the performance statistics and compared to previously established latency threshold levels. If the current latency level is greater than or equal to a specific latency threshold level, the memory system's configuration setting can be adjusted according to the operating parameters associated with the latency threshold level to offset the increased latency. | 11-05-2009 |
20090193305 | TEST MODE SOFT RESET CIRCUITRY AND METHODS - An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggering a soft reset by updating the test mode registers of the test controller. The soft reset therefore eliminates the need for an extra reset pin, when testing in scan mode. The communication channel defined through the use of the scan-in and scan clock pins can be used to trigger other soft actions. | 07-30-2009 |
20090180325 | Partitioned Erase And Erase Verification In Non-Volatile Memory - A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors. | 07-16-2009 |
20090172802 | LOCAL PROXY SYSTEM AND METHOD - A local proxy system includes a storage device having a local proxy and a physical port connection. The local proxy is part of a split proxy configuration having a local proxy and a remote proxy. The physical port connection is operative to receive commands from a host via an internet application protocol; and to transmit commands to the host via a modem control protocol, to thereby function as a gateway for conveying these commands to a remote proxy, via the host. Also provided is a method of optimizing communication over a network; and a local proxy system that includes a storage device having a local proxy. The storage device is in connection with a host via a physical port connection complying with a standard storage device interface. | 07-02-2009 |
20090167093 | Systems and Circuits with Multirange and Localized Detection of Valid Power - Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case. | 07-02-2009 |
20090153234 | CURRENT MIRROR DEVICE AND METHOD - In an embodiment, a circuit is disclosed that includes a current mirror including a first transistor pair and a second transistor pair. The first transistor pair includes a first transistor and a second transistor. The second transistor pair includes cascode transistors. The circuit also includes an operational amplifier having an output coupled to both the first transistor and the second transistor. | 06-18-2009 |
20090134502 | LEADFRAME BASED FLASH MEMORY CARDS - A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts. | 05-28-2009 |
20090106469 | SIGNALING AN INTERRUPT REQUEST THROUGH DAISY CHAINED DEVICES - A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history. | 04-23-2009 |
20090100198 | ADDRESSING MULTIPLE DEVICES ON A SHARED BUS - Assigning addresses to legacy sharing at least one signal line with a plurality of client devices. Each of the devices includes a number of I/O pins selected ones of which are connected to the at least one signal line and each client device includes a first and a second initialization pin. In the described embodiment, all but a first one of the plurality of client devices are connected to one another in a daisy chain arrangement by way of the first and the second initialization pin separate from the signal line. A first client device has a first initialization pin that is independently held at a first logic level and a second initialization pin that is connected to the daisy chain arrangement. The first one of the client devices is initialized and, in turn, triggers initialization of the daisy chained client devices. The legacy device is initialized separately from the client devices. | 04-16-2009 |
20090087963 | METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE - A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist. | 04-02-2009 |
20090085087 | LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY - A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off. | 04-02-2009 |
20090043984 | METHOD FOR MANAGING PARTITIONS IN A STORAGE DEVICE - A method for re-allocating memory partition space is provided. The method comprises determining when a first memory partition is full or has reached a threshold value, determining that a second memory partition has unused storage space that can be allocated to the first memory partition, and assigning the unused storage space from the second memory partition to the first memory partition. A memory controller embedded within the mass storage device and having an interface to an external host assigns the unused storage space from the second memory partition to the first memory partition. | 02-12-2009 |
20090021983 | Word Line Compensation In Non-Volatile Memory Erase Operations - Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used. | 01-22-2009 |
20090006796 | Media Content Processing System and Non-Volatile Memory That Utilizes A Header Portion of a File - A computer readable media storing operational instructions is disclosed. The instructions includes at least one instruction to store data of an encrypted computer readable file that includes a header portion and associated content data into a storage area of a non-volatile memory. The storage area includes a secure memory area to store data from the header portion including at least one encryption ID. The storage area further includes a memory area to store the content data. The header portion further includes trailer data derived from a portion of the content data. The instructions also include at least one instruction to provide data read access to the header portion and to the content data with respect to a host device. | 01-01-2009 |
20090006724 | Method of Storing and Accessing Header Data From Memory - Methods of storing and accessing data using a header portion of a file are disclosed. In an embodiment, a method of storing content in a non-volatile memory is disclosed. The method includes reading a content file including media content and including a trailer, storing information related to the trailer together with secure data in a header portion of a file, and storing the file to a storage element of the non-volatile memory or a memory area of a host device coupled to the non-volatile memory device. | 01-01-2009 |
20080315382 | MULTIPLE DIE INTEGRATED CIRCUIT PACKAGE - A multiple die package and removable storage card is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be electrically coupled via anisotropically conductive areas of the leadframes. | 12-25-2008 |
20080297961 | Systems, Circuits, Chips and Methods with Protection at Power Island Boundaries - Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages. | 12-04-2008 |
20080254576 | Method of fabricating a self-aligning damascene memory structure - A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements. | 10-16-2008 |
20080250202 | FLASH CONTROLLER CACHE ARCHITECTURE - A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss. | 10-09-2008 |
20080238555 | Systems, Modules, Chips, Circuits and Methods with Delay Trim Value Updates on Power-Up - Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup. | 10-02-2008 |
20080211570 | Systems, Methods, and Integrated Circuits with Inrush-Limited Power Islands - A new approach for managing turn-on of power islands uses a precharge phase to begin the process of bringing up the island's internal supply voltage, while minimizing transients and associated power-control-logic instability. | 09-04-2008 |
20080198031 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package. | 08-21-2008 |