ROUND ROCK RESEARCH, LLC Patent applications |
Patent application number | Title | Published |
20140361753 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY AND A MEMORY DEVICE - A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 12-11-2014 |
20140281177 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 09-18-2014 |
20140247942 | METHODS AND APPARATUSES TO SECURE DATA TRANSMISSION IN RFID SYSTEMS - Methods and apparatuses to secure data transmission in a radio frequency identification (RFID) system against eavesdropping, using multiple communication channels. In one embodiment, a method includes communicating key information and cipher text generated based on the key information, or plain text, using a plurality of different, distinct and separate communication channels connected to an RFID tag. | 09-04-2014 |
20140115383 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 04-24-2014 |
20140112087 | POWER MANAGEMENT CONTROL AND CONTROLLING MEMORY REFRESH OPERATIONS - A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation. | 04-24-2014 |
20140104466 | METHOD OF OPERATING A CMOS IMAGER USING COLOR INTERPOLATION - An imager has first and second photosensitive sites and an interpolator located in a semiconductor substrate. The first photosensitive site is configured to receive light having a spectral component, and the second photosensitive site is configured to measure the level of the spectral component in light received by the second photosensitive site. The interpolator is configured to estimate the level of the spectral component in the light received by the first photosensitive site based on the measurement by the second photosensitive site. | 04-17-2014 |
20140089620 | SYSTEM AND METHOD FOR CONTROLLING MEMORY COMMAND DELAY - A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media. | 03-27-2014 |
20140085980 | MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria. | 03-27-2014 |
20140062665 | METHODS AND SYSTEMS USING POLARIZATION MODULATED ELECTROMAGNETIC WAVES - Methods and systems using polarization modulated electromagnetic waves. At least some of the illustrative embodiments are systems comprising a radio frequency identification (RFID) reader, and a RFID tag (the RFID tag communicatively coupled to the RFID reader). The RFID tag is configured to transmit data to the RFID reader with data encoded in polarization of electromagnetic waves transmitted from the RFID tag. | 03-06-2014 |
20140047563 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided. | 02-13-2014 |
20130341416 | FLEXIBLE RFID LABEL - An RFID tag includes a base having at least one fold formed therein. An integrated circuit is formed on the base. At least one antenna segment extends from the integrated circuit and crosses the fold. When the fold is creased, a portion of the antenna segment on one side of the fold is aligned to be orthogonal to a portion of the antenna segment on the other side of the fold. | 12-26-2013 |
20130326132 | MEMORY SYSTEM AND METHOD HAVING UNIDIRECTIONAL DATA BUSES - A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices. | 12-05-2013 |
20130238495 | METHODS AND APPARATUS FOR FACILITATING PURCHASE TRANSACTIONS ACROSS A NETWORK - One embodiment of the present invention relates to a system that provides information and records information to facilitate a purchase transaction across a network. The system operates by receiving a request for billing information relating to a purchase transaction from a remote computer system. In response to the request, the system retrieves the billing information from a local store in the local computer system, and sends the billing information to the remote computer system. After the remote computer system completes the purchase transaction, the system receives confirmation information for the purchase transaction from the remote computer system. The system records this confirmation information in the local store in the local computer system. This enables a user of the local computer system to subsequently look up the confirmation information based on a purchase transaction identifier. Methods for facilitating a purchase transaction are also disclosed. | 09-12-2013 |
20130234275 | METHODS OF FABRICATION OF PACKAGE ASSEMBLIES FOR OPTICALLY INTERACTIVE ELECTRONIC DEVICES AND PACKAGE ASSEMBLIES THEREFOR - Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier. | 09-12-2013 |
20130162407 | RFID MATERIAL TRACKING METHOD AND APPARATUS - A method and apparatus for tracking items automatically is described. A passive RFID (Radio Frequency IDentification) tag is used with a material tracking system capable of real-time pinpoint location and identification of thousands of items in production and storage areas. Passive RFID tags are attached to the item to be tracked, remote sensing antennas are placed at each remote location to be monitored, interrogators with several antenna inputs are connected to the sensing antennas to multiplex the antenna signals, and a host computer communicates with the interrogators to determine item locations to an exacting measure. | 06-27-2013 |
20130161386 | ELECTRONIC MONITORING SYSTEMS, SHIPMENT CONTAINER MONITORING SYSTEMS AND METHODS OF MONITORING A SHIPMENT IN A CONTAINER - A shipping container has passive radio antenna element having internal and external antennas. A connector spanning the wall joins the two antennas. An internal communications device is disposed within the container and an external communications device is disposed external to the container. Another shipping container has a repeater element having internal and external antennas. A repeater unit spans the wall joining the two antennas. A communications device is disposed within the container and another communications device is disposed externally. RF signals are re-radiated by the antennas. Methodology includes inputting PF signals from a communication device disposed at a first location, receiving the signals through an antenna comprised by an antenna element, and re-radiating the signal from a second antenna comprised by the element, where the element spans the wall of a shipping container. The re-radiated signal is received by a second communications device disposed at a second location. | 06-27-2013 |
20130153902 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed. | 06-20-2013 |
20130140703 | CONTACT STRUCTURE IN A MEMORY DEVICE - Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching. | 06-06-2013 |
20130140646 | TRANSISTOR WITH REDUCED DEPLETION FIELD WIDTH - Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode. | 06-06-2013 |
20130132689 | MEMORY REGISTER ENCODING APPARATUS AND METHODS - Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded it to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed. | 05-23-2013 |
20130127597 | WIRELESS COMMUNICATION SYSTEMS, AND METHODS OF COMMUNICATION WITHIN A WIRELESS COMMUNICATION SYSTEM - The present invention relates to wireless communication systems, interrogators and methods of communicating within a wireless communication system. One aspect of the present invention provides a wireless communication system including at least one remote communication device configured to communicate a return link wireless signal; an interrogator including: a communication station configured to receive the return link wireless signal and to generate a return link communication signal corresponding to the return link wireless signal; communication circuitry coupled with the communication station and configured to communicate the return link communication signal; and a housing remotely located with respect to the communication station and including circuitry configured to receive the return link communication signal from the communication circuitry and to process the return link communication signal. | 05-23-2013 |
20130073807 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 03-21-2013 |
20130033514 | FULL-SCENE ANTI-ALIASING METHOD AND SYSTEM - A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a resulting image. A scene is rasterized at a first angle relative to a first coordinate system to generate a plurality of pixels, which are then applied to a polygon surface that is rendered at a second angle equal to the inverse of the first angle. Thus, the resulting image is re-oriented with respect to the first coordinate system. | 02-07-2013 |
20130026547 | ACTIVE PIXEL SENSOR WITH A DIAGONAL ACTIVE AREA - An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line and a processor based system with such an imaging device. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines. | 01-31-2013 |
20120312883 | COMMUNICATIONS METHODS, METHODS OF FORMING A READER, WIRELESS COMMUNICATIONS READERS, AND WIRELESS COMMUNICATIONS SYSTEMS - Communications methods, methods of forming a reader, wireless communications readers, and wireless communications systems are described in some embodiments. In one embodiment, a communications method includes associating a plurality of remote communications devices with a plurality of objects located within a wireless communications range of a reader having a first configuration, providing one of the remote communications device within a wireless communications range of a reader having a second configuration, wherein the wireless communications range of the reader having the second configuration is less than the wireless communications range of the reader having the first configuration, and during the presence of the one of the remote communications devices within the wireless communications range of the reader having the second configuration, implementing communications between the reader having the second configuration and only the one of the remote communications devices. | 12-13-2012 |
20120303885 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 11-29-2012 |
20120297129 | MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device. | 11-22-2012 |
20120278524 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 11-01-2012 |
20120268254 | METHOD AND SYSTEMS OF TAGGING OBJECTS AND READING TAGS COUPLED TO OBJECTS - Methods and systems of tagging objects and reading tags coupled to objects. At least some of the illustrative embodiments are systems comprising a reading antenna, a tag reader coupled to the reading antenna, and a radio frequency identification (RFID) tag comprising a tag antenna electromagnetically coupled to the reading antenna. The RFID tag couples to an object such as the body of a living organism or a metallic article. Moreover, the tag antenna has a far-field radiation pattern in a direction away from the object that is substantially unaffected by proximity of the RFID tag to the object, and substantially unaffected by which surface of the RFID tag faces the object. | 10-25-2012 |
20120243316 | MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size. | 09-27-2012 |
20120242670 | MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM - A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed. | 09-27-2012 |
20120239885 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 09-20-2012 |
20120232716 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 09-13-2012 |
20120226964 | DYNAMIC SYNCHRONIZATION OF DATA CAPTURE ON AN OPTICAL OR OTHER HIGH SPEED COMMUNICATIONS LINK - A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals. | 09-06-2012 |
20120223816 | RFID INTERROGATOR WITH ADJUSTABLE SIGNAL CHARACTERISTICS - A radio frequency identification (RFID) interrogator housed in a portable platform that includes at least one antenna, a transceiver for transmitting and receiving a radio frequency (RF) signal through the antenna, and a controller in communication with the transceiver for adjusting power and direction of the transmitted RF signal. The controller can be configured to adjust the antenna orientation, and can also selectively activate and deactivate one or more antennas. | 09-06-2012 |
20120221780 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 08-30-2012 |
20120221779 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 08-30-2012 |
20120218083 | METHODS AND APPARATUSES TO SECURE DATA TRANSMISSION IN RFID SYSTEMS - Methods and apparatuses to secure data transmission in a radio frequency identification (RFID) system against eavesdropping, using multiple communication channels. In one embodiment, a method includes communicating key information and cipher text generated based on the key information, or plain text, using a plurality of different, distinct and separate communication channels connected to an RFID tag. | 08-30-2012 |
20120210089 | MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY - A daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. By predicting command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM is programmeable to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response. | 08-16-2012 |
20120198194 | Multi-Bank Memory Accesses Using Posted Writes - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 08-02-2012 |
20120198144 | DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE BY APPLYING SIGNAL TO AT LEAST ONE EXTERNAL PIN DURING A READ OR WRITE TRANSACTION - A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller. | 08-02-2012 |
20120192018 | APPARATUS AND METHOD FOR DETECTING OVER-PROGRAMMING CONDITION IN MULTISTATE MEMORY DEVICE - A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells. | 07-26-2012 |
20120166862 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY AND A MEMORY DEVICE - A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 06-28-2012 |
20120159229 | METHOD FOR GENERATING A CLOCK SIGNAL - An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal. | 06-21-2012 |
20120137161 | METHOD AND APPARATUS FOR GENERATING A PHASE DEPENDENT CONTROL SIGNAL - A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted. | 05-31-2012 |
20120131251 | FAST AND COMPACT CIRCUIT FOR BUS INVERSION - A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch. | 05-24-2012 |
20120113705 | CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD - Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin. | 05-10-2012 |
20120104528 | WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING - The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision. | 05-03-2012 |
20120089801 | SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 04-12-2012 |
20120080798 | MEMORY DEVICES HAVING CONTACT FEATURES - Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching. | 04-05-2012 |
20120062762 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT AND PHOTOSENSOR CELL WITH SELECTIVELY SILICIDED GATES - The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager. | 03-15-2012 |
20120057047 | Method of operating an image sensor having a digital exposure circuit - Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the pixels are characterized, the number of pixels in any particular group is counted. That counting is compared with thresholds which set whether the image is over exposed, under exposed, and can optionally also determine if the image is seriously over exposed or seriously under exposed. Adjustment of the exposure is carried out to bring the image to a more desired state. | 03-08-2012 |
20120044752 | HIGH DENSITY INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY - Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells. | 02-23-2012 |
20120044735 | STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS - Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery. | 02-23-2012 |
20120039123 | MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE - The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels. | 02-16-2012 |
20120037902 | CONSTRUCTIONS COMPRISING HAFNIUM OXIDE AND/OR ZIRCONIUM OXIDE - The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase. | 02-16-2012 |
20120036314 | MEMORY DEVICES HAVING PROGRAMMABLE ELEMENTS WITH ACCURATE OPERATINGPARAMETERS STORED THEREON - A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system. | 02-09-2012 |
20120036303 | APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS - Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. | 02-09-2012 |
20120033513 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access. | 02-09-2012 |
20120028582 | METHODS OF OPERATING ELECTRONIC DEVICES, AND METHODS OF PROVIDING ELECTRONIC DEVICES - Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing. | 02-02-2012 |
20120005420 | DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE BY APPLYING SIGNAL TO AT LEAST ONE EXTERNAL PIN DURING A READ OR WRITE TRANSACTION - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. | 01-05-2012 |
20120005389 | SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 01-05-2012 |
20120002474 | INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM - An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank. | 01-05-2012 |
20120001242 | SINGLE POLY CMOS IMAGER - More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate. | 01-05-2012 |
20110314199 | APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations. | 12-22-2011 |
20110307649 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 12-15-2011 |
20110298077 | METHODS OF FABRICATION OF PACKAGE ASSEMBLIES FOR OPTICALLY INTERACTIVE ELECTRONIC DEVICES AND PACKAGE ASSEMBLIES THEREFOR - Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier. | 12-08-2011 |
20110273938 | CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZING CIRCUIT FOR LOW POWER REFRESH OPERATION - A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete. | 11-10-2011 |
20110273362 | ELECTRONIC MONITORING SYSTEMS, SHIPMENT CONTAINER MONITORING SYSTEMS AND MEHTODS OF MONITORING A SHIPMENT IN A CONTAINER - A shipping container has a passive radio antenna element having internal and external antennas. A connector spanning the wall joins the two antennas. An internal communications device is disposed within the container and an external communications device is disposed external to the container. Another shipping container has a repeater element having internal and external antennas. A repeater unit spans the wall joining the two antennas. A communications device is disposed within the container and another communications device is disposed externally. RF signals are re-radiated by the antennas. Methodology includes emitting RF signals from a communication device disposed at a first location, receiving the signals through an antenna comprised by an antenna element, and re-radiating the signal from a second antenna comprised by the element, where the element spans the wall of a shipping container. The re-radiated signal is received by a second communications device disposed at a second location. | 11-10-2011 |
20110273297 | METHOD AND SYSTEM FOR IDENTIFYING MISSING ITEMS - A system for identifying a lost or stolen device includes a transmitter, a receiver and a computer. The transmitter is coupled to the device and transmits identification information. The receiver receives the identification information transmitted by the transmitter when the transmitter is within a defined distance from the receiver. The computer is coupled to the receiver so as to receive the information from the receiver. The computer has a first secure database which stores data associated with lost or stolen devices and which prevents unauthorized access to the data stored therein. The computer compares the information with the stored data, and generates an alarm if the information matches at least some of the stored data. | 11-10-2011 |
20110261628 | 256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. | 10-27-2011 |
20110261082 | METHODS AND APPARATUS FOR RENDERING OR PREPARING DIGITAL OBJECTS OR PORTIONS THEREOF FOR SUBSEQUENT PROCESSING - Methods and apparatus render images of digital objects or prepare digital objects for subsequent processing. The method includes sorting data representative of positions of at least three vertices of polygons of a digital object, then determining whether the orientation of the vertices of each polygon from a specific reference point differs from the actual, or original, orientation of the vertices. Such a determination may be made by generating an orientation decision variable based on the relative positions of the vertices and calculating a cross product term (CPT) after the vertex data has been sorted. The CPT may also be used in other operations involving the polygon, such as in imparting appearance characteristics to the polygon. The method may be embodied as a computer program that controls the operation of a processor. Accordingly, processors, computers, and systems that render images of digital objects in accordance with the method are also disclosed. | 10-27-2011 |
20110260838 | SYSTEMS AND METHODS FOR RFID TAG ARBITRATION WHERE RFID TAGS GENERATE MULTIPLE RANDOM NUMBERS FOR DIFFERENT ARBITRATION SESSIONS - A radio frequency identification device (RFID) tag includes a processor, a memory configured to store an identification number that distinguishes the tag from other tags, and a transponder coupled to the memory and the processor. The tag arbitrates by selecting a random number in response to an inventory query from a reader. The tag responds to the reader depending on the random number selected. The tag is configured for multiple concurrent inventory session arbitrations with multiple readers by separately storing random numbers for respective inventory session arbitrations. | 10-27-2011 |
20110260835 | METHODS AND SYSTEMS OF TAGGING OBJECTS AND READING TAGS COUPLED TO OBJECTS - Methods and systems of tagging objects and reading tags coupled to objects. At least some of the illustrative embodiments are systems comprising a reading antenna, a tag reader coupled to the reading antenna, and a radio frequency identification (RFID) tag comprising a tag antenna electromagnetically coupled to the reading antenna. The RFID tag couples to an object such as the body of a living organism or a metallic article. Moreover, the tag antenna has a far-field radiation pattern in a direction away from the object that is substantially unaffected by proximity of the RFID tag to the object, and substantially unaffected by which surface of the RFID tag faces the object. | 10-27-2011 |
20110258403 | MEMORY HUB WITH INTEGRATED NON-VOLATILE MEMORY - A method for initializing a memory sub-system is provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub. The non-VOLATILE memory is accessed through a first configuration path from a memory controller of the memory sub-system to the non-VOLATILE memory. | 10-20-2011 |
20110255362 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized clock output signal. The system has a plurality of signal buses coupling the processor to the memory controller and the memory controller to said DRAM chips. The signal line conveys signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic. A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 10-20-2011 |
20110246743 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 10-06-2011 |
20110239876 | DIFFERENTIAL PRESSURE APPLICATION APPARATUS FOR USE IN POLISHING LAYERS OF SEMICONDUCTOR DEVICE STRUCTURES AND METHODS - An apparatus for applying different amounts of pressure to different locations of a semiconductor device structure or other substrate during polishing thereof. The apparatus is configured to be associated with a wafer carrier of a polishing apparatus and includes pressurization structures configured to individually apply pressure to a major surface of the semiconductor device structure during polishing thereof. Systems including the pressure application apparatus, as well as differential pressure application methods and polishing methods are also disclosed. | 10-06-2011 |
20110219256 | SYNCHRONIZATION DEVICES HAVING INPUT/OUTPUT DELAY MODEL TUNING ELEMENTS IN SIGNAL PATHS TO PROVIDE TUNING CAPABILITIES TO OFFSET SIGNAL MISMATCH - Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures. | 09-08-2011 |
20110219196 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 09-08-2011 |
20110205409 | COLOR INTERPOLATION - An imager has first and second photosensitive sites and an interpolator located in a semiconductor substrate. The first photosensitive site is configured to receive light having a spectral component, and the second photosensitive site is configured to measure the level of the spectral component in light received by the second photosensitive site. The interpolator is configured to estimate the level of the spectral component in the light received by the first photosensitive site based on the measurement by the second photosensitive site. | 08-25-2011 |
20110193685 | RFID COMMUNICATION SYSTEMS AND METHODS, AND RFID READERS AND SYSTEMS - A method of coordinating a plurality of RFID readers includes controlling the RFID readers such that only one of the readers performs an inventory of RFID tags at a time. A system for coordinating a plurality of RFID readers is also provided. | 08-11-2011 |
20110186964 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES - The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions. | 08-04-2011 |
20110182130 | LOW CURRENT WIDE VREF RANGE INPUT BUFFER - A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages. | 07-28-2011 |
20110180695 | LAYERED LENS STRUCTURES AND METHODS OF PRODUCTION - A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an angle away from normal to form upper lens layers that increase the effective focal length of the microlens structure. The upper lens layers can be deposited in an aspherical shape with radii of curvature longer than the lower lens layers. As a result, small microlenses can be provided with longer focal length. The microlenses are arranged in arrays for use in imaging devices. | 07-28-2011 |
20110169993 | METHOD AND APPARATUS PROVIDING CMOS IMAGER DEVICE PIXEL WITH TRANSISTOR HAVING LOWER THRESHOLD VOLTAGE THAN OTHER IMAGER DEVICE TRANSISTORS - A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V. | 07-14-2011 |
20110169846 | MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM - A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed. | 07-14-2011 |
20110169421 | METHOD AND APPARATUS FOR PROVIDING ILLUMINATION WITH A PULSE-CONTROLLED LIGHT EMITTING DIODE SOURCE - An array of LEDs includes first and second rows of LEDs. The LEDs emit light at red, green, and blue wavelengths parallel to an output port, and the light is re-directed by a light reflecting material from directions parallel to the output port toward the output port. The first and second rows are parallel to each other, and the LEDs are powered by pulse width modulated signals that establish a brightness of the LEDs. | 07-14-2011 |
20110169007 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed. | 07-14-2011 |
20110167238 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 07-07-2011 |
20110167237 | MULTI-BANK MEMORY ACCESSES USING POSTED WRITES - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 07-07-2011 |
20110164453 | SYSTEM AND MEMORY FOR SEQUENTIAL MULTI-PLANE PAGE MEMORY OPERATIONS - A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes. | 07-07-2011 |
20110163443 | METHODS FOR WAFER-LEVEL PACKAGING OF MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED BY SUCH METHODS - Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices re disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state. | 07-07-2011 |
20110145463 | SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 06-16-2011 |
20110145453 | CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate. | 06-16-2011 |
20110140222 | PASSIVATION PLANARIZATION - A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on glass layer may be deposited over the non-uniform passivation layer prior to planarization. Once a uniform, flat first passivation layer is achieved over the final metal, a second passivation layer, a color filter array, or a lens forming layer with uniform thickness is formed over the first passivation layer. The passivation layers can be oxide, nitride, a combination of oxide and nitride, or other suitable materials. The color filter array layer may also undergo a planarization process prior to formation of the lens forming layer. The present invention is also applicable to other devices. | 06-16-2011 |
20110124178 | STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE - An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation. | 05-26-2011 |
20110124171 | APPLYING EPITAXIAL SILICON IN DISPOSABLE SPACER FLOW - A method of fabricating transistors on a semiconductor substrate includes forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively. The transistor gates have generally vertical sidewalls. Source and drain regions are simultaneously formed for the first and second transistors. Temporary spacers are formed on the vertical sidewalls of the first and second transistor gates. The temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered. The temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed. The semiconductor substrate is exposed to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors. | 05-26-2011 |
20110122710 | METHOD AND APPARATUS FOR GENERATING A SEQUENCE OF CLOCK SIGNALS - A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch. | 05-26-2011 |
20110119519 | METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM - An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal. | 05-19-2011 |
20110117743 | MULTIPLE DEPOSITION FOR INTEGRATION OF SPACERS IN PITCH MULTIPLICATION PROCESS - Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon. | 05-19-2011 |
20110113189 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 05-12-2011 |
20110108929 | ENHANCED ATOMIC LAYER DEPOSITION - Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF | 05-12-2011 |
20110102036 | PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS - A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL. | 05-05-2011 |
20110089539 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad. | 04-21-2011 |
20110084808 | TRACKING SYSTEMS, METHODS OF LOCATING AND IDENTIFYING RFIDS, AND METHODS OF TRACKING ITEMS - Some embodiments include observable properties triggered upon interrogation of RFIDs. The RFIDs can be passive RFIDs, and the observable properties can be visible changes that require little power to generate, and little or no power to maintain. The visible information can include information about items tracked with the RFIDs, such as shipping information. Some embodiments include passive RFIDs utilizing a single antenna to power an integrated-circuit chip and a visual identifier. Some embodiments include methods of locating interrogated RFIDs. Some embodiments include methods of tracking items. | 04-14-2011 |
20110069567 | Memory device having data paths with multiple speeds - A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. | 03-24-2011 |
20110050305 | CENTRALIZING THE LOCK POINT OF A SYNCHRONOUS CIRCUIT - A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line. | 03-03-2011 |
20110042640 | METHOD OF FABRICATING PHASE CHANGE MEMORY CELL - A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. | 02-24-2011 |
20110038217 | MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active. | 02-17-2011 |
20110037437 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY - A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 02-17-2011 |
20110032261 | METHOD OF IMPLEMENTING AN ACCELERATED GRAPHICS PORT FOR A MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM - An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions. | 02-10-2011 |
20110032171 | METHODS AND SYSTEMS OF CHANGING ANTENNA POLARIZATION - A switch assembly selectively couples an antenna communication circuit to a first feed point of a first antenna, and selectively couples the antenna communication circuit to a second feed point of a second antenna. Each feed point is selected based on polarization of an electromagnetic wave to be radiated from or received by the corresponding antenna. | 02-10-2011 |
20110029746 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 02-03-2011 |
20110025506 | REMOTE COMMUNICATION DEVICES, RADIO FREQUENCY IDENTIFICATION DEVICES, WIRELESS COMMUNICATION SYSTEMS, WIRELESS COMMUNICATION METHODS, RADIO FREQUENCY IDENTIFICATION DEVICE COMMUNICATION METHODS, AND METHODS OF FORMING A REMOTE COMMUNICATION DEVICE - Remote communication devices, radio frequency identification devices, wireless communication systems, wireless communication methods, radio frequency identification device communication methods, and methods of forming a remote intelligent communication device are provided. According to one aspect, a remote intelligent communication device includes communication circuitry configured to at least one of receive communication signals and generate communication signals; and an antenna coupled with the communication circuitry and substantially tuned to a plurality of frequencies, the antenna being configured to communicate wireless signals corresponding to the communication signals including at least one of receiving wireless signals and outputting wireless signals. Another aspect includes a wireless communication method including providing a remote intelligent communication device having an antenna substantially tuned to a plurality of frequencies; and communicating wireless signals using the antenna including at least one of receiving wireless signals at one of the frequencies and outputting wireless signals at one of the frequencies. | 02-03-2011 |
20110022873 | SYSTEM WITH POWER SAVING DELAY LOCKED LOOP CONTROL - The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed. | 01-27-2011 |
20110013451 | NON-VOLATILE MEMORY DEVICE WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions. | 01-20-2011 |
20110006372 | FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES - Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping. | 01-13-2011 |
20110006347 | LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS - In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry. | 01-13-2011 |
20100329082 | RANGE FINDING AUDIO SYSTEM - A range finding audio system automatically modifies the audio output of an audio source based on the distance of a listener from the speakers. A speaker in an audio system may include a range device coupled with a controller. The range device may utilize infrared, laser, or acoustic technology to determine the distance between the speaker and the listener. The controller may transfer distance information to an audio interface of a processor unit. The audio lo interface may include a positioning routine to modify the audio output according to the distance from the speaker to the listener. Alternatively, the controller may perform the functions ascribed to the positioning routine making the necessary modifications to the audio output based on the distance information. | 12-30-2010 |
20100323656 | METHODS OF OPERATING ELECTRONIC DEVICES, AND METHODS OF PROVIDING ELECTRONIC DEVICES - Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing. | 12-23-2010 |
20100289678 | Parallel-to-serial data sort device - A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals. | 11-18-2010 |
20100267226 | Method of forming a structure over a semiconductor substrate - The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. | 10-21-2010 |
20100262769 | METHOD AND CIRCUIT FOR ADJUSTING A SELF-REFRESH RATE TO MAINTAIN DYNAMIC DATA AT LOW SUPPLY VOLTAGES - A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor. | 10-14-2010 |
20100244916 | SELF-TIMED FINE TUNING CONTROL - A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop. | 09-30-2010 |
20100244261 | THROUGH-HOLE CONTACTS IN A SEMICONDUCTOR DEVICE - Devices with conductive through-waver vias. In one embodiment, the device is formed by a method comprising providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting material to thereby expose a portion of the layer of metal, the opening extending from at least a second side of the layer of semiconducting material to the layer of metal, and performing a deposition process to form a conductive contact in the opening using the exposed portion of the metal layer as a seed layer. | 09-30-2010 |
20100220537 | ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS - An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively. | 09-02-2010 |
20100220103 | MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM - A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed. | 09-02-2010 |
20100214138 | Balanced Data Bus Inversion - A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used. | 08-26-2010 |
20100210111 | PITCH REDUCED PATTERNS RELATIVE TOPHOTOLITHOGRAPHY FEATURES - Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate. | 08-19-2010 |
20100191924 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING AMEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 07-29-2010 |
20100184258 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT ELECTRODE HAVING A REDUCED CONTACT AREA - A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug. | 07-22-2010 |
20100153794 | SYSTEM AND METHOD FOR ON-BOARD TIMING MARGIN TESTING OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices. | 06-17-2010 |
20100148924 | Wireless Communication Devices - A method of controlling access to a movable container, the method comprising controllably locking the container using an electronically actuated locking mechanism; storing in a memory a desired geographical location; determining the geographical location of the container; and enabling the locking mechanism to unlock the container if the determined geographical location matches the desired geographical location. A secure cargo transportation system comprises a vehicle including an enclosure having an opening; a door movable relative to the opening between a closed position, wherein the door restricts access to the enclosure, and an open position; an electronically actuable lock configured to selectively lock or unlock the door relative to the enclosure; a memory supported by the vehicle and configured to store a location coordinate; and a global positioning system supported by the vehicle and coupled to the memory and to the lock, and configured to enable the lock to unlock the door if the vehicle is within a predetermined distance of the location coordinate. | 06-17-2010 |
20100148331 | SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR DICE IN LATERALLY OFFSET STACKED ARRANGEMENT - A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device. | 06-17-2010 |
20100142273 | PROGRAMMING METHODS FOR MULTI-LEVEL MEMORY DEVICES - A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage. | 06-10-2010 |
20100138598 | MEMORY DEVICES WITH BUFFERED COMMAND ADDRESS BUS - Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller. | 06-03-2010 |