NUVOTON TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20160119121 | ENCRYPTION/DECRYPTION APPARATUS AND ENCRYPTION/DECRYPTION METHOD THEREOF - An encryption/decryption apparatus and an encryption/decryption method thereof are provided. A data encryption/decryption unit performs an encryption/decryption operation to a digital data and thus generates an encryption/decryption power signal corresponding to the encryption/decryption operation. A complementary power generating unit generates a complementary power signal corresponding to the encryption/decryption power signal. The encryption/decryption apparatus outputs the complementary power signal and the encryption/decryption power signal as a power signal, wherein a sum of the complementary power signal and the encryption/decryption power signal is a fixed value. | 04-28-2016 |
20150340432 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer. | 11-26-2015 |
20150340187 | ELECTRICALLY RESETTABLE FUSE DEVICE - An integrated circuit is provided that includes an electrically resettable fuse device. The electrically resettable fuse device has a plurality of resettable fuse modules coupled in parallel. Each resettable fuse module including a fuse element characterized by a first and a second impedance states. The plurality of resettable fuse modules are configured such that when the fuse element is in the first impedance state, and a current flowing through each fuse element in a first direction exceeds a current limit, the fuse element enters into the second impedance state. When the fuse element is in the second impedance state and, in response to a global reset signal and a local reset signal, a current is applied to the fuse element in a second direction opposite the first direction, the fuse element is reset to the first impedance state. | 11-26-2015 |
20150268681 | Voltage Converter and Regulating Circuit Control Chip - A voltage converter having a regulating circuit controlled by a duration adaptive pulse signal is disclosed. An input voltage is regulated by the regulating circuit according to the pulse signal to generate an output voltage. A first comparator of the voltage converter compares a first reference signal with a feedback value of the output voltage and thereby generates a first comparator output. The first reference signal fluctuates with the pulse signal. The voltage converter further includes an active-duration adjusting circuit that starts the active duration of the pulse signal in accordance with the first comparator output and ends the active duration of the pulse signal in accordance with a second reference signal. The DC value of the second reference signal depends on the duty cycle of the pulse signal. | 09-24-2015 |
20150251554 | SWITCH CIRCUIT AND MOTOR ENERGY RECYCLING SYSTEM - A switch circuit and a motor energy recycling system are disclosed herein. The switch circuit includes a power unit and a switch module. The power unit includes a first battery and a second battery, in which the first battery is configured to supply the electrical energy and the second battery is configured to store the electrical energy. The switch module is configured to switch the first battery to store the electrical energy and to switch the second battery to supply the electrical energy, according to a switch signal. | 09-10-2015 |
20150214734 | Control Chip, Control Method and Connection Device Utilizing the Same - A control chip including a plurality of first pins, a plurality of second pins, a plurality of third pins, a level detection unit, a determining unit and a control unit is provided. The first pins are coupled to a host device via a first connection port. The second pins are coupled to an electronic device via a second connection port. The third pins are coupled to a peripheral device via a third connection port. The level detection unit detects the first and second pins to generate a first detection result. The determining unit determines whether a portion of the first and second pins transmit data to generate a determination result. The control unit adjusts a level of a specific pin among the first and second pins according to the first detection result and the determination result. | 07-30-2015 |
20150149703 | APPARATUSES FOR SECURING PROGRAM CODE STORED IN A NON-VOLATILE MEMORY - An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region. Two NVMMCS (non-volatile memory management controllers respectively coupled to the two regions. A programming command-and-address decoder is coupled to the NVMMCS. The programming command-and-address decoder instructs the first NVMMC to erase data from the first region when receiving a command to erase the first region via a programming interface, and instructs the second NVMMC to erase data from the second region when receiving a command to erase the second region via the programming interface. | 05-28-2015 |
20150116028 | Fuse Circuit - A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses. | 04-30-2015 |
20150085416 | INTEGRATED CIRCUIT WITH PROTECTION FUNCTION - An integrated circuit generating a driving signal to a load according to an input voltage and including an impedance switching unit, a first protection unit, a first detection unit and a control unit is disclosed. The impedance switching unit takes the input voltage as the driving signal according to a control signal. The first protection unit generates a first detection signal when a current passing through the impedance switching unit is higher than a predetermined current. The first detection unit detects a voltage of the impedance switching unit to generate a detection result. The control unit controls the control signal according to the first detection signal. | 03-26-2015 |
20150074460 | APPARATUS AND METHOD FOR COMPUTER DEBUG - A computer debug module for use in a computer at least includes a power sequence monitor module. The power sequence monitor module includes a monitor unit, a register, and an output control unit. The monitor unit is configured to monitor a plurality of power sequence signals relative to the computer and generate a monitor result. The register is configured to store the monitor result. When the power sequence monitor module operates in a debug mode, the output control unit generates a detection signal according to the stored monitor result and transmits the detection signal to an output device. | 03-12-2015 |
20150063585 | METHOD AND APPARATUS FOR REDUCING CROSSTALK IN AN INTEGRATED HEADSET - An audio system has a first channel for receiving a first input signal and driving a first speaker and a second channel for receiving a second input signal and driving a second speaker. A first feedforward circuit couples an input of the second channel circuit to an input of the first channel circuit. A second feedforward circuit couples an input of the first channel circuit to an input of the second channel circuit. Circuit parameters of the first and the second feedforward circuits are determined such that a first detected output signal is zero when the first input signal is non-zero and the second input signal is zero, and a second detected output signal is zero when the second input signal is non-zero and the first input signal is zero. The audio system is configured to operate using the determined circuit parameters for the first and the second feedforward circuits. | 03-05-2015 |
20150062074 | SENSING DEVICE - A sensing device includes a comparator, a first and a second variable capacitor unit. A first comparator input of the comparator is electrically coupled to a touch pad. The first variable capacitor unit is configured to charge the first comparator input such that the first comparator input has a first potential. The second variable capacitor unit is configured to charge a second comparator input of the comparator such that the second comparator input has a second potential. The comparator is configured for comparing the first potential and the second potential to generate a comparator output signal. In a condition of the touch pad being operated, the first variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the first comparator input, or the second variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the second comparator input. | 03-05-2015 |
20150057772 | INPUT DEVICE PROVIDING CONTROL INFORMATION TO HOST DEVICE - An input device provides control information to a host device and including a plurality of keys, a division module and a control module is disclosed. When an object presses a specific key, the specific key generates a resistance value according to a force applied by the object. The division module receives the resistance value and generates a voltage level according to the resistance value and a first level. The control module generates the control information according to the voltage level. The host device executes a function corresponding to the specific key according to the control information. | 02-26-2015 |
20150042478 | ALERT METHOD AND ALERT SYSTEM THEREOF - An alert method and an alert system thereof. The alert method includes: detecting, by a turn detector installed on a steering wheel, a first turn and a second turn of the steering wheel in a predetermined period; generating, by a controller, a first alert signal based on the first and second turns; and when receiving the first alert signal, generating, by an alert device, a first alert message. | 02-12-2015 |
20150026367 | COMPUTER DEVICE AND IDENTIFICATION DEVICE THEREIN - An identification device includes a processing unit. The processing unit is electrically connected between a control circuit and a connection port, in which the processing unit is configured for detecting and identifying an external device which is connected to the port; when the processing unit identifies the external device as a first external device, the processing unit is configured for blocking information transmission between the first external device and the control circuit and when the processing unit identifies the external device as a second external device, the processing unit is configured for enabling the information transmission between the second external device and the control circuit. | 01-22-2015 |
20150022178 | REFERENCE VOLTAGE GENERATING CIRCUITS - A reference voltage generating circuit. A bandgap circuit includes a current mirror circuit and an output circuit. The current mirror circuit generates a first current. The output circuit generates a reference current based on the first current. A compensation circuit is coupled to the bandgap circuit in parallel at a combination node and generates a compensation current. The compensation current is smaller than the reference current. The reference current has a first temperature coefficient and the compensation current has a second temperature coefficient that is inverse to the first temperature coefficient. The reference current and the compensation current are combined at the combination node, such that an absolute value of a temperature coefficient of the reference voltage of the combination node is smaller than an absolute value of the first temperature coefficient and an absolute value of the second temperature coefficient. | 01-22-2015 |
20140348344 | COMMUNICATION SYSTEM AND TRANSFER METHOD THEREOF - A communication system is provided. A receiver receives a plurality of audio signals, wherein a frequency of each of the audio signals is selected from a frequency group formed by at least three frequencies. A signal detector coupled to the receiver is configured to obtain the frequency of each of the audio signals. A processor coupled to the signal detector is configured to convert the frequency of each of the audio signals into a digital signal having a first logic level or a second logic level. Two adjacent audio signals of the audio signals have different frequencies, and at least one frequency of the frequency group is used to dynamically represent the first logic level or the second logic level. | 11-27-2014 |
20140317391 | METHOD FOR CHANGING A SYSTEM PROGRAM AND PROCESSING DEVICE UTILIZING THE SAME - A processing device includes a program memory and a processor. The program memory includes at least a first memory partition for storing a system program and a second memory partition for storing an application program. The processor is coupled to the program memory for executing the programs stored in the program memory. The processor executes the application program to enable the processing device to provide at least a predetermined function, and executes the system program to enable the processing device to update the application program. When the system program has to be changed, the processor further receives a first program from a host, stores the first program in the second memory partition, triggers a reboot procedure to reboot from the second memory partition and thereafter execute the first program to change the system program based on the first program. | 10-23-2014 |
20140223212 | POWER MANAGEMENT CIRCUIT, POWER MANAGEMENT METHOD, AND COMPUTER SYSTEM - A power management circuit is provided. The power management circuit includes a power switch, a current/voltage detector, a current setting unit, and a control unit. The power switch is coupled to a power supply of the computer system. When the power switch is turned on, it supplies an output current and an output voltage of the power supply to an external device. The current/voltage detector detects the magnitudes of the output current and the output voltage. The current setting unit sets a plurality of current thresholds. When the computer system is in a power-saving state and when the output current is greater than a first current threshold and smaller than a second current threshold or the output voltage is smaller than a first voltage threshold and larger than a second voltage threshold, the control unit issues a notification signal to execute a predetermined operation on the power supply. | 08-07-2014 |
20140207961 | CHIP AND COMPUTER SYSTEM - A computer system is provided. The computer system comprises a network module and an input device. The network module receives remote information from a remote host through a network. The input device receives first input information, a display device and a chip. The display device comprises a display panel and an on-screen display (OSD) control module. The chip comprises a control connection interface and a control module. The control connection interface is electrically connected to the OSD control module. The control module is electrically connected to the network module, the input device and the control connection interface to control the OSD control module through the control connection interface according to the remote information or the first input information to further control the display function of the display panel | 07-24-2014 |
20140207879 | COMMUNICATION SYSTEM, MASTER DEVICE, AND COMMUNICATION METHOD - A communication system, a master device, and a communication method are provided. The communication system includes a master device and at least one slave device. The master device periodically sends a plurality of synchronous messages at intervals of a first predetermined time. The at least one slave device respectively receives the corresponding synchronous messages via wireless communication. The master device and the at least one slave device synchronously switch an operating frequency of wireless communication according to a frequency table. | 07-24-2014 |
20140173370 | DEBUG SYSTEM, APPARATUS AND METHOD THEREOF FOR PROVIDING GRAPHICAL PIN INTERFACE - A debug apparatus for debugging a chip under test with a plurality of pins is provided. The debug apparatus includes a processor for controlling the chip under test via a bridge device. The processor provides graphical data to indicate pin states of the chip under test when the chip under test is controlled by the processor. | 06-19-2014 |
20140164460 | DIGITAL SIGNAL PROCESSING APPARATUS AND PROCESSING METHOD THEREOF - A digital signal processing apparatus and a digital signal processing method are provided. The digital signal processing apparatus includes a memory, a control logic unit, a butterfly arithmetic unit, a selector, a first twiddle factor generator, a second twiddle factor generator and a twiddle factor latch. The first twiddle factor generator and the second twiddle factor respectively provide a first sub-twiddle factor and a second sub-twiddle factor. A weight value (twiddle factor) is produced by the butterfly arithmetic unit through performing a complex multiplication operation on the first sub-twiddle factor and the second sub-twiddle factor. | 06-12-2014 |
20140125411 | METHOD AND APPARATUS FOR FILTER-LESS ANALOG INPUT CLASS D AUDIO AMPLIFIER CLIPPING - An integrated circuit (IC) chip has a class D PWM (pulse width modulation) amplifier configured for generating first and second PWM signals. The class-D PWM modulator includes a differential output driver configured for driving a first and a second output signals in response to the first and the second PWM signals. A clipping detection circuit is configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal. The clipping detection circuit is also configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal. | 05-08-2014 |
20140118293 | TOUCH SENSING PANEL - A touch sensing panel includes first electrodes and second electrodes. The first electrodes are connected with each other. The second electrodes and the first electrodes are formed on a same surface of a substrate. The first electrodes are formed on the substrate in a first direction, and the second electrodes are formed on the substrate in a second direction which is perpendicular to the first direction. Furthermore, the second electrodes are electrically connected with each other through conductive lines, and adjacent two of the first electrodes surround one of the second electrodes. | 05-01-2014 |
20140089710 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND OPERATION METHOD THEREOF - An embodiment of the invention provides an electronic device. The electronic device includes a first wireless module, a second wireless module and a controller. The first wireless module is controlled by a chipset to communicate with a portable device. The second wireless module communicates with the portable device. The controller is coupled to the second wireless module. When the first wireless module and the chipset are disabled, the electronic device receives a signal from the portable device via the second wireless module. | 03-27-2014 |
20140082721 | SECURED COMPUTING SYSTEM WITH ASYNCHRONOUS AUTHENTICATION - A computing device includes an input bridge, an output bridge, a processing core, and authentication logic. The input bridge is coupled to receive a sequence of data items for use by the device in execution of a program. The processing core is coupled to receive the data items from the input bridge and execute the program so as to cause the output bridge to output a signal in response to a given data item in the sequence, and the authentication logic is coupled to receive and authenticate the data items while the processing core executes the program, and to inhibit output of the signal by the output bridge until the given data item has been authenticated. | 03-20-2014 |
20140061788 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region. | 03-06-2014 |
20140052977 | ELECTRONIC APPARATUS AND METHOD FOR BOOTING THE SAME - An electronic apparatus includes an operating system and a control circuit. The operating system is driven by an output command signal to execute one of plural different boot procedures. The control circuit detects an input command signal correspondingly generated when a power push-button is pressed down in a condition of the operating system being deactivated, and generates the output command signal according to the detected input command signal. Moreover, a method for booting an electronic apparatus is also disclosed herein. | 02-20-2014 |
20140027811 | SEMICONDUCTOR DEVICE - A semiconductor device includes a metal-oxide-semiconductor field effect transistor (MOSFET), in which parasitic silicon controlled rectifier (SCR) equivalent circuits are formed in the MOSFET, and the MOSFET further includes a drain region. The drain region includes P-type heavily doped regions which are different from each other, in which the P-type heavily doped regions are respectively operated as anodes of the SCR equivalent circuits. | 01-30-2014 |
20140025718 | CIRCUIT AND METHOD FOR GENERATING RANDOM NUMBER - A circuit and a method for generating a random number are provided. The circuit for generating the random number includes an analog-to-digital converter and a controller. The analog-to-digital converter sequentially generates a plurality of digital data in response to an analog signal. The controller utilizes an estimation procedure to sequentially analyze a variation trend of the plurality of digital data in a time sequence or extract components of the plurality of digital data within a preset frequency band. In addition, the controller generates a true random number based on a result of the estimation procedure. | 01-23-2014 |
20130335010 | CONNECTOR AND CONTROL CHIP - A connector is provided. In one embodiment, the connector conforms to a data communication standard, and is connected to a cable, and comprises a contact opening and a control chip. The contact opening comprises a plurality of first contacts on a first side for performing a data communication process, and a plurality of second contacts on a second side for performing a rapid charging process. The control chip is coupled between the contact opening and the cable, and couples the second contacts to a downstream power port of the cable when the second contacts of the contact opening is coupled to a host connector of a host. | 12-19-2013 |
20130300707 | PARSIMONIOUS SYSTEMS FOR TOUCH DETECTION AND CAPACITIVE TOUCH METHODS USEFUL IN CONJUNCTION THEREWITH - A touch sensing system comprising a set of touch surfaces in a touch panel including a population of touch surfaces; and at least one touch alert generator separately alerting for touch on each of, and both of, at least first and second touch surfaces from among the population of touch surfaces, wherein the alert generator is operative to determine capacitance of said first touch surface, determine touch object capacitance of said first and second touch surfaces, and compute a difference between the two capacitances, thereby to generate an approximation for touch object capacitance of said second touch surface. | 11-14-2013 |
20130300500 | METHOD AND APPARATUS FOR FILTER-LESS CLASS D AUDIO AMPLIFIER EMI REDUCTION - An audio system includes a speaker and a class D amplifier with a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals, each with three differential output levels. The class-D amplifier also has a differential output driver configured for driving a first and a second output signals onto a first and a second output terminals in response to the first and the second PWM signals, wherein each of the first and the second output signals has three differential output levels. An inverse common-mode signal generator is coupled to first and second output signals for providing an inverse common-mode signal. The audio system also includes one or more output terminals for providing the inverse common mode signal, and further includes a wire or a trace on a PCB (printed circuit board) inverse common mode signal. | 11-14-2013 |
20130287019 | ROUTING CIRCUIT AND CIRCUIT HAVING THE ROUTING CIRCUIT - A routing circuit and a circuit having the routing circuit are provided. The circuit includes a plurality of integrated circuits (ICs), a plurality of signal terminals and the routing circuit. Each of the ICs has a plurality of signal channels. The routing circuit is coupled between the ICs and the signal terminals to route the signal channels to the signal terminals. The routing circuit has a plurality of sequencers and a processing circuit. Each of the sequencers is configured to reconfigure an arrangement sequence of the signal channels of a corresponding one of the ICs. The processing circuit is coupled to the sequencers and has a first distributor. The first distributor routes the signal channels to the signal terminals in a group manner based on the arrangement sequences of the signal channels reconfigured by the sequencers according to a control signal. | 10-31-2013 |
20130260680 | ELECTRONIC DEVICE FOR REDUCING POWER CONSUMPTION - An electronic device includes a transparent substrate, an antenna, a first chip, and a second chip. The antenna is disposed above the transparent substrate. The first chip includes a sensor. The sensor is configured to detect whether the antenna has received a wireless signal or not. The second chip is coupled to the first chip, and operates in a power-saving mode. When the antenna receives the wireless signal, the first chip wakes up the second chip such that the second chip switches from the power-saving mode to a work mode, and the first chip transmits the wireless signal to the second chip. | 10-03-2013 |
20130234980 | Touch Sensing Apparatus and Method - A touch sensing apparatus includes a touch sensing trace and a signal processing circuit. The touch sensing trace is configured to generate a sensing signal including a noise signal. A first input terminal of the signal processing circuit is configured to receive the sensing signal, and a second input terminal of the signal processing circuit is configured to receive a reference voltage signal and selectively coupled to at least one of first electrodes and second electrodes of the touch sensing trace, such that the second input terminal synchronously receives the reference voltage signal and the noise signal associated with the touch sensing trace. | 09-12-2013 |
20130232286 | OUTPUT INPUT CONTROL APPARATUS AND CONTROL METHOD THEREOF - An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage. | 09-05-2013 |
20130201079 | SIGNAL TRANSMISSION SYSTEMS OF ELECTRONIC DISPLAY DEVICES AND TRANSMISSION METHODS - A signal transmission system of electronic display devices includes a plurality of electronic display devices and a wireless signal transmission device. The wireless signal transmission device broadcasts a first packet data to the electronic display device. The first packet data comprises an access control address list, and the access control address list comprises the MAC address of a first group of electronic display device. When the wireless signal transmission device receives an acknowledgement (ACK) message from at least a first electronic display device of the first group of electronic display devices, the wireless signal transmission device changes the method of transmission from broadcast to unicast in order to transmit second packet data to the first electronic display device, wherein the second packet data comprises video packet data. | 08-08-2013 |
20130176277 | TOUCH SENSING DEVICE - A touch sensing device includes a touch sensing trace layout, a comparator and a variable capacitor unit. The touch sensing trace layout performs a sensing operation according to at least one first driving signal in a sensing state. An input of the comparator is electrically coupled to the touch sensing trace layout for receiving a sensing signal outputted by the touch sensing trace layout. The variable capacitor unit is selectively coupled to one of the inputs of the comparator, for correspondingly performing potential compensation to the sensing signal received by the input of the comparator according to at least one second driving signal. | 07-11-2013 |
20130147759 | TOUCH SENSING METHOD AND TOUCH SENSING APPARATUS OF CHARGE DISTRIBUTION TYPE - A touch sensing method of charge distribution type is disclosed. Firstly, charges in a panel are removed. Next, a scanning signal is provided to scan a plurality of sensing regions of the panel. Subsequently, the panel is set in a first switching mode for charging the panel with the scanning signal. Thereafter, the panel is set in a second switching mode for modifying a distribution of charges injected into the panel. Next, an equivalent voltage is acquired after the charges are distributed at an equilibrium state. Furthermore, a touch sensing apparatus with charge distribution type is provided herein. | 06-13-2013 |
20130097363 | MEMORY CONTROL DEVICE - A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal. | 04-18-2013 |
20130075829 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode. | 03-28-2013 |
20130073810 | Memory Sharing Between Embedded Controller and Central Processing Unit Chipset - An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals. | 03-21-2013 |
20130009218 | METAL OXIDE SEMICONDUCTOR FIELD TRANSISTOR - A metal oxide semiconductor field transistor including a source region, a drain region, a gate and a gate dielectric layer is provided. The drain region is located in a substrate. The drain region has an elliptical spiral shape and a starting portion of the drain region is strip or water drop or has a curvature of 0.02 to 0.0025 [1/um]. The source region located in the substrate is around the drain region. The gate is located above the substrate and between the source region and the drain region. The gate dielectric layer is located between the gate and the substrate. | 01-10-2013 |
20120329385 | WIRELESS COMMUNICATION METHOD - A wireless communication method is provided, and the method includes the following steps. After a first wireless communication device is powered on, an environment background signal is detected. The detected environment background signal is used to generate a random number to serve as an identity. The first wireless communication device searches for a second wireless communication device, and when the first wireless communication device has found the second wireless communication device, an identity matching procedure is executed by using the identity. After executing the identity matching procedure, wireless communication between the first and the second wireless communication devices is performed. | 12-27-2012 |
20120275072 | POWER MANAGEMENT CIRCUIT AND HIGH VOLTAGE DEVICE THEREIN - A high voltage device includes a high voltage transistor and a protection device. The high voltage transistor has a first end and a second end, in which the first end is coupled to a voltage input/output terminal. The protection device is coupled between the second end of the high voltage transistor and a ground terminal, and has a parasitical equivalent circuit. When the voltage input/output terminal is charged based on positive ESD charges, the current corresponding to the positive ESD charges flows from the voltage input/output terminal through the high voltage transistor and the equivalent circuit in the protection device toward the ground terminal. A power management circuit is also disclosed herein. | 11-01-2012 |
20120239848 | MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE - An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met. | 09-20-2012 |
20120209449 | PROCESSOR TEMPERATURE CONTROL - A method of controlling cooling of a processor, including monitoring at least one parameter of a current status of the processor and determining in which of a plurality of value ranges the at least one parameter of the current status of the processor is located. If the at least one parameter is located in a first range, determining a first desired value for a cooling parameter, based on the processor temperature, using a first method, determining a second desired value for the cooling parameter, based on the processor temperature, using a second method, in which the value of the cooling parameter increases, in a manner indicating more cooling, from a low value for a low processor temperature to a higher value for a higher processor temperature and selecting a value of the cooling parameter as a function of the first and second desired values. If the at least one parameter is located in a second range, selecting a value of the cooling parameter of the processor using a third method, based on the processor temperature. Further controlling a cooling unit of the processor according to the selected value of the cooling parameter; and repeating periodically the monitoring, range determination, value selection and controlling. | 08-16-2012 |
20120194454 | FINGER TILT DETECTION IN TOUCH SURFACE-BASED INPUT DEVICES - An input device includes a touch sensor and a processing unit. The touch sensor has a surface and is configured to sense an imprint of a finger that touches the surface. The processing unit is configured to calculate a tilt of the finger relative to the surface by measuring a shift of the imprint sensed by the touch surface, and to produce an output based on the tilt. | 08-02-2012 |
20120166826 | BUS-HANDLING - A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state. | 06-28-2012 |
20120150467 | POWER EFFICIENT CAPACITIVE DETECTION - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 06-14-2012 |
20120146721 | VOLTAGE DETECTION CIRCUIT - A voltage detection circuit including a comparator circuit, a tunable gain circuit and a switch circuit is disclosed. The comparator circuit has a first input terminal and a second input terminal. The tunable gain circuit is coupled between the first input terminal and a reference signal. The tunable gain circuit has a plurality of gain configurations. The tunable gain circuit adjusts the reference signal and transmits the adjusted reference signal to the first input terminal. The switch circuit selectively transmits a signal under test or the reference signal to the second input terminal. When the voltage detection circuit is in an auto-trimming mode, the switch circuit transmits the reference signal to the second input terminal and the tunable gain circuit sequentially adopts the gain configurations until the comparator circuit detects that voltage levels of the first input terminal and the second input terminal are substantially equal. | 06-14-2012 |
20120133376 | Sensing Device and Method - A sensing device includes an oscillator, a driver, a switch, a counter and a timer. The oscillator includes an input coupled to a reference capacitor. The driver alternately sources and sinks current in accordance with an oscillation signal outputted by the oscillator. The switch connects or disconnects the reference capacitor with a sensing capacitor. The counter counts value for the oscillation signal. The timer counts operation periods respectively when the switch connects the reference capacitor with the sensing capacitor and when the switch disconnects the reference capacitor with the sensing capacitor, and the counter counts values corresponding to conditions of the switch connecting and disconnecting the reference capacitor with the sensing capacitor during the operation periods, respectively. | 05-31-2012 |
20120068985 | CHIP AND COMPUTER SYSTEM - A computer system is provided. The computer system comprises system and peripheral hardware devices, a display device and a chip. The display device comprises a display panel and an on-screen display (OSD) control module. The chip comprises a computer system environment information monitoring module, a control connection interface and a control module. The computer system environment information monitoring module monitors computer system environment information according to the system and peripheral hardware devices. The control connection interface is electrically connected to the OSD control module. The control module is electrically connected to the computer system environment information monitoring module and the control connection interface to control the OSD control module through the control connection interface according to the computer system environment information to further control the display function of the display panel. | 03-22-2012 |
20110274290 | FAST START-UP CIRCUIT FOR AUDIO DRIVER - A driver device for suppression audible transients of an audio amplifier includes an amplifier for receiving an audio signal and a bias circuit configured to quickly generate a voltage level for biasing the amplifier, wherein the voltage level is maintained even if the driver device is powered off. The bias circuit may include a CMOS inverter having a negative feedback that has a standby current of less than 100 nA. The bias circuit further includes a buffer for rapidly charging an external capacitor. The buffer may change to a high impedance state rapidly when the power supply is disconnected. | 11-10-2011 |
20110254817 | DISPLAY, CONTROL CIRCUIT THEREOF, AND METHOD OF DISPLAYING IMAGE DATA - A method of displaying image data includes the steps as follows. Image data with various data bits are transmitted, and one of the image data is selectively received and processed to output N-bit image data, where 010-20-2011 | |
20110239033 | Bus Interface and Clock Frequency Control Method of Bus Interface - A bus interface includes a chip select terminal, a first transmission bus terminal, a second transmission bus terminal, and a clock control device. The chip select terminal transmits a chip select signal to start the data transmission. When the data transmission starts, the first transmission bus terminal sends data to the second device, and the second transmission bus terminal sends the data from the second device to the first device. The clock control device includes a frequency processing unit and a transmission clock generating unit. The frequency processing unit outputs a clock control signal when a frequency to set value changes. The transmission clock generating unit receives the clock control signal and generates a transmission clock in accordance with the frequency setting value. | 09-29-2011 |
20110221452 | CAPACITIVE SENSOR AND SENSING METHOD - A capacitive sensing method is provided. The capacitive sensing method includes the step of alternately charging/discharging a capacitive sensing electrode of a capacitive sensor for predetermined times under an active mode and charging/discharging the capacitive sensing electrode during a fixed period under a standby mode while an object is not coupled to the capacitive sensing electrode, in which the capacitive sensing electrode has a first capacitance while the object is not coupled to the capacitive sensing electrode. The capacitive sensing method also includes the step of generating a switch signal while the object is coupled to the capacitive sensing electrode under the standby mode such that the capacitive sensing electrode has a second capacitance larger than the first capacitance and the step of switching the standby mode to the active mode according to the switch signal. | 09-15-2011 |
20110216038 | SYSTEMS AND METHODS FOR DETECTING MULTIPLE TOUCH POINTS IN SURFACE-CAPACITANCE TYPE TOUCH PANELS - Surface-capacitance-based multi-touch touch panel apparatus including a multiplicity of electrically conductive shapes e.g. diamonds arranged along at least one of rows and columns whose capacitance is measured by capacitive sensors; wherein the rows and columns include a set of linear arrays including at least one individual linear array which includes a plurality of first sets of shapes, each first set including n>=1 shapes all shorted to a single set-specific capacitive sensor such that no two first sets are both shorted to a common capacitive sensor. | 09-08-2011 |
20110157083 | RESISTIVE TOUCH APPARATUS - The subject matter discloses an apparatus, comprising a first resistive sheet and a second resistive sheet disposed in proximity to the first resistive sheet, such that pressure applied at a first touch point and at a second touch point on the first resistive sheet causes flow of electrical current between the first resistive sheet and the second resistive sheet. The apparatus further comprises a control unit coupled to a first terminal and to a second terminal, and configured to measure a first resistance between the first terminal and the second terminal; and configured to estimate a distance between the first touch point and the second touch point. The apparatus further estimates the location of the first touch point and the second touch point. | 06-30-2011 |
20110135103 | System and Method for Audio Adjustment - A system and a method for audio adjustment are provided. The method includes following steps. A first output audio signal generated from the under-test audio playback device according to a frequency response test signal is received. The first output audio signal is analyzed to generate a set of suggested equalization parameter. A set of equalization parameters are adjusted according to the suggested equalization parameters, and a sound test signal is generated from an original sound signal according to the equalization parameters and output to the under-test audio playback device. A second output audio signal is generated from the under-test audio playback device in response to the sound test signal. Whether the auditory effect of the second output audio signal is close to the original sound signal or matches the user's need is determined. The equalization parameters are adjusted when the auditory effect of the second output audio signal is not close to the original sound signal or the user is not satisfied with the auditory effect. | 06-09-2011 |
20110128658 | ESD PROTECTION APPARATUS AND ESD DEVICE THEREIN - An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein. | 06-02-2011 |
20110121394 | CHIP AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE THEREOF - An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions. | 05-26-2011 |
20110102476 | DRIVER OF FIELD SEQUENTIAL DISPLAY AND DRIVING METHOD THEREOF - A driver of a field sequential display is provided. The driver includes a first power device, a second power device, and a driving waveform generator. The first power device generates a first power when the field sequential display is in a color mode. The second power device generates a second power when the field sequential display is in a monochrome mode. The voltage and current of the second power are respectively smaller than the voltage and the current of the first power. The driving waveform generator coupled to the first power device and the second power device and generates a plurality of scan signals and a plurality of display signals according to the first power or the second power, so as to drive a display panel of the field sequential display. | 05-05-2011 |
20110007019 | SYSTEMS AND METHODS FOR USING TFT-BASED LCD PANELS AS CAPACITIVE TOUCH SENSORS - A display screen system operative in the presence of backlight, which may be provided by a rear light source or by a mirror according to reflective LCD technologies, to identify presence of a conductive member such as a finger, the system comprising a structural, transparent planar element including an array of structural, planar conductive areas independently electrically addressable by a source of electric power, each conductive area having a plurality of transparency states controlled by said source of electric power; and capacitance sensing circuitry operative to sense capacitance of at least one of said conductive areas. | 01-13-2011 |
20100324841 | Capacitive Detection Systems, Modules and Methods - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area. | 12-23-2010 |
20100302198 | Power Efficient Capacitive Detection - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 12-02-2010 |
20100265218 | DRIVING METHOD OF FIELD SEQUENTIAL DISPLAY - A driving method of a field sequential display apparatus is provided. First, a plurality of scan lines of the field sequential display apparatus are sequentially driven according to a scanning sequence in a first period of a first field, wherein the first field is in a first frame. Next, the scan lines are sequentially driven according to an opposite sequence in a second period of the first field, wherein the opposite sequence is in the reverse order of the scanning sequence. Finally, the scan lines are simultaneously driven or not driven in a third period of the first field. Consequently, the disclosed driving method can promote the uniformity of the image brightness. | 10-21-2010 |
20100246049 | COMPUTER HAVING FUNCTION FOR DISPLAYING STATUS OF OPERATION AND FLOPPY MODULE - A floppy module includes a floppy disk controller (FDC), a control circuit, and a display. The FDC has a first control terminal, a second control terminal, and a plurality of third control terminals. Wherein, the first control terminal and the second control terminal may respectively output a first control signal and a second control signal, and the first and second control signals having the same statuses are used for controlling a floppy disk. The display has a fourth control terminal and a plurality of data terminals respectively coupled to a portion of the third control terminals. Additionally, the control circuit may use the first control signal to replace the second control signal for controlling the floppy disk, and transmit the second control signal to the fourth control terminal such that a status information is shown on the display as the floppy disk being idle. | 09-30-2010 |
20100199096 | INTEGRATED CIRCUIT AND MEMORY DATA PROTECTION APPARATUS AND METHODS THEREOF - A memory data protection apparatus including a storage device, a cipher, and a validator is provided. The storage device is embedded in a chip electrically coupled to an external memory for storing an offset value, a signature and a key. The cipher electrically coupled to the storage device and the external memory to receive the key includes an encrypter and a decrypter. The encrypter is capable of executing an encryption to output an encrypted data and an encrypted certified data. The decrypter is capable of executing a decryption to output a decrypted data. The validator electrically coupled to the storage device receives the signature, the offset value and the certified data and determines an access limit of the external memory by validating the certified data with the signature and the offset value. The memory data protection apparatus accesses an original data in the external memory according to the access limit. | 08-05-2010 |
20100185797 | KEYBOARD-MOUSE SWITCH AND SWITCHING METHOD THEREOF - A keyboard-mouse switch is disclosed. The keyboard-mouse switch mentioned above is embedded in a computer apparatus and includes an information monitoring unit, a hot-key look up table and a hot-key identification controller. The information monitoring unit receives input information generated by at least one of a keyboard and a mouse. The hot-key look up table stores at least start up hot-key information. The hot-key identification controller receives the start up hot-key information and the input information. The hot-key identification identifies whether the input information is hot-key information or not and dis/enables the input information to be transmitted to the computer apparatus according to the start up hot-key information and the hot-key information. | 07-22-2010 |
20100176891 | SINGLE-PIN RC OSCILLATOR - Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations. | 07-15-2010 |
20100176787 | POWER CONVERTER - A power converter is provided. The power converter comprises an output pin having an address setting function, for flexibly setting a system management bus (SMBus) slave address. As such, the present invention is adapted for saving the amount of the strapping pins employed in the power converter, and thus saving the IC packaging cost. | 07-15-2010 |
20100148851 | LOW VOLTAGE ANALOG CMOS SWITCH - A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit. | 06-17-2010 |
20100146169 | Bus-handling - A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state. | 06-10-2010 |
20100128899 | LARGE RC TIME-CONSTANT GENERATION FOR AUDIO AMPLIFIERS - A circuit for generating a large RC time-constant includes an input node for receiving an input signal making a transition from a first state to a second state characterized by a first time-constant, and an output node for providing an output signal making a transiting from the first state to the second state in response to the input signal. The circuit also includes a first MOS field effect transistor coupled between the input node and the output node. The circuit further includes a first capacitor coupled between the output node and a ground node. A switch circuit is connected to a gate of the first MOS field effect transistor. The switch circuit is configured to bias the MOS field effect transistor to operate in saturation mode and the transition of the output signal is characterized by a time-constant associated with this large output resistance and the capacitor coupled to the output node. | 05-27-2010 |
20100128898 | METHOD AND APPARATUS FOR OPERATION SEQUENCING OF AUDIO AMPLIFIERS - A circuit, system and method provide the suppression of pop at power up of audio amplifiers. The output driver is tri-stated at power up and is enabled after a predetermined time constant. In one embodiment, the output driver includes a MOS transistor pair connected in a push-pull configuration and switches that are under the control of a delay circuit. the. The output driver and the delay circuit may be part of a power amplifier in an audio system. The delay circuit may be implemented using mixed analog and digital signals or a digital controller configured to receive a clock frequency and execute a machine readable program code. The delay circuit is responsive for the start-up behavior of the audio system. | 05-27-2010 |
20100128401 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND DEVICE - An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided. | 05-27-2010 |
20100127772 | FEEDBACK AMPLIFIER AND AUDIO SYSTEM THEREROF - A feedback amplifier includes an operational amplifier having an input end and an output end. A first resistor is coupled with the input end of the operational amplifier. A second resistor has a first end coupled with the input end of the operational amplifier and a second end coupled with the output end of the amplifier. A voltage divider has a first end being operably coupled with the output end of the operational amplifier and a second end being analog grounded. In an embodiment, the feedback amplifier further includes a first switch coupled to the first end of the voltage divider and the output end of the operational amplifier, and a second switch coupled to an internal node of the voltage divider. In an embodiment, the feedback amplifier is configured to provide attenuation when the first switch is open and second switch is closed. | 05-27-2010 |
20100117687 | TRACK AND HOLD CIRCUITS FOR AUDIO SYSTEMS AND OEPRATIONAL METHODS THEREOF - A track and hold circuit includes an operational amplifier having first and second input ends and first and second output ends. A first capacitor has a first end and a second end operably coupled with the first input end and the first output end of the operational amplifier, respectively, wherein the second end of the first capacitor is switchably coupled with a first input voltage (V | 05-13-2010 |
20100098268 | HIGH-VOLTAGE OUTPUT AMPLIFIER FOR AUDIO SYSTEMS - An amplifier circuit having low-voltage transistors and being configured to operate at a high voltage level is provided. The amplifier circuit includes a driver circuit having a first stage and a second stage connected in series between a power supply and a ground. The driver circuit has a control terminal for receiving a signal for controlling a current flow in the output driver. The amplifier circuit also includes a switch transistor having a drain connected to the power supply, a source connected to the control terminal of the output driver, and a gate. A bias circuit is coupled to the switch transistor. In a first mode of operation, the bias circuit is adapted to turn off the switch transistor, and, in a second mode of operation, the bias circuit is adapted to turn on the switch transistor. The bias circuit is adapted to maintain a gate-to-drain voltage of the switch transistor within a predetermined voltage range. | 04-22-2010 |
20100086121 | METHOD AND SYSTEM FOR SUBSCRIBER LINE INTERFACE CIRCUIT HAVING A HIGH-VOLTAGE MOS LINEFEED CIRCUIT - A subscriber line interface circuit apparatus includes a linefeed circuit and a subscriber line control circuit (SLCC). In an embodiment, the linefeed circuit includes a signal conversion circuit having cross-coupled first and second MOSFETs for providing a differential mode signal and a common mode signal in response to at least a tip signal and a ring signal from the subscriber loop. The linefeed circuit includes a tip control circuit and a ring control circuit, each having two or more MOSFETs. In an embodiment, the SLCC is provided in a single integrated circuit chip and is coupled to the linefeed circuit which isolates the SLCC from the tip or ring signals. The SLCC includes a first and a second differential mode inputs for receiving the differential mode signal, and a common-mode input for receiving the common-mode signal. | 04-08-2010 |
20100026392 | METHOD AND APPARATUS FOR OUTPUT AMPLIFIER PROTECTION - An amplifier circuit includes a first circuit and a second circuit connected in series. The first circuit has a first terminal coupled to a first power supply terminal, a second terminal coupled to an output node, and a control terminal for receiving a first signal for controlling a current flow. The second circuit has a first terminal coupled to the output node, a second terminal couple to a second power supply terminal, and a control terminal for receiving a second signal controlling a current flow in the first circuit. A bias circuit is coupled to the third terminal of the first circuit and is configured to limit a current flow in the first circuit when a voltage at the output node is outside a predetermined voltage range. In an embodiment, the bias circuit includes a plurality of diode devices connected in series and a switch device coupled to the diode devices. | 02-04-2010 |
20100011130 | Non-intrusive debug port interface - A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard. | 01-14-2010 |
20090309880 | DRAWING CONTROL METHOD, DRAWING CONTROL APPARATUS, AND DRAWING CONTROL SYSTEM FOR EMBEDDED SYSTEM - A drawing control method, a drawing control apparatus, and a drawing control system for embedded system are provided. The present invention adopts an independent drawing control apparatus to control a drawing unit to draw a frame, and move the drawn frame to an external frame buffer in advance, and therefore the number of lines that can be drawn is not restricted by the capacity of the memory of the drawing unit. Further, the present invention employs a counter to accumulate a counting number upon each time completion of drawing frame or moving frame. Whenever the counting number is accumulated, the drawing unit is controlled to perform a next stage of frame drawing or frame moving. In this concern, the present invention eliminates the time for external accessing, and thus achieving parallel processing, and instant displaying. | 12-17-2009 |