NATIONAL INSTRUMENTS CORPORATION Patent applications |
Patent application number | Title | Published |
20150339127 | Configuration Change Tracking for Measurement Devices - System and method for configuring a measurement device. An initial configuration of a measurement device may be stored on a storage medium. In response to a change in the configuration of the measurement device, information indicating the change in the configuration may be stored on the storage medium, where the change in the configuration results in a modified configuration. Storing the information indicating the change in the configuration may be repeated one or more times for respective changes. The stored initial configuration and the stored information indicating changes in the configuration may comprise a history of configuration changes for the measurement device which may be useable to perform one or more of: generating a report regarding the measurement device, displaying a history of changes in the configuration of the measurement device, or reverting the measurement device to a previous configuration. | 11-26-2015 |
20150304075 | Time-Domain Mechanism for Computing Error Vector Magnitude of OFDM Signals - A mechanism for determining an error vector magnitude EVM | 10-22-2015 |
20150303936 | Systems and Methods for High Throughput Signal Processing Using Interleaved Data Converters - Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal. | 10-22-2015 |
20150301085 | Automatically Capturing Data Sets of Interest from a Data Acquisition Data Stream - Capturing datasets of interest from a data acquisition data stream. An acquired dataset may be received from a measurement device. The acquired dataset may include measurement data from measurements of one or more physical phenomena acquired by the measurement device, and may be a current dataset in a sequence of datasets acquired by the measurement device. The acquired dataset is buffered, resulting in a buffered dataset. One or more thresholds specifying datasets of interest may be automatically determined based on the buffered dataset or one or more previously acquired datasets. The buffered dataset may be automatically analyzed with respect to the one or more thresholds, and a determination may be made as to whether the buffered dataset is a dataset of interest based on said automatically analyzing. In response to determining that the buffered dataset is a dataset of interest, the buffered dataset may be stored in a storage medium. | 10-22-2015 |
20150286239 | Single-Junction Voltage Reference - A single semiconductor-based junction may be used to create a voltage reference, and temperature compensate the voltage reference, by time-multiplexing the voltage reference between different current drive levels. That is, the value of the current driven through the single junction may be repeatedly varied in a recurring manner. In case the junction is a zener diode, the current may be repeatedly switched between forward and reverse directions. As long as the temperature coefficients (in ppm/° C.) of the different voltages developed responsive to the different currents across the junction are different, a weighting of the different voltage values yield a zero temperature coefficient voltage reference value. To implement a bandgap reference, a single diode-connected bipolar junction transistor may alternately be forward-biased using a first current and at least a second current. A weighting of the (at least) two resulting Vbe (base-emitter voltage) drops may yield a zero temperature coefficient bandgap voltage. | 10-08-2015 |
20150244399 | Ultra-broadband Programmable Hybrid Step Attenuator - Systems and methods for partitioning the frequency spectrum for use in a plurality of function circuits, including step attenuation, phase modulation, and gain amplification functional circuits. A system may include a programmable step attenuator including selection circuitry and functional circuitry. First selection circuitry may include a plurality of outputs and may receive a signal and selectively provide the signal to an output based on the signal's frequency. First circuitry may be coupled to one of the outputs and may operate as a first step attenuator for signals in a first portion of the frequency spectrum. Second circuitry may be coupled to another output and operate as a second step attenuator for signals in a second portion of the frequency spectrum. Second selection circuitry may be coupled to the first and second circuitry and may provide a step attenuated signal from the first or second portion of the frequency spectrum. | 08-27-2015 |
20150226771 | Low Profile Current Measurement Connector - A current measurement connector may include a first part and a second part. Each part may include a mount and a joint. The first and second part may be joined via the respective joints through a current transformer interposed between the first and second parts. The respective mounts may be configured to receive a current from a current source and pass the received current through the current transformer via the first and second parts inducing a current in the current transformer. The induced current may be useable to measure the current from the current source. Methods for fabricating the current measurement connector may include die casting the first and second parts and press fitting the first and second parts at the respective joints through the current transformer. Methods for use may include withstanding a fault current pulse and dissipating heat associated with the pulse via the first and second parts. | 08-13-2015 |
20150161068 | Address Range Decomposition - Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices. | 06-11-2015 |
20150137840 | Solid State Wideband High Impedance Voltage Converter - A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node. | 05-21-2015 |
20150130526 | Compensated Temperature Variable Resistor - A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement DC gain compensation using a programmable variable resistance. A MOS transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations. An integrated CMOS-based variable resistor may be thereby used for an analog adjustable attenuator. Master and slave CMOS transistors may be operated in linear mode, and temperature effects on the linear transistors may be compensated for by using an integral loop controller (current controller) configured around the master MOS transistor. Circuits implemented with the compensated variable resistance have a wide range of adjustment with a control voltage, and may be used in the front-end (circuits) of an oscilloscope or digitizer, or in any other circuit and/or instrumentation benefitting from an adjustable attenuator. | 05-14-2015 |
20150124842 | Lossless Time Based Data Acquisition and Control in a Distributed System - Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network. | 05-07-2015 |
20150103848 | System and Method for Synchronizing a Master Clock Between Networks - Systems and methods for synchronizing clocks across networks using a time-sensitive (TS) network interface controller (NIC). The TS NIC may include a functional unit, a port, a clock, a plurality of input/output queue pairs, and a time stamp unit (TSU). The functional unit may be configured to generate synchronization packets usable by an NTS network timekeeper of a respective NTS network to synchronize the NTS network to the master clock, including using the TSU to generate time stamps for the synchronization packets in accordance with the clock synchronized to the master clock and communicate with the respective NTS network via the port using the corresponding input/output queue pair, including sending the synchronization packets to the NTS network timekeeper of the respective NTS network. | 04-16-2015 |
20150103836 | System and Method for Interoperability Between Multiple Networks - Systems and methods for interoperating between a time-sensitive (TS) network and a non-time-sensitive (NTS) network. The system may include a TS network switch and a TS network interface controller (NIC). Each may have a functional unit. A first port of the TS switch may be coupled to an NTS node of the NTS network and its functional unit may be configured to manage insertion and removal of tags associating packets received from the NTS network with the NTS network. The tagged packets may be forwarded on to the TS NIC via a second port. The functional unit of the TS NIC may be configured to queue tagged packets received from the TS network switch and queue and tag packets destined for the NTS network via the TS network switch. | 04-16-2015 |
20150103828 | Time-Sensitive Switch for Scheduled Data Egress - Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port. | 04-16-2015 |
20150077195 | Ultra-Broadband Diplexer Using Waveguide and Planar Transmission Lines - A hybrid diplexer combining planar transmission line(s) and a waveguide is disclosed. In one embodiment, a diplexer includes first, second, and third ports. The diplexer also includes a first signal path and a second signal path. The first signal path may be used to convey lower frequencies, and may be implemented using planar transmission lines. The second signal path may be used to convey higher frequencies, and may be implemented, at least in part, using a waveguide. The first signal path may be coupled between the first port and the second port, while the second signal path may be coupled between the first port and the third port. In one embodiment, the first signal path may implement a low-pass filter, while the second signal path may implement a high-pass filter. | 03-19-2015 |
20150040100 | Creation and Deployment of RESTful Web Services in a Graphical Programming Language - Method and memory medium for generating a web service. A plurality of graphical data flow programs may be provided, and user input selecting one or more of plurality of graphical data flow programs for inclusion in a web service may be received, The web service may be generated based on the one or more graphical data flow programs. Each graphical data flow program may implement a respective web method, where each web method may implement or request a respective action. The web service may be deployable to a server for hosting, where the web service is invocable over a network to perform the corresponding one or more web methods. | 02-05-2015 |
20150039272 | Integrated Digitizer System with Streaming Interface - A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records. | 02-05-2015 |
20150035515 | DC-to-DC Converter Input Stage with Capacitive Current Limit - A power converter may have an input stage that includes a pair of transformer coils, switching circuitry to energize the pair of transformer coils according to an input supply voltage provided by an input source, and a limiting circuit coupled between the pair of transformer coils to cause the input stage to stop drawing current from the input source once the amount of charge drawn from the input source reaches a specific value. An output stage of the power converter may receive energy from the pair of transformer coils, and convert the received energy into an output supply voltage. The pair of transformer coils may continue providing energy stored in a leakage inductance of the pair of transformer coils to the output stage for at least a period of time, once the limiting circuit has caused the input stage to stop drawing current from the input supply. | 02-05-2015 |
20140359590 | Development and Deployment of Parallel Floating-Point Math Functionality on a System with Heterogeneous Hardware Components - System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program. | 12-04-2014 |
20140359589 | Graphical Development and Deployment of Parallel Floating-Point Math Functionality on a System with Heterogeneous Hardware Components - System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program. | 12-04-2014 |
20140358469 | Extending Programmable Measurement Device Functionality - System and method for extending programmable device functionality while preserving functionality of the device driver and driver IP. User input may be received specifying functionality of custom IP for a programmable measurement device with standard driver IP. The custom IP may be generated accordingly, and may be deployable to the programmable measurement device. During operation the custom IP may communicate directly with the standard driver IP and may provide custom functionality of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement device and the standard device driver. | 12-04-2014 |
20140344614 | Specifying and Implementing Relative Hardware Clocking in a High Level Programming Language - System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion. | 11-20-2014 |
20140306720 | Using a Shared Local Oscillator to Make Low-noise Vector Measurements - Measurements, e.g. S-parameter measurements may be performed by obtaining a complex ratio of at least two signals, using a single signal-receiver while eliminating noise problems traditionally associated with single receiver systems. A Vector Signal Generator (VSG) may be used to generate the input stimulus (signal), making it possible to share the local oscillator (LO) signal of the VSG with a single vector receiver, such that the phase noise of the LO signal is common to both the VSG and the vector receiver. When the stimulus signal from the VSG is observed with the vector receiver, the LO phase noise is unobservable, resulting in a significant reduction of the phase noise in the measured signals in both the numerator and the denominator, which in turn leads to a significant reduction in the phase noise of the ratio while retaining the benefits of a simple, single receiver. | 10-16-2014 |
20140304709 | Hardware Assisted Method and System for Scheduling Time Critical Tasks - A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task. | 10-09-2014 |
20140286382 | Computing I/Q Impairments at System Output Based on I/Q Impairments at System Input - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-25-2014 |
20140285180 | Circuit to Compensate for Inaccuracies in Current Transformers - An improved measurement circuit includes a current transformer and an active feedback circuit operated as a negative resistance that matches the value of the winding resistance of the current transformer. An amplifier in the feedback circuit provides power to drive a secondary current through a sense resistor and the transformer winding resistance, reducing the most significant error source in a current transformer circuit by presenting a negative impedance to the current transformer. Combined with the positive resistance of the transformer's winding, the negative impedance results in a net burden of zero on the current transformer, which eliminates the need for the transformer having to provide power to drive the secondary current. This facilitates the use of smaller transformers while achieving reduced measurement errors. Thus, a single, compact measurement device may be used in a wide range of applications with high measurement performance. | 09-25-2014 |
20140281595 | CONTINUOUS POWER LEVELING OF A SYSTEM UNDER TEST - Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop. | 09-18-2014 |
20140266243 | POWER LEVELING OF A SYSTEM UNDER TEST - Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop. | 09-18-2014 |
20140257735 | CALIBRATION OF MODULAR SYSTEM USING AN EMBEDDED CALIBRATION SIGNAL GENERATOR - A user obtains a set of modules, inserts them into slots of a chassis, and interconnects the modules to form a modular instrument. A signal path extends through the modules. To support calibration of the signal path, a first of the modules (or the chassis or a calibration module) includes a calibration signal generator. A computer directs the first module to apply the calibration signal from the generator to the signal path, and measures the power (or amplitude) of the output of the signal path. The computer reads a factory-measured value A of the calibration signal amplitude from a memory of the first module (or the chassis or the calibration module). The value A and the measured output power of the signal path are used to determine a gain of the signal path. The system compensates for that gain when the signal path is used to measure live operational signals. | 09-11-2014 |
20140247902 | Correction of I/Q Impairments In Transmitters and Receivers - Communication devices and associated methods for reducing I/Q impairments in signals used by the communication devices are described. A transmitter device may perform filtering (or matrix multiplication) on digital I and Q signals to pre-correct them before converting them into analog I and Q signals. The pre-correction may pre-compensate for I/Q impairments which have not been introduced yet, but which will subsequently be introduced during digital-to-analog conversion, I/Q modulation, or other processing that occurs to produce a transmission signal from the original digital I and Q signals. A receiver device may receive a transmission signal, produce digital I and Q signals from the received signal, and perform filtering on the digital I and Q signals to correct I/Q impairments at a plurality of frequency offsets. | 09-04-2014 |
20140244705 | Phase Aligned Interleaved Sampling of Multiple Data Channels - Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample. | 08-28-2014 |
20140241410 | IQ Baseband Matching Calibration Technique - The first and second outputs of a signal generation system are coupled to the first and second inputs of a signal digitizing system via respective electrical conductors. A controller directs the generation system to generate a first calibration signal, and the digitizing system responsively captures a first set of vector samples. The conductors are then reconfigured so they connect the first and second outputs of the generation system respectively to the second and first inputs of the digitization system. The controller then directs the generation system to generate a second calibration signal, and the digitizing system responsively captures a second set of vector samples. The controller or other processing agent computes gain and/or phase impairments using the first and second vector sample sets. Digital filter parameters may be computed based on the computed impairment(s), and used to correct the impairment(s) of the generation system and/or the digitizing system. | 08-28-2014 |
20140237483 | Graphical Programming System for Data Sharing between Programs via a Memory Buffer - A graphical program execution environment that facilitates communication between a producer program and a consumer program is disclosed. The producer program may store data in a memory block allocated by the producer program. A graphical program may communicate with the producer program to obtain a reference to the memory block. The graphical program may asynchronously pass the reference to the consumer program, e.g., may pass the reference without blocking or waiting while the consumer program accesses the data in the memory block. After the consumer program is finished accessing the data, the consumer program may asynchronously notify the graphical program execution environment to release the memory block. The graphical program execution environment may then notify the producer program that the block of memory is no longer in use so that the producer program can de-allocate or re-use the memory block. | 08-21-2014 |
20140236517 | Method for Calibrating a Vector Network Analyzer - A method for calibrating a vector network analyzer may include performing a first set of measurements on a first port of a plurality of ports and determining error coefficients for the first port. The error coefficients may be used to obtain a first calibrated port. For an uncalibrated port of the plurality of ports, a connection via a known through between an already calibrated port and the uncalibrated port may be established and a first signal from a first signal source may be applied to the calibrated port and a second signal form a second signal source may be applied to the uncalibrated port. A further set of measurements with respect to the uncalibrated port may be performed and error coefficients may be determined for the uncalibrated port based on the further set of measurements and relation to error coefficients of the calibrated port. | 08-21-2014 |
20140223056 | Controlling Bus Access Priority in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140223055 | Controlling Bus Access in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140214910 | Implementing Modified QR Decomposition in Hardware - System and method for computing QR matrix decomposition and inverse matrix R | 07-31-2014 |
20140207418 | Real-Time Resampling of Optical Coherence Tomography Signals Using a Field Programmable Gate Array - A signal processing system implemented on a Field Programmable Gate Array (FPGA) operates according to a low frequency K-Clock to sample Optical Coherence Topography (OCT) signals, as opposed to relying on a high frequency K-Clock to obtain the same information. A resampler is used to resample the OCT signal uniformly in the optical frequency domain. The resampling may be performed by extracting instantaneous phase information from a low-frequency digitized K-Clock signal, unwrapping the extracted phase information, multiplying the unwrapped extracted phase information with an interpolation factor to obtain recalculated phase information, determining one or more integer crossing points corresponding to the recalculated phase information, and interpolating one or more values of the OCT signal based on the one or more integer crossing points. The integer crossing points may represent points in phase divisible by 360 degrees, within the range of points in phase defined by the recalculated phase information. | 07-24-2014 |
20140204989 | Measuring I/Q Impairments from Sampled Complex Signals - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 07-24-2014 |
20140153664 | Determining Transmitter Impairments Using Offset Local Oscillators - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 06-05-2014 |
20140129752 | Methods for Data Acquisition Systems in Real Time Applications - A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device. | 05-08-2014 |
20140126676 | Estimation of Sample Clock Frequency Offset Based on Error Vector Magnitude - A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/T | 05-08-2014 |
20140122915 | Backplane Clock Synchronization - Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example. | 05-01-2014 |
20140118877 | Programmable Protected Input Circuits - An input protection circuit may include an input node to receive an input signal, and may further include an output node to provide a protected output signal based on the input signal. Protection circuitry may be coupled between the input node and the output node to establish a current path that bypasses the input node and pulls the output pin to a specified reference voltage level in the event of a transient at the input node. A push-pull power supply may be used to provide the reference voltage to the current path, and dissipate any excess voltage by burning it off in a semiconductor device included in the push-pull power supply circuitry. | 05-01-2014 |
20140109096 | Time Monitoring in a Processing Element and Use - System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread | 04-17-2014 |
20140105342 | Frame and Symbol Timing Recovery for Unbursted Packetized Transmissions Using Constant-Amplitude Continuous-Phase Frequency-Modulation - A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data. | 04-17-2014 |
20140101636 | Automated Analysis of Compilation Processes in a Graphical Specification and Constraint Language - When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass. | 04-10-2014 |
20140101347 | Isochronous Data Transfer Between Memory-Mapped Domains of a Memory-Mapped Fabric - Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating. | 04-10-2014 |
20140096108 | Editing a Graphical Data Flow Program in a Web Browser On a Client Computer - System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP. | 04-03-2014 |
20140078683 | High Frequency High Isolation Multichip Module Hybrid Package - In one embodiment, a high frequency module may include a substrate. The substrate may include a first surface and a second surface substantially opposite of the first surface. The high frequency module may include a component coupled to the second surface. A direct current may be provided to the component using the substrate. The high frequency module may include a core coupled to the second surface of the substrate. In some embodiments, the core may include at least one opening extending through the core. The component may be positioned in at least one of the openings. In some embodiments, the high frequency module may include a cover coupled to the core. The component may be positioned in at least one of the openings between the substrate and the cover. | 03-20-2014 |
20140075419 | Sequentially Constructive Model of Computation - System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining. Such techniques may allow validation of a larger set of programs than conventional models while maintaining deterministic results. | 03-13-2014 |
20140075080 | Accumulation of Waveform Data using Alternating Memory Banks - System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms. | 03-13-2014 |
20140075059 | Waveform Accumulation and Storage in Alternating Memory Banks - System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes first and second memory banks. A first waveform is stored in chunks alternating between successive buffers in the first and second memory banks, and concurrently, the first and second chunks may be transferred to first and second FIFOs, respectively, which may be accumulated with respective first and second chunks of a second waveform into the first and second memory banks. This process may be repeated for respective successive pairs of the first and second waveforms, where the first and second memory banks and FIFOs are used in an alternating manner, and further, to accumulate additional waveforms, where previously stored (and accumulated) waveform data are accumulated chunkwise with successive additional waveform data, and where at least some of the accumulation is performed concurrently with waveform data transfers to and from the memory banks and FIFOs. | 03-13-2014 |
20140072026 | Mechanism for Performing Equalization Without Prior Knowledge of Modulation Type or Constellation Order - A system, method and memory medium for performing blind equalization. A block {u | 03-13-2014 |
20140059854 | Crushable Connector Interface - A connector is disclosed. The connector includes a conductive housing. The conductive housing includes a wall region enclosing a space for receiving an adapter. The conductive housing also includes an annular end piece extending radially inward from a first end of the wall region and terminating the space. The annular end piece includes a flat annular surface, and a raised deformable annulus mounted on the flat annular surface. The raised deformable annulus is of a height such that an insertion of the adapter into the space deforms the raised deformable annulus to generate a physical contact connection between the flat annular surface and the adapter. | 03-06-2014 |
20140040855 | Optimization of a Data Flow Program Based on Access Pattern Information - System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information. | 02-06-2014 |
20140040798 | Physics Based Diagram Editor - System and method for editing a graphical diagram. A graphical diagram, such as a graphical program, is displayed on a display device. User input may be received editing the graphical diagram, thereby generating an edited graphical diagram. Placement of one or more elements in the graphical diagram may be adjusted in response to the editing based on determined forces applied to the one or more elements in the edited graphical diagram based on the said editing, resulting in an adjusted edited graphical diagram. The adjusted edited graphical diagram may be displayed on the display device, which may include displaying an animation illustrating the movement of the elements to an equilibrium state in which the forces balance and movement ceases. The editing, adjusting, and displaying may be performed sequentially and/or concurrently, as desired. | 02-06-2014 |
20140040792 | Physics Based Graphical Program Editor - System and method for editing a graphical diagram. A graphical diagram, such as a graphical program, is displayed on a display device. User input may be received editing the graphical diagram, thereby generating an edited graphical diagram. Placement of one or more elements in the graphical diagram may be adjusted in response to the editing based on determined forces applied to the one or more elements in the edited graphical diagram based on the said editing, resulting in an adjusted edited graphical diagram. The adjusted edited graphical diagram may be displayed on the display device, which may include displaying an animation illustrating the movement of the elements to an equilibrium state in which the forces balance and movement ceases. The editing, adjusting, and displaying may be performed sequentially and/or concurrently, as desired. | 02-06-2014 |
20140040241 | Data Rendering With Specified Constraints - System and method for rendering data with specified constraints. A request for data from a data set may be received. The data set may include time-stamped historical data, including multiple reduced data sets, each having a respective resolution. The request may specify a time frame. A first reduced data set of the reduced data sets may be determined based on the specified time frame. First data from the first reduced data set corresponding to the specified time frame may be retrieved, and are usable for display on a display device. The data set may be generated from received raw data, where the raw data includes time-stamped historical data at a first resolution. The raw data may be reduced via multiple stages, thereby generating the reduced data sets at their respective resolutions. The reduced data are generated and represented in a way that is visually pleasing and technically accurate. | 02-06-2014 |
20140019794 | Counter Based Clock Distribution in a Distributed System With Multiple Clock Domains Over a Switched Fabric - System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events. | 01-16-2014 |
20140006860 | Test Executive System With Processing of Results Data in Chunks | 01-02-2014 |
20130332864 | Automatically Determining Data Transfer Functionality For Wires in a Graphical Diagram - Configuring wires/icons in a diagram. The diagram may be an executable diagram such as a graphical program or a system diagram. The diagram may include a plurality of icons that are connected by wires, and the icons may visually represent functionality of the diagram. The diagram may be executable to perform the functionality. Displaying the diagram may include displaying a first wire in the diagram, where the first wire connects a first icon and a second icon. Data transfer functionality may be specified for the first wire and/or the first or second icon in the diagram. The data transfer functionality may be visually indicated in the diagram, e.g., by appearances of the first icon, the second icon, the first wire, and/or icons displayed proximate to these components of the diagram. | 12-12-2013 |
20130262695 | Lossless Data Streaming to Multiple Clients - System and method for streaming data. A host device that includes a server may acquire data from a data source. The server may receive a request for data from at least one client device over a network via a lossless transmission protocol, wherein the request may specify a range of data to stream to the at least one client device. The server may stream the data over the network to the at least one client device via the lossless transmission protocol in accordance with the request. The at least one client device may receive and process the streamed data. | 10-03-2013 |
20130243061 | Mechanism for the Measurement of DC Properties of a Signal Path - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-19-2013 |
20130243060 | Measurement of I/Q Impairments from a Sampled Complex Signal - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-19-2013 |
20130243059 | Mechanisms for Measuring the I/Q Impairments of a Receiver - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-19-2013 |
20130243058 | Mechanism for Measuring Transmitter I/Q Impairments Using Shared Local Oscillators - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-19-2013 |
20130243057 | Mechanism for Measuring Transmitter Impairments Using Offset Local Oscillators - Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system. | 09-19-2013 |
20130232466 | Generating a Hardware Description for a Programmable Hardware Element Based on a Graphical Program Including Multiple Models of Computation - Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program. | 09-05-2013 |
20130230114 | Using Error Vector Magnitude to Estimate Sample Clock Frequency Offset - A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/T | 09-05-2013 |
20130215986 | Blind Estimation of Frequency and Phase Offsets for Received Signals - A mechanism for jointly correcting carrier phase and carrier frequency errors in a demodulated signal. A computer system may receive samples of a baseband input signal (resulting from QAM demodulation). The computer system may compute values of a cost function J over a grid in a 2D angle-frequency space. A cost function value J(θ,ω) is computed for each point (θ,ω) in the grid by (a) applying a phase adjustment of angle θ and a frequency adjustment of frequency ω to the input signal; (b) performing one or more iterations of the K-means algorithm on the samples of the adjusted signal; (c) generated a sum on each K-means cluster; and (d) adding the sums. The point (θ | 08-22-2013 |
20130145312 | Wiring Method for a Graphical Programming System on a Touch-Based Mobile Device - A touch-gesture wiring method for connecting data flow wires to input/output terminals of nodes in a graphical program is described. The method may be implemented by a graphical programming application that executes on a mobile device that includes a touch-sensitive screen configured to receive user input as touch gestures. The method may aid the user by displaying a magnified view of the input/output terminals that makes it easier (relative to the default view of the graphical program) for the user to see the input/output terminals and/or easier to select a desired one of the input/output terminals. | 06-06-2013 |
20130031494 | Type Generic Graphical Programming - A system and method for creating and using type generic graphical programs. The method may include storing a first graphical program on a memory medium. The first graphical program may have been created based on user input. The first graphical program may include a plurality of nodes and interconnections between the nodes, and the plurality of nodes and interconnections between the nodes may be type generic. User input may be received specifying one or more data types of at least one input and/or at least one output of the first graphical program. The data types may be associated with the first graphical program in response to said user input specifying the one or more data types. | 01-31-2013 |