MaxLinear, Inc. Patent applications |
Patent application number | Title | Published |
20150073706 | GPS-ASSISTED SOURCE AND RECEIVER LOCATION ESTIMATION - A mobile communication device includes, in part, a first wireless receiver adapted to determine, as it travels along a path, a multitude of positions of the mobile communication device using signals received from a primary positioning source, a second wireless receiver adapted to receive signals from one or more ambient wireless sources as the mobile communication device travels along the path, and a positioning module. An internal or external memory stores estimated positions and corresponding time references of the signals of the one or more ambient sources. The positioning module uses the data stored in the database to estimate the position of the mobile communication device when no primary positioning source signal is available. The positioning module optionally uses the data stored in the database to improve estimates of the position of the mobile communication device when primary positioning signal is available. | 03-12-2015 |
20150016557 | METHOD AND SYSTEM FOR A LOW-COMPLEXITY SOFT-OUTPUT MIMO DETECTION - An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N | 01-15-2015 |
20140347222 | STEERABLE MICROWAVE BACKHAUL TRANSCEIVER - A first microwave backhaul transceiver may comprise a reflector and a signal processing subassembly. The signal processing subassembly may comprise a plurality of antenna elements positioned at a focal plane of the reflector. The signal processing subassembly may process a plurality of microwave signals corresponding to the plurality of antenna elements using a corresponding plurality of phase coefficients and a corresponding plurality of amplitude coefficients. The signal processing subassembly may adjust a radiation pattern of the plurality of antenna elements during operation of the signal processing subassembly through adjustment of the phase coefficients and/or the amplitude coefficients. | 11-27-2014 |
20140335808 | METHOD AND SYSTEM FOR A CONFIGURABLE LOW-NOISE AMPLIFIER WITH PROGRAMMABLE BAND-SELECTION FILTERS - Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a low-noise amplifier (LNA) with a low pass filter coupled to a first input of the LNA and a high pass filter coupled to a second input of the LNA. The low pass filter and the high pass filter may also be coupled to a signal source input. Signals may be received in a pass band of the high pass filter and a pass band of the low pass filter. Input signals in the pass band of the one filter (but not signals in the pass band of the other filter) may be amplified by coupling the one input of the LNA to ground and coupling the other filter to ground utilizing a shunt resistor. The filters may be configurable and may each comprise at least one inductor and at least one capacitor. | 11-13-2014 |
20140329481 | BAND TRANSLATION WITH PROTECTION OF IN-HOME NETWORKS - Methods and systems are provided for band translation with protection. A signal processing circuitry (chip) may be configured to handle a plurality of signals, comprising at least a first signal corresponding to internal communication within an in-premises network and at least a second signal originating from a source external to the in-premises network; and to process on-chip the plurality of input signals, to generate one or more output signals. In this regard, at least one output signal may comprise components corresponding to the first signal and the second signal; and the processing may be configured to mitigate on-chip, during generating of the one or more outputs, at least one effect of including in the at least one output signal a first component corresponding to one of the first signal and the second signal on a second component corresponding to the other one of the first signal and the second signal. | 11-06-2014 |
20140329477 | HOT-SWAPPABLE HARDWARE FOR WIRELESS MICROWAVE LINKS - Methods and systems are provided for hot-swappable hardware for communication links (e.g., wireless microwave links). A communication assembly that comprises processing circuitry may be configured to allow replacing a circuitry element during active operation of the communication assembly. The replacing may comprise configuring the communication assembly to communicate signals based on a first configuration, using the circuitry element being replaced; receiving addition of a replacement circuitry element; configuring the communication assembly to communicate signals based on a second configuration, using the replacement circuitry element; and after the communication assembly is fully configured to communicate signals based on the second configuration, removing the circuitry element being replaced. | 11-06-2014 |
20140323072 | METHOD AND APPARATUS FOR AN ENERGY-EFFICIENT RECEIVER - One or more circuits may comprise at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC. The circuit(s) may be operable to receive a plurality of signals, each of which may comprise a plurality of channels. The circuit(s) may be operable to digitize a selected one or more of the channels. Which, if any, of the selected channels are digitized via the at least one first-type ADC and which, if any, of the selected channels are digitized via the at least one second-type ADC, may be based on which of the plurality of channels are the selected channels and/or based on power consumption of the circuit(s). A bandwidth of each first-type ADC may be on the order of the bandwidth of one of the received signals. A bandwidth of each second-type ADC may be on the order of the bandwidth of one of the plurality of channels. | 10-30-2014 |
20140320328 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result. | 10-30-2014 |
20140320206 | METHOD AND SYSTEM FOR A PSEUDO-DIFFERENTIAL LOW-NOISE AMPLIFIER AT KU-BAND - Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor. | 10-30-2014 |
20140317294 | BANDWIDTH ALLOCATION FOR SHARED NETWORK INFRASTRUCTURE - Methods and systems are provided for adaptive management of local networks (e.g., in-premises networks, which may access or be connected to cable or satellite networks). A network device (e.g., a gateway device) may be configured to function as a network manager in a local network, to manage internal connections and/or communications within the local network. The managing may comprise assessing effects of the internal connections and/or communications on external connections and/or communications with one or more devices and/or networks external the local network; and setting and/or adjusting based on the assessed effects, one or more communication parameters associated with each one of the internal connections and/or communications. The effects of the internal connections and/or communications may result from utilizing one or more physical mediums that are shared with and/or are commonly used by the external connections and/or communications with one or more devices and/or networks external the local network. | 10-23-2014 |
20140314186 | LOOP-THROUGH FOR MULTI-CHIP COMMUNICATION SYSTEMS - Methods and systems are provided for loop-through for multi-chip communication systems. Receiver circuitry, that is operable to receive one or more input feeds, may comprise a plurality of chips, each of which may be configurable to generate a corresponding output comprising one or more feed elements (e.g., channels) extracted from the input feed(s). However, only a first chip may be operable to handle reception and/or initial processing of the one or more input feeds, with each one of the remaining chips processing a loop-through feed generated by the first chip, in order to generate the corresponding output of that chip. The first chip generates the loop-through feed based on the one or more input feeds, such as after the initial processing thereof in the first chip. Generating the loop-through feed may comprise applying channelization (e.g., separately for each remaining chip), switching based processing, and/or interfacing based processing. | 10-23-2014 |
20140313914 | Coordinated Access and Backhaul Networks - A communications network comprises performance determination circuitry and link control circuitry. The performance determination circuitry is operable to determine performance of a microwave backhaul link between a first microwave backhaul transceiver and a second microwave backhaul transceiver. The microwave backhaul link backhauls traffic of a mobile access link. The link control circuitry is operable to, in response to an indication from the performance determination circuitry that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the mobile access link. The link control circuitry is operable to, in response to the indication that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the backhaul link in combination with the adjustment of the parameter(s) of the access link. | 10-23-2014 |
20140313079 | GPS ANTENNA DIVERSITY AND NOISE MITIGATION - A system and method for improving acquisition sensitivity and tracking performance of a GPS receiver using multiple antennas is provided. In an embodiment, the acquisition sensitivity can be improved by determining the correlation weight of each received path signal path associated with one antenna form a plurality of antennas and then combining the path signals based on their respective correlation weight. In another embodiment, carrier offset correction information of each path signal is individually determined and then summed together to be used for tracking the code phase in a code phase tracking loop. The code phase tracking loop generates an early code and a late code that are used to determine the code phase error. The system includes notch and bandpass filters to mitigate narrowband and broadband noises of a received GPS signal, wherein the digital adaptive filters are switched on periodically or by external events. | 10-23-2014 |
20140313074 | SATELLITE RECEPTION ASSEMBLY INSTALLATION AND MAINTENANCE - A direct broadcast satellite (DBS) reception assembly may receive a desired satellite signal and process the desired satellite signal for output to a gateway. The DBS assembly may also receive one or more undesired satellite signals and determine a performance metric of the one or more undesired satellite signals. The elevation angle of the assembly and/or the azimuth angle of the assembly may be adjusted based on the performance metric(s) of the undesired satellite signal(s). The adjusting of the elevation angle and/or the azimuth angle may comprise electronically steering a directivity of a receive radiation pattern of the DBS reception assembly and/or mechanically steering one or more components of the assembly via motors, servos, actuators, MEMS, and/or the like. The performance metric may be received signal strength of the undesired signals, received signal strength of the desired signal, SNR of the desired signal, and/or SNR of the undesired signals. | 10-23-2014 |
20140301413 | METHOD AND SYSTEM FOR AN ANALOG CROSSBAR ARCHITECTURE - Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer. | 10-09-2014 |
20140301133 | METHOD AND SYSTEM FOR A HIGH-DENSITY, LOW-COST, CMOS COMPATIBLE MEMORY - Methods and systems for a high-density, low-cost, CMOS compatible memory may comprise a memory cell on a chip, the memory cell comprising: a plurality of capacitor/switch pairs, where for each pair comprising a switch and a capacitor, a source terminal of the switch is coupled to a gate terminal of the capacitor. The memory cell may also comprise a reset transistor, a biasing circuit, and a source follower. A drain terminal of each switch may be coupled to a floating node that couples a source terminal of the reset transistor and a gate terminal of the source follower. Drain and source terminals of each of the switches of the plurality of capacitor/switch pairs may be coupled to ground. A number of the plurality of capacitor/switch pairs may indicate a number of bits in the memory. The biasing circuit may comprise a current mirror. A bit-line for the memory cell may be coupled to a source terminal of the source follower. The bit-line may comprise a metal trace. | 10-09-2014 |
20140300501 | MULTI-ZONE DATA CONVERTERS - Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone. | 10-09-2014 |
20140300499 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 10-09-2014 |
20140298396 | Method and Apparatus for Band Separation for Multiband Communication Systems - Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module. The triplexer may comprise a multiband port, a Multimedia Over Coaxial Alliance (MoCA) port, a television upstream port, and a television downstream port. The leakage processing module may comprise a television downstream input port, a cable television downstream output port, a MoCA port, and a cable television upstream port. The leakage processing module may be operable to (1) process a MoCA signal to generate a first compensation signal; (2) process a cable upstream signal to generate a second compensation signal; (3) process a filtered signal based at least in part on the first and second compensation signals; and (4) output the processed filtered signal via the cable television downstream output port of said leakage processing module. | 10-02-2014 |
20140294056 | Low-Complexity Diversity Reception - A system may comprise a plurality of signal processing paths, a bin-wise combiner, an inverse transformation block, and a DAC. Each signal processing path may comprise a transformation block that is operable to transform a first time-domain digital signal to an associated frequency-domain signal having a plurality of subband signals. The bin-wise combiner may be operable to combine corresponding subband signals of the plurality of signal processing paths. The inverse transformation block may be operable to transform output of the bin-wise combiner to an second time-domain signal. The DAC may be operable to converts the second time-domain signal to a corresponding analog signal. | 10-02-2014 |
20140293854 | Method and System for Server-Side Handling of a Low-Power Client in a Wide Area Network - A CMTS may receive a request that a network device be permitted to enter a power-saving mode of operation. In response, the CMTS may enter a power-saving mode of operation wherein MAC management messages, transmission opportunities for the sleeping network device, and/or contention periods on one or more channels occur at independently determinable intervals. The CMTS may then transmit a message granting the network device permission to enter the power-saving mode of operation. The CMTS may start a sleep timer upon transmitting the MAC management message and may deregister the network device if no communication is received from the network device prior to expiration of the sleep timer. The CMTs may buffer traffic destined for the network device in a buffer of the CMTS while the network device is in the power-saving mode of operation, and may wake the network device upon the amount of buffered traffic reaching a threshold. | 10-02-2014 |
20140292548 | SYSTEM AND METHOD FOR LOW-POWER DIGITAL SIGNAL PROCESSING - A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal. | 10-02-2014 |
20140289769 | Method and Apparatus for Communicating Electronic Service Guide Information in a Satellite Television System - Aspects of a method and apparatus for communicating electronic service guide information in a satellite television system are provided. A satellite communication system may receive a signal via an interface to a satellite dish, and receive data from a network via a second interface (e.g., an interface to a LAN or a WAN, such as the Internet). The satellite communication system may be operable to channelize the received satellite signal into a plurality of channels, wherein a first channel of the plurality of channels carries electronic service guide (ESG) data. The satellite communication system may select which of the plurality of channels to input to a demodulator based, at least in part, on whether ESG data is available via the second interface. A second channel carrying media data may be input to the demodulator while the ESG data is available via the second interface. | 09-25-2014 |
20140286447 | PEAK TO AVERAGE POWER RATIO SUPPRESSION - A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria. | 09-25-2014 |
20140274134 | METHOD AND SYSTEM FOR AN INTERNET PROTOCOL LNB SUPPORTING POSITIONING - An Internet protocol low noise block downconverter (IP LNB) assembly, which may be within a satellite reception assembly, may be operable to determine location information and/or time information of the IP LNB assembly, such as via a global navigation satellite system (GNSS) module in the IP LNB assembly. The IP LNB assembly may provide services based on the determined location information and/or the determined time information of the IP LNB assembly. The IP LNB assembly may communicate the determined location information and/or the determined time information to a wireless communication device for determining location information of the wireless communication device. The IP LNB assembly may determine location information of a wireless source device based on a signal received from the wireless source device, the determined location information and the determined time information of the IP LNB assembly. | 09-18-2014 |
20140256362 | METHOD AND SYSTEM FOR GLOBAL NAVIGATION SATELLITE SYSTEM CONFIGURATION OF WIRELESS COMMUNICATION APPLICATIONS - Methods and systems for global positioning navigate satellite system configuration of wireless communication applications may comprise in a wireless communication device (WCD) comprising a satellite positioning RF path, determining a location of the WCD utilizing LEO signals received by said satellite positioning RF path, establishing communications with a wireless access point based on the determined location, and configuring a wireless communication function of the WCD based on the determined location. The wireless communication function may comprise a power level of wireless local area network circuitry in the WCD, a point-of-sale transaction, or a synchronization of data on the WCD with one or more devices in a home location of the WCD. The determined location and a transaction ID for the point-of-sale transaction may be stored utilizing a security processor in the WCD. The satellite positioning RF path may be powered down based on the determined location. | 09-11-2014 |
20140245059 | HYBRID REDUNDANCY FOR ELECTRONIC NETWORKS - Aspects of a method and system for hybrid redundancy for electronic networks are provided. A first line card may comprise a first instance of a network layer circuit, a first instance of a physical layer circuit, and an interface to a data bus (e.g., an Ethernet bus) for communicating with a second line card. In response to detecting a failure of the first instance of the network layer circuit, the first instance of the physical layer circuit may switch from processing of a signal received via the first instance of the network layer circuit to processing of a signal received via the interface. The system may comprise a second line card. The second line card may comprise a second instance of the network layer circuit. The second instance of the network layer circuit may be coupled to the data bus. | 08-28-2014 |
20140218235 | INTERMITTENT TRACKING FOR GNSS - A GNSS system operates intermittently and has adaptive activity and sleep time in order to reduce power consumption. The GNSS system provides an enhanced estimate of its position in the absence of GNSS signals of sufficient strength. The user's activity and behavior is modeled and used to improve performance, response time, and power consumption of the GNSS system. The user model is based, in part, on the received GNSS signals, a history of the user's positions, velocity, time, and inputs from other sensors disposed in the GNSS system, as well as data related to the network. During each activity time, the GNSS receiver performs either tracking, or acquisition followed by tracking The GNSS receiver supports both normal acquisition as well as low-power acquisition. | 08-07-2014 |
20140201801 | FLEXIBLE CHANNEL STACKING - A receiver includes a plurality of input paths for receiving and processing a plurality of input RF signals. The input paths isolate one or more portions of corresponding ones of the received input RF signals, and combine the isolated portions of the corresponding ones of the received input RF signals onto one or more output signals. A bandwidth of the isolated portions of the corresponding ones of the received input RF signals and a bandwidth of the output signals are variable. The isolated portions of the corresponding ones of the received plurality of input RF signals are extracted and utilized to generate the output signals. The portions of the corresponding ones of the received plurality of input RF signals may be mapped into one or more channel slots in the time domain. The channel slots may be assigned in the frequency domain to one or more frequency bins. | 07-17-2014 |
20140201594 | Low-Power Low Density Parity Check Decoding - In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node. | 07-17-2014 |
20140201593 | Efficient Memory Architecture for Low Density Parity Check Decoding - A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. | 07-17-2014 |
20140201089 | COMMUNICATIONS SYSTEMS AND METHODS - Various aspects of a method and system for electronics lifetime wear monitoring are provided. Various aspects of a method and system for scheduling various maintenance-related activities based, at least in part, on circuit monitoring are also provided. | 07-17-2014 |
20140199081 | Feedback-Based Configuration of a Hybrid Fiber-Coaxial Network - Circuitry of a fiber node which is configured to couple to an optical link and an electrical link may comprise an electrical-to-optical conversion circuit for transmitting on the optical link. The circuitry may be operable to receive signals via the optical link. The circuitry may select between or among different configurations of the electrical-to-optical conversion circuit based on the signals received via the optical link. The signals received via the optical link may be intended for one or more gateways served by the fiber node or may be dedicated signals intended for configuration of the circuitry. The circuitry may be operable to generate feedback and insert the feedback into a datastream received from one or more gateways via the electrical link prior to transmitting the datastream onto the optical link. | 07-17-2014 |
20140199080 | ADVANCED FIBER NODE - Circuitry of a hybrid fiber-coaxial network may comprise a first transceiver configured to connect the circuitry to an optical link, a second transceiver configured to connect the circuitry to an electrical link, a first processing path, a second processing path, and a switching circuit. In a first configuration, the switching circuit may couple the first transceiver to the second transceiver via the first processing path. In a second configuration, the switching circuit may couple the first transceiver to the second transceiver via the second processing path. The first transceiver may comprise a passive optical network (PON) transceiver and the second transceiver may comprise a data over coaxial service interface specification (DOCSIS) physical layer transceiver. The switching circuit may be configured based on the type of headend to which the circuitry is connected. | 07-17-2014 |
20140199077 | Multi-Mode Fiber Node - In a first configuration, circuitry of a fiber node may be configured to modulate an optical carrier by an analog upstream electrical signal received via the electrical network. In a second configuration, the circuitry may be configured to digitize the analog upstream electrical signal to generate a digitized upstream signal, and modulate the optical carrier with the digitized upstream signal. An optical receiver of the fiber node may be configured to convert a downstream optical signal to a downstream electrical signal. In the first configuration, the downstream electrical signal may be a first analog signal and the circuitry may be configured to output the first analog signal into the electrical network. In a third configuration, the downstream electrical signal is a digitized waveform and the circuitry is configured to convert the digitized waveform to a second analog signal and output the second analog signal into the electrical network. | 07-17-2014 |
20140198828 | FREQUENCY SPREADING FOR HIGH-PERFORMANCE COMMUNICATIONS - Methods and systems are provided for using frequency spreading during communications, in particular communications in which multiple carriers (or subcarriers) are used. The frequency spreading may comprise generating a plurality of spreading data vectors based on transmit data, such as by application of a spreading matrix to portions of the transmit data. Each spreading data vector may comprise a plurality of elements, for assignment to the multiple subcarriers. The receive-side device may then apply frequency de-spreading, to obtain the original transmit data. The frequency de-spreading may comprise use of the same spreading matrix on data extracted from received signals, which (the data) may correspond to the plurality of spreading data vectors. | 07-17-2014 |
20140198597 | DYNAMIC RANDOM ACCESS MEMORY FOR COMMUNICATIONS SYSTEMS - An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit. | 07-17-2014 |
20140198258 | METHOD AND SYSTEM FOR DIVERSITY COMBINING FOR HIGH-PERFORMANCE SIGNAL RECEPTION - A terrestrial receiver at a premises includes a plurality of antennas and a corresponding plurality of tuners. The terrestrial receiver receives terrestrial television signals via the plurality of antennas and the plurality of tuners and diversity combines a corresponding plurality of terrestrial television channels within the received terrestrial television signals, for example, based on control signals received from one or more customer premises equipment (CPE). The terrestrial receiver processes the diversity combined corresponding plurality of terrestrial television channels and communicates the processed and diversity combined corresponding plurality of terrestrial television channels to the one or more CPE. The diversity combined corresponding plurality of terrestrial television channels may be remodulated, and converted to corresponding analog signals prior to being communicated to the one or more CPE. The diversity combined corresponding plurality of terrestrial television channels may be demodulated and converted to intermediate frequency signals prior to being communicated to the one or more CPE. | 07-17-2014 |
20140197986 | SATELLITE RECEPTION ASSEMBLY WITH PHASED HORN ARRAY - A direct-to-home satellite outdoor unit may comprise a reflector, a support structure, circuitry, and an array of antenna elements mounted to the support structure such that energy of a plurality of satellite beams is reflected by the reflector onto the array where the energy is converted to a plurality of first signals. The circuitry may be operable to process the first signals to concurrently generate a plurality of second signals, each of the second signals corresponding to a respective one of the plurality of satellite beams. The circuitry may be operable to process one or more of the second signals for outputting content carried in the one or more of the second signals onto a link to an indoor unit. | 07-17-2014 |
20140173640 | TARGETED ADVERTISEMENT IN THE DIGITAL TELEVISION ENVIRONMENT - A method for targeted advertisement includes storing a profile tag associated with each user in a device maintained by that user. Each profile tag includes the demographic information of its associated user. A multitude of target tags are also transmitted to the users. Each target tag is associated with an advertiser and includes the demographic information of the users. The advertisements and their corresponding target tags are transmitted and cached in the devices maintained by the users. The number of matches between the target tags and the user profiles are supplied to their respective advertisers. The advertisers use the matching number to modify the prices they are willing to offer for the commercial break. The target tags include information that is used to select one of the cached advertisement for playing during the commercial break. | 06-19-2014 |
20140155009 | CRYSTAL CONTROL SCHEME TO IMPROVE PERFORMANCE OF A RECEIVER - A circuit includes, in part, a receiver, a received signal strength indicator (RSSI), and an oscillator. The receiver receives an incoming signal and an oscillating signal. The RSSI is responsive to the receiver and generates an output signal representative of the strength of the incoming signal. The oscillator receives different biasing conditions in response to different outputs of the RSSI. The oscillator generates the oscillating signal received by the receiver. The oscillator receives a first biasing condition when the incoming signal is detected as having a strength lower than or equal to a predetermined threshold value and a second biasing condition when the incoming signal is detected as having a strength higher than the predetermined threshold value. The first biasing condition may be defined by a first current, and the second biasing condition may be defined by a sum of the first current and a second current. | 06-05-2014 |
20140109163 | FAST RESYNCHRONIZATION FOR RECEPTION IN TIME SLICING - A method and an apparatus for achieving fast resynchronization of received signals in a time slice in DVB-T/H systems. When the clock drift is low, the location of the symbol window can be decided based on a previous time slice. When the clock drift is high and when there are large delay spreads, the location of the symbol window can be decided based on the detected scattered pilot positions. The placement of the symbol window can further be enhanced through processing of the received TPS bits. | 04-17-2014 |
20140106696 | DYNAMIC BANDWIDTH CONTROL SCHEME OF A FRAC-N PLL IN A RECEIVER - A receiver includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired signals that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to the feedback signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer. | 04-17-2014 |
20140105339 | SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING - A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry. | 04-17-2014 |
20140104499 | WIDEBAND TUNER ARCHITECTURE - A wideband receiver system is provided to concurrently receive multiple RF channels including a number of desired channels that are located in non-contiguous portions of a radio frequency spectrum and to group the number of desired channels into a contiguous frequency band. The system includes a wideband receiver having a complex mixer for down-shifting the multiple RF channels and transforming them to an in-phase signal and a quadrature signal in the baseband. The system further includes a wideband analog-to-digital converter module that digitizes the in-phase and quadrature signals and a digital frontend module that transforms the digital in-phase and quadrature signals to baseband signals that contains only the number of desired RF channels that are now located in a contiguous frequency band. An up-converter module up-shifts the baseband signals to a contiguous band in an IF spectrum so that the system can directly interface with commercially available demodulators. | 04-17-2014 |
20140089961 | METHOD AND SYSTEM FOR AN INTERNET PROTOCOL LNB SUPPORTING POSITIONING - An Internet protocol low noise block downconverter (IP LNB) assembly, within a satellite reception assembly, may be operable to determine location information and/or time information of the IP LNB assembly, via a global navigation satellite system (GNSS) module in the IP LNB assembly. The IP LNB assembly may provide services based on the determined location information and/or the determined time information of the IP LNB assembly. The IP LNB assembly may communicate the determined location information and/or the determined time information to a wireless communication device for determining location information of the wireless communication device. The IP LNB assembly may determine location information of a wireless source device, based on the determined location information and the determined time information of the IP LNB assembly along with a plurality of other location information and a plurality of corresponding other time information associated with a plurality of other IP LNB assemblies. | 03-27-2014 |
20140077981 | METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY - Methods and systems are provided for calibrating nonlinearity correction during analog-to-digital conversions on received analog signals. Correction-parameters may be estimated, such as to reduce, when applied to total spectral content, distortion resulting from the nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity correction calibration may be performed during reception and handling of the analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. | 03-20-2014 |
20140064420 | Method and System for Power Management in a Network Device Based on Multi-protocol Detection - A network device may comprise one or more circuits including a clock signal generator, an ADC, and a processor. The ADC may digitize a received signal across a range of frequencies that encompasses a first band of frequencies used for a first network and a second band of frequencies used for a second network. A sampling frequency of the ADC may be determined by a frequency of a clock signal output by the clock signal generator. The processor may determine whether the first network is active and whether the second network is active. The processor may configure the clock generator such that, when both of the first network and the second network are active, the clock signal is set to a first frequency, and when the first network is active and the second network is inactive, the clock signal is set to a second frequency. | 03-06-2014 |
20140056316 | METHODS AND APPARATUS FOR INTELLIGENT POWER REDUCTION IN COMMUNICATIONS SYSTEMS - Methods and apparatus for power control in a communications device are described. Bonding of channels in a modem may be dynamically adjusted responsive to user activity or demand for bandwidth. Bonded channel Configurations may be adjusted to single channel configurations for low power operation. Modem configuration may be dynamically adjusted so as to maintain only required synchronization and system information to facilitate rapid data transfer resumption upon demand. | 02-27-2014 |
20140050288 | APPARATUS & METHODS FOR SYMBOL TIMING ERROR DETECTION, TRACKING AND CORRECTION - Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks. | 02-20-2014 |
20140049331 | TCXO REPLACEMENT FOR GPS - To determine the level of frequency drift of a crystal oscillator as a result of a change in the its temperature, the temperature of the crystal oscillator is sensed and used together with previously stored data that includes a multitude of drift values of the frequency of the crystal oscillator each associated with a temperature of the crystal oscillator. Optionally, upon initialization of a GPS receiver in which the crystal oscillator is disposed, an initial temperature of the crystal oscillator is measured and a PLL is set to an initial frequency in association with the initial temperature. When acquisition fails in a region, the ppm region is changed. The temperature of the crystal oscillator is periodically measured and compared with the initial temperature, and the acquisition process is reset if there is a significant change in temperature. The GPS processor enters the tracking phase when acquisition is successful. | 02-20-2014 |
20140043175 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) - An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | 02-13-2014 |
20140037030 | GAIN PARTITIONING IN A RECEIVER - An automatic gain control loop disposed in a receiver is adapted to compensate for varying levels of out of band interference sources by adaptively controlling the gain distribution throughout the receive signal path. One or more intermediate received signal strength indicator (RSSI) detectors are used to determine a corresponding intermediate signal level. The output of each RSSI detector is coupled to an associated comparator that compares the intermediate RSSI value against a corresponding threshold. The take over point (TOP) for gain stages is adjusted based in part on the comparator output values. The TOP for each of a plurality of gain stages may be adjusted in discrete steps or continuously. | 02-06-2014 |
20140029703 | I/Q CALIBRATION TECHNIQUES - A receiver includes a static I/Q calibration block and a correlation/integration block. The static I/Q calibration block is configured to substantially eliminate mismatches between in-phase and quadrature components of a portion of the spectrum having associated I/Q mismatches that are relatively frequency-independent. The correlation/integration block is configured to substantially eliminate mismatches between the in-phase and quadrature components of portions of the spectrum having associated I/Q mismatches that are relatively frequency-dependent in accordance with a pair of signals generated by the static I/C calibration block. | 01-30-2014 |
20140026176 | NOISE SUPPRESSION IN A HYBRID FIBER COAXIAL NETWORK - A coupling device for use in a hybrid fiber coaxial (HFC) network may be configured to disable an upstream path through it when there is only noise incident on the upstream path, and enable the upstream path through it when a desired transmission from a cable modem downstream of the coupling device is incident on the upstream path. The coupling device may be a trunk amplifier, a distribution amplifier, a splitter, or the like. The coupling device may comprise a single upstream interface coupled to a plurality of downstream interfaces. The enabling and/or disabling may be in response to a signal strength indicated by the SSI being below a threshold and/or in response to one or more control messages indicating whether any downstream cable modem is, or will be, transmitting. | 01-23-2014 |
20140022943 | METHOD AND SYSTEM FOR SERVICE GROUP MANAGEMENT IN A CABLE NETWORK - A cable modem termination system (CMTS) may determine, for a plurality of cable modems served by the CMTS, a corresponding plurality of SNR-related metrics. The CMTS may assigning the modems among a plurality of service groups based on the SNR-related metrics. For any one of the modems, the CMTS may configure physical layer communication parameters to be used by the one of the modems based on a SNR-related metric of a service group to which the one of the modems is assigned. The physical layer communication parameters may include one or more of: transmit power, receive sensitivity, timeslot duration, modulation type, modulation order, forward error correction (FEC) type, and FEC code rate. The CMTS and the modems may communicate using orthogonal frequency division multiplexing (OFDM) over a plurality of subcarriers, and the physical layer communication parameters may be determined on a per-subcarrier basis. | 01-23-2014 |
20140022926 | METHOD AND SYSTEM FOR A HIGH CAPACITY CABLE NETWORK - A cable modem termination system (CMTS) may communicate with a plurality of cable modems using a plurality of orthogonal frequency division multiplexed (OFDM) subcarriers. The CMTS may determine a performance metric of each of the cable modems. For each of the OFDM subcarriers and each of the cable modems, the CMTS may select physical layer parameters to be used for communication with that cable modem on that OFDM subcarrier based on a performance metric of that cable modem. The parameters may be selected for each individual modem and/or each individual subcarrier, or may be selected for groups of modems and/or groups of subcarriers. The parameters may include, for example, one or more of: transmit power, receive sensitivity, timeslot duration, modulation type, modulation order, forward error correction (FEC) type, and FEC code rate. | 01-23-2014 |
20140022105 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE - A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. | 01-23-2014 |
20130268979 | Method And System For Full Spectrum Capture Sample Rate Adaptation - An electronic device may be operable to sample a signal during an analog-to-digital conversion using an analog-to-digital converter in the electronic device, and the signal may comprise a wide bandwidth and a plurality of channels. The electronic device may adaptively change a sample rate of the sampling to move aliasing out of a region of one or more desired channels of the plurality of channels. The electronic device may change the sample rate using a variable oscillator in the electronic device. The change of the sample rate may comprise, for example, increasing or decreasing the sample rate by a particular percentage. In response to the change of the sample rate, the electronic device may perform, using a variable rate interpolator in the electronic device, variable rate interpolation. The variable rate interpolator may comprise, for example, a finite impulse response filter. | 10-10-2013 |
20120322398 | Harmonic Rejection Mixer Architecture with Reduced Sensitivity to Gain and Phase Mismatches - A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions. | 12-20-2012 |
20120302193 | HARMONIC REJECT RECEIVER ARCHITECTURE AND MIXER - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 11-29-2012 |
20120302192 | HARMONIC REJECT RECEIVER ARCHITECTURE AND MIXER - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 11-29-2012 |
20120300887 | HARMONIC REJECT RECEIVER ARCHITECTURE AND MIXER - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 11-29-2012 |
20120299650 | Self-Calibrating Gain Control System - A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit. | 11-29-2012 |
20120244826 | Method and Apparatus for Efficient DC Calibration in a Direct-Conversion System with Variable DC Gain - A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated. | 09-27-2012 |
20120223860 | Use of Motion or Accelerometer Sensors in Low Power Positioning System - A power-saving GNSS includes a sensor for detecting a motion of the receiver, an RF front-end for receiving satellite signals, and a central processing unit coupled to the front-end for acquiring a set of the received satellite signals if the motion is detected. The receiver further include a signal strength evaluator for evaluating a signal strength of the acquired set of the received signals and a counter to count a time period for which the signal strength is below a predetermined value. The receiver also includes a control unit for setting the receiver into an intermittent operating mode if the signal strength exceeds the predetermined value sets the receiver into a power-saving mode if the signal strength is below the predetermined value for the time period determined by the counter. The receiver may also be set into the power-saving mode if it remains stationary for a given time interval. | 09-06-2012 |
20120218146 | Dynamic Sleep Time Calculation for GNSS Receiver - A GNSS receiver includes a sensing element for detecting an environmental condition, a control unit for dynamically calculating a sleep time duration in response to the environmental condition, and a digital processing unit that operates in a first mode or in a second mode based on the calculated sleep time duration and the environmental condition. The environmental condition may include a receiver signal strength indicator, a receiver velocity, the stability and precision of a local reference clock, a recent almanac, an ephemeris data, and the like. The first operation mode may include a tracking of satellite signals, and the second operation mode may include an acquisition operation, a tracking operation, or a combination of acquisition and tracking operations of satellite signals. | 08-30-2012 |
20120218142 | Reporting of Last Acquired Position During Gap of Satellite Reception for GNSS Systems - A GNSS receiver includes a radio frequency module and an antenna for acquiring and tracking signals from various satellites and demodulating them to an intermediate frequency or a baseband signal. The receiver also includes a processing unit for processing the demodulated signals to obtain a first position, velocity, and time (PVT fix) data and displays the data to a user. The receiver may include a memory unit for storing the obtained PVT fix. The receiver may further include one or more sensors for detecting a motion of the receiver and provide an index to the processing unit that determines a next position of the receiver based on the index during a coverage gap. The one or more sensors may include an accelerometer, a compass, or a combination thereof. | 08-30-2012 |
20120198224 | Encryption Keys Distribution for Conditional Access Software in TV Receiver SOC - A method for securely generating and distributing encryption keys includes generating, by a secured server, a pair of keys including a first key and a second key and providing, by a key distributing unit, the first key to a first recipient and a second key to a second recipient. The first recipient may use the first key to encrypt a data file and send the encrypted data file via a non-volatile memory device to a target subscriber. The second recipient may program the second key into an one-time-programmable register contained in a secure element during a manufacturing process. The secure element may further include a random access memory configured to store an image of the encrypted data file, a read-only memory containing a boot code, and a processing unit coupled to the random-access memory and the read-only memory and operative to decrypt the encrypted data file. | 08-02-2012 |
20120134451 | Method and System for a Low-Complexity Soft-Output MIMO Detection - An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N | 05-31-2012 |
20120105284 | GPS ANTENNA DIVERSITY AND NOISE MITIGATION - A system and method for improving acquisition sensitivity and tracking performance of a GPS receiver using multiple antennas is provided. In an embodiment, the acquisition sensitivity can be improved by determining the correlation weight of each received path signal path associated with one antenna form a plurality of antennas and then combining the path signals based on their respective correlation weight. In another embodiment, carrier offset correction information of each path signal is individually determined and then summed together to be used for tracking the code phase in a code phase tracking loop. The code phase tracking loop generates an early code and a late code that are used to determine the code phase error. The system includes notch and bandpass filters to mitigate narrowband and broadband noises of a received GPS signal, wherein the digital adaptive filters are switched on periodically or by external events. | 05-03-2012 |
20120105277 | TIME SYNCHRONIZATION WITH AMBIENT SOURCES - Systems and methods for extracting synchronization information from ambient signals, such as broadcast television signals, and using the synchronization information as a reference for correcting the local time base so that a GNSS positioning receiver system maintains relative time base accuracy with respect to a GNSS time. | 05-03-2012 |
20120079287 | Firmware Authentication and Deciphering for Secure TV Receiver - A method for authenticating and deciphering an encrypted program file for execution by a secure element includes receiving the program file and a digital certificate that is associated with the program file from an external device. The method stores the program file and the associated certificate in a secure random access memory disposed in the secure element and hashes the program file to obtain a hash. The method authenticates the program file by comparing the obtained hash with a checksum that is stored in the certificate. Additionally, the method writes runtime configuration information stored in the certificate to corresponding configuration registers disposed in the secure element. The method further generates an encryption key using a seed value stored in the certificate and a unique identifier disposed in the secure element and deciphers the program file using the generated encryption key. | 03-29-2012 |
20120079279 | Generation of SW Encryption Key During Silicon Manufacturing Process - A method of generating an encryption key during the manufacturing process of a device includes randomly generating a seed, encrypting a unique identifier disposed in the device to obtain a first encryption key, encrypting the first encryption key using a public key to obtain a second encryption key, and sending the second encryption key and the seed to a software provider. The method further includes receiving the second encryption key and the seed by the software provider and decrypting the second encryption key using a private key to recover the first encryption key. The manufacturer then encrypts a program code using the recovered first encryption key and installs the seed in a certificate that is associated with the encrypted program code. | 03-29-2012 |
20120079261 | Control Word Obfuscation in Secure TV Receiver - A device for descrambling encrypted data includes a descrambler, a secure link, and a secure element that securely transmits a control word to the descrambler in a normal operating mode. The secure element includes a first secure register, a read-only memory having a boot code, a random-access memory for storing a firmware image from an external memory, and a processor coupled to the first secure register, the read-only memory, and the random access memory. The processor executes the boot code to generate the control word, stores the control word in the first secure register, and send the stored control word to the descrambler through a secure communication link. The descrambler may include a second secure register that is connected to the first secure register through the secure link. The first and second secure registers are not scannable during a normal operation. The secure link contains buried signal traces. | 03-29-2012 |
20120060039 | Code Download and Firewall for Embedded Secure Application - A device includes a demodulator for receiving an encrypted content, an interface unit communicatively coupled to an external memory, and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received content. The hardware unit includes a processing unit, a ROM having a boot code causing the device to fetch data from the external memory, a RAM for storing the fetched data, multiple non-volatile memory registers or fuse banks, and a mechanism configured to write the stored data to an external storage device in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage device. The interface unit may include a wired or wireless communication link. The boot code includes executable instructions performing a series of validations. The device disables the executable instructions in the event of a validation failure. | 03-08-2012 |
20120057621 | Diversity Receiver - A diversity receiver includes a first receiving channel and a second receiving channel. The receiver also includes a baseband processor that computes a difference between the received signal strengths of the signals received from the first and second channels, wherein the processor disables the signal received from the second channel if the difference is greater than a first threshold value and a BER associated with the second receiving channel is greater than a BER threshold value, and disables the signal received from the first channel if the difference is less than the negative first threshold value and the bit error rate (BER) associated with the first channel is greater than the BER threshold value. The receiver further includes a bypass circuit coupled to an input of an amplifier and a RSSI circuit that provides a conduction path between the input and a ground when the RSSI circuit detects a blocker signal. | 03-08-2012 |
20120042157 | RAM Based Security Element for Embedded Applications - An integrated circuit includes a demodulator for receiving an encrypted message and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received message. The hardware unit includes a processing unit, a read-only access memory (ROM) having a boot code causing the integrated circuit to fetch data from an external memory, a random access memory (RAM) for storing the fetched data, multiple non-volatile memory registers or fuses, and an interface unit configured to write the data stored in the RAM to an external storage in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage. The interface unit may include a direct memory access controller. The external memory and the external storage can be a same non-volatile memory, namely a Flash device. | 02-16-2012 |
20120036372 | Conditional Access Integration in a SOC for Mobile TV Applications - An integrated circuit (IC) includes a demodulator for receiving encrypted information data and a hardware unit that enables conditional access to the information data. The hardware unit includes a processing unit, a RAM, a ROM, multiple non-volatile registers, and an interface unit for transferring an attribute to the demodulator. The non-volatile registers may include an IC identification and an encryption key. In an embodiment, the ROM includes a boot code that causes the processing unit to fetch a code from an external memory and store the fetched code in the RAM. The fetched code may include a certificate that ensures the authenticity of the code. The fetched code may be encrypted and decrypted by the ROM using the IC identification and the encryption key. The demodulator includes a descrambler for decrypting the received information data using the attribute. The information data may include digital radio or television content. | 02-09-2012 |
20120025904 | AREA-OPTIMIZED ANALOG FILTER WITH BANDWIDTH CONTROL BY A QUANTIZED SCALING FUNCTION - A programmable active frequency-selective circuit includes a first capacitor having a fixed value and a second capacitor having a value defined by a product of a parameter and a plurality of switchable capacitors, wherein the parameter is defined by a gain, a bandwidth mode, and a process resolution. The parameter may be stored in a form of a look-up table and enables a user or manufacturer to program the gain, select the bandwidth mode and tune the process. The frequency-selective circuit may include a differential input and a differential output having a first feedback path connected across a positive output terminal to a negative input terminal and a second feedback path connected across a negative output terminal and a positive input terminal. | 02-02-2012 |
20120002767 | FAST RESYNCHRONIZATION FOR RECEPTION IN TIME SLICING - A method and an apparatus for achieving fast resynchronization of received signals in a time slice in DVB-T/H systems. When the clock drift is low, the location of the symbol window can be decided based on a previous time slice. When the clock drift is high and when there are large delay spreads, the location of the symbol window can be decided based on the detected scattered pilot positions. The placement of the symbol window can further be enhanced through processing of the received TPS bits. | 01-05-2012 |
20120001797 | GNSS RECEPTION USING DISTRIBUTED TIME SYNCHRONIZATION - A GNSS receiver communicates with any connectivity device, such as a WiFi device that is, in turn, in communication with a wired network having access to the DTI timing. Such connectivity devices may set their timing and frame synchronization to the DTI and thus serve as Geopositiong beacons, thereby enabling the GNSS receiver to accurately determine its position. The GNSS receiver may also use the DTI timing supplied by such a network to perform relatively long integration time so as to achieve substantially improved sensitivity that is necessary for indoor Geopositioning applications. Furthermore, the GNSS data, such as satellite orbital information, may also be propagated by such devices at high speed. By providing this data to the GNSS receivers via such connectivity devices in a rapid fashion, the GNSS receivers are enabled to receive the transmitted data associated with the satellite without waiting for the GNSS transmission from the satellites. | 01-05-2012 |
20110310948 | LOW-COMPLEXITY DIVERSITY USING PREEQUALIZATION - A diversity receiver includes a first RF front end module for receiving a first RF signal, and frequency converting the first RF signal and outputting a first diversity signal, a second RF front end module for receiving a second RF signal, frequency converting the second RF signal and outputting a second diversity signal, a first converter for converting the first diversity signal to a first time-domain signal, a second converter for converting the second diversity signal to a second time-domain signal, a first transformer for translating the first time-domain signal to a first frequency-domain signal, a second transformer for translating the second time-domain signal to a second frequency-domain signal, a first pre-equalizer for equalizing the first frequency-domain signal, a second pre-equalizer for equalizing the second frequency-domain signal, and a combiner for combining the first and second pre-equalized frequency-domain signals. The diversity receiver further includes a channel estimator having a mirror window. | 12-22-2011 |
20110309976 | INTERMITTENT TRACKING FOR GNSS - A GNSS system operates intermittently and has adaptive activity and sleep time in order to reduce power consumption. The GNSS system provides an enhanced estimate of its position in the absence of GNSS signals of sufficient strength. The user's activity and behavior is modeled and used to improve performance, response time, and power consumption of the GNSS system. The user model is based, in part, on the received GNSS signals, a history of the user's positions, velocity, time, and inputs from other sensors disposed in the GNSS system, as well as data related to the network. During each activity time, the GNSS receiver performs either tracking, or acquisition followed by tracking. The GNSS receiver supports both normal acquisition as well as low-power acquisition. | 12-22-2011 |
20110294448 | ANALOG FRONT END CIRCUIT FOR CABLE AND WIRELESS SYSTEMS - A circuit includes, an attenuator responsive to an input signal and a feedback signal, a variable gain low-noise amplifier responsive to the attenuator and to the feedback signal, a tracking filter, a frequency converter, and an RSSI responsive to the variable gain amplifier to generate an output signal to which the feedback signal is responsive. The frequency converter may be a mixer having a single-ended input and a differential output. The circuit may further include an analog baseband block responsive to the mixer to filter out high frequency signals. The tracking tuner performs bandpass filtering operation on the output signals of the variable gain low-noise amplifier. | 12-01-2011 |
20110291882 | CO-OPERATIVE GEOLOCATION - A method and apparatus for extending the coverage of geolocation to indoor locations through cooperative geolocation. The method includes establishing an ad-hoc wireless network comprising a plurality of devices including a first device. The method includes receiving, at the first device, position information from the plurality of devices and determining a physical location of the first device based on the received position information. In an embodiment, the position information is transmitted in response to a request by the first device. In an embodiment, the position information may include a time of arrival of the request received by each of the plurality of devices; and the time of arrival may be associated with a GNSS time. In an embodiment, the ad-hoc wireless network may be a Wi-Fi network, which is associated with one of the IEEE 802.11 standards. | 12-01-2011 |
20110287725 | DIVERSITY BLOCKER PROTECTION - A transmitting/receiving circuit includes, in part, at least one transceiver, and at least two receiving channels forming a diversity receiver. One of the receiving channels includes, in part, a saw filter, an amplifier, and a frequency converter. The other receiving channel includes, in part, an amplifier, a frequency converter, and a received signal strength indicator (RSSI) adapted to detect signals transmitted by the transceiver. The RSSI is optionally coupled to an input terminal of its associated amplifier. The receiver further includes, in part, at least one processor operative to combine signals processed through the first and second receiving channels using a weight the processor assigns to the signal received by the second receiving channel in accordance with a strength of the blocker signal that the RSSI detects. The second receiving channel optionally includes an RSSI. | 11-24-2011 |
20110286561 | CLOCK-OUT AMPLITUDE CALIBRATION SCHEME TO ENSURE SINE-WAVE CLOCK-OUT SIGNAL - A clock generator includes, in part, a buffer, a peak detector and a control logic. The buffer generates a clock output signal in response to receiving a clock signal and a feedback signal that controls the gain of the buffer. If the peak detector detects that the amplitude of the output signal is higher than the upper bound of the predefined range, the gain value applied to the variable buffer is decreased. If the peak detector detects that the amplitude of the output signal is lower than the lower bound of the predefined range, the gain value applied to the variable buffer to increased. If the peak detector detects that the amplitude of the output signal is within the predefined range, no change is made to the gain value applied to the variable buffer. The control logic generates the feedback signal in response to the peak detector's output signal. | 11-24-2011 |
20110285912 | Integrated IF SAW Filter in Baseband Digital Design for Analog TV (or Hybrid) Tuner - A filter for processing a digital TV composite signal having a video component and an audio component includes a digital video filter and a digital audio filter. The digital video filter includes a lowpass finite impulse response (FIR) filter, an up-mixer, an asymmetric filter for compensating a Nyquist slope of the video component, and a down-mixer connected in this order. The digital audio filter includes an audio down-mixer, a decimated FIR filter, an enhancing FIR filter, an interpolated FIR filter, and an audio up-mixer. These components are connected in series. Optionally, the decimating FIR filter is decimated by an integer decimation factor M, and the interpolated FIR filter is interpolated by an integer factor N. The integer M and N may have the same value. | 11-24-2011 |
20110281542 | CRYSTAL CONTROL SCHEME TO IMPROVE PERFORMANCE OF A RECEIVER - A circuit includes, in part, a receiver, a received signal strength indicator (RSSI), and an oscillator. The receiver receives an incoming signal and an oscillating signal. The RSSI is responsive to the receiver and generates an output signal representative of the strength of the incoming signal. The oscillator receives different biasing conditions in response to different outputs of the RSSI. The oscillator generates the oscillating signal received by the receiver. The oscillator receives a first biasing condition when the incoming signal is detected as having a strength lower than or equal to a predetermined threshold value and a second biasing condition when the incoming signal is detected as having a strength higher than the predetermined threshold value. The first biasing condition may be defined by a first current, and the second biasing condition may be defined by a sum of the first current and a second current. | 11-17-2011 |
20110280344 | DYNAMIC BANDWIDTH CONTROL SCHEME OF A FRAC-N PLL IN A RECEIVER - A receiver, in accordance with one embodiment of the present invention, includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired noise that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to an output signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer. | 11-17-2011 |
20110264721 | SIGNAL PROCESSING BLOCK FOR A RECEIVER IN WIRELESS COMMUNICATION - A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented ( | 10-27-2011 |
20110227614 | TCXO Replacement for GPS - To determine the level of frequency drift of a crystal oscillator as a result of a change in the its temperature, the temperature of the crystal oscillator is sensed and used together with previously stored data that includes a multitude of drift values of the frequency of the crystal oscillator each associated with a temperature of the crystal oscillator. Optionally, upon initialization of a GPS receiver in which the crystal oscillator is disposed, an initial temperature of the crystal oscillator is measured and a PLL is set to an initial frequency in association with the initial temperature. When acquisition fails in a region, the ppm region is changed. The temperature of the crystal oscillator is periodically measured and compared with the initial temperature, and the acquisition process is reset if there is a significant change in temperature. The GPS processor enters the tracking phase when acquisition is successful. | 09-22-2011 |
20110222633 | HIGH DYNAMIC RANGE RADIO ARCHITECTURE WITH ENHANCED IMAGE REJECTION - A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations. | 09-15-2011 |
20110170587 | EDGE EQUALIZER - To compensate for roll-off while estimating a communication channel, an estimate of the channel is provided using a signal transmitted via the communication channel. The pilot tones positioned along the edges of the estimated channel are divided by the corresponding pilot tones of the received signal to generate a first number of ratios. An algorithm is thereafter applied to the first number of ratios to generate a second number of ratios associated with the non-pilot tones positioned along the edges of the estimated channel. Next, numbers that are inverse of the first and second number of ratios are applied to the pilot and non-pilot tones positioned along the edges of the estimated channel to compensate for the roll-offs in the estimated channel. | 07-14-2011 |
20110169697 | GPS-ASSISTED SOURCE AND RECEIVER LOCATION ESTIMATION - A mobile communication device includes, in part, a first wireless receiver adapted to determine, as it travels along a path, a multitude of positions of the mobile communication device using signals received from a primary positioning source, a second wireless receiver adapted to receive signals from one or more ambient wireless sources as the mobile communication device travels along the path, and a positioning module. An internal or external memory stores estimated positions and corresponding time references of the signals of the one or more ambient sources. The positioning module uses the data stored in the database to estimate the position of the mobile communication device when no primary positioning source signal is available. The positioning module optionally uses the data stored in the database to improve estimates of the position of the mobile communication device when primary positioning signal is available. | 07-14-2011 |
20110164690 | METHODS AND SYSTEMS FOR LOCATION ESTIMATION - A receiver system and method for determining the location of a device in a wireless network having a plurality of transmitters is provided. The method includes receiving a signal at the device, transforming the received signal into a time-domain signal having a characteristic, and computing a range of the device from each of the plurality of transmitters based on the characteristic. Additionally, the method includes determining the location of the device based on the computed ranges. In certain embodiments, the characteristic may be a time of arrival, time difference of arrival, or a signal strength, and the wireless network is a DTV broadcasting network. | 07-07-2011 |
20110105068 | WIDEBAND TUNER ARCHITECTURE - A wideband receiver system is provided to concurrently receive multiple RF channels including a number of desired channels that are located in non-contiguous portions of a radio frequency spectrum and to group the number of desired channels into a contiguous frequency band. The system includes a wideband receiver having a complex mixer for down-shifting the multiple RF channels and transforming them to an in-phase signal and a quadrature signal in the baseband. The system further includes a wideband analog-to-digital converter module that digitizes the in-phase and quadrature signals and a digital frontend module that transforms the digital in-phase and quadrature signals to baseband signals that contains only the number of desired RF channels. that are now located in a contiguous frequency band. An up-converter module up-shifts the baseband signals to a contiguous band in an IF spectrum so that the system can directly interface with commercially available demodulators. | 05-05-2011 |
20110102257 | GPS BASEBAND CONTROLLER ARCHITECTURE - A GPS receiver includes an RF front end for acquiring and tracking a satellite signal and a baseband processor configured to preserve power. The baseband processor includes a GPS engine configured to process the satellite signal and generate a PVT fix, a power supervisory module for receiving the PVT fix, and a user state module that determines an environmental state, wherein the power supervisory module may power down the GPS receiver for a period of time based on a result of the determined environment state. The baseband processor also includes a time-based management module that adjusts the TCXO in response to the determined environmental state. The GPS receiver includes a plurality of operation modes, each of which is associated with a plurality of tracking profiles. | 05-05-2011 |
20110096874 | WIDEBAND PERSONAL-RADIO RECORDER - Methods and apparatuses for concurrently recording multiple radio channels. A recorder includes a wideband tuner having a complex mixer for converting a received wideband RF signal to a complex signal that is then digitized. A digital front end module applies a number of complex down-mixers to the digital complex signal to generate the multiple radio channels in the baseband. Each one of the multiple radio channels in the baseband is further filtered, decimated and demodulated. A digital signal processing unit encodes each demodulated channel according to an audio compression format and stores the then encoded audio content to a storage unit. An RBDS decoder parses radio data service information associated with the stored audio content. The radio data service information is stored in a first section of the storage unit while the encoded audio content is stored in a second section of the storage unit. | 04-28-2011 |
20110096864 | PROGRAMMABLE DIGITAL CLOCK CONTROL SCHEME TO MINIMIZE SPUR EFFECT ON A RECEIVER - A device includes an analog front end for receiving a radio frequency (RF) signal. The analog front end contains a local oscillator that is tuned to a local oscillation frequency for down-converting the received RF signal to a first intermediate frequency (IF) signal. An analog-to-digital converter module converts the first IF signal to a digital baseband signal. The device also includes a digital processing unit for processing the baseband signal. The digital processing unit generates multiple clock signals from a reference oscillator having digitally adjustable reference frequency. The reference frequency and the multiple clock signals may interfere with the local oscillator and generate several frequency spurs that may fall within the bandwidth of the received RF signal. In a preferred embodiment, the digital processing unit adjusts the reference frequency by a certain amount so that the spurs do not fall within the RF signal bandwidth. | 04-28-2011 |
20110090971 | DOPPLER ESTIMATOR FOR OFDM SYSTEMS - A method of estimating the Doppler spread of a communication channel includes computing a first sum defined by a difference between the pilot tones of a first group of N symbols and a corresponding pilot tones of a second group of N symbols preceding the first group of N symbols, computing a second sum defined by the pilot tones of the second group of N symbols, and computing a ratio of the first sum and the second sum for each of the N symbols of the first and second group of symbols to generate N ratios representative of the Doppler spread of the channel. The first sum is further defined by the square of the difference between the pilot tones of the first group of N symbols and the corresponding pilot tones of the second group of N symbols. | 04-21-2011 |
20110081877 | DUAL CONVERSION RECEIVER WITH PROGRAMMABLE INTERMEDIATE FREQUENCY AND CHANNEL SELECTION - A dual conversion receiver architecture that converts a radio frequency signal to produce a programmable intermediate frequency whose channel bandwidth and frequency can be changed using variable low-pass filtering to accommodate multiple standards for television and other wireless standards. The dual conversion receiver uses a two stage frequency translation and continual DC offset removal. The dual conversion receiver can be completely implemented on an integrated circuit with no external adjustments. | 04-07-2011 |
20110009080 | RECEIVER ARCHITECTURE WITH DIGITALLY GENERATED INTERMEDIATE FREQUENCY - A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware. | 01-13-2011 |
20100271558 | HYBRID RECEIVER ARCHITECTURE USING UPCONVERSION FOLLOWED BY DIRECT DOWNCONVERSION - A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF. | 10-28-2010 |
20100003943 | Harmonic Reject Receiver Architecture and Mixer - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 01-07-2010 |
20090258625 | GAIN PARTITIONING IN A RECEIVER - An automatic gain control loop disposed in a receiver is adapted to compensate for varying levels of out of band interference sources by adaptively controlling the gain distribution throughout the receive signal path. One or more intermediate received signal strength indicator (RSSI) detectors are used to determine a corresponding intermediate signal level. The output of each RSSI detector is coupled to an associated comparator that compares the intermediate RSSI value against a corresponding threshold. The take over point (TOP) for gain stages is adjusted based in part on the comparator output values. The TOP for each of a plurality of gain stages may be adjusted in discrete steps or continuously. | 10-15-2009 |
20090252264 | LOW-COMPLEXITY DIGITAL RADIO INTERFACE - A radio integrated circuit includes, in part, an analog front end block, an analog-to-digital converter responsive to the analog-front end block, a digital signal processor responsive to the analog-to-digital converter and adapted to generate in-phase and quadrature signals, and a serial communication interface configured to receive and transmit the in-phase and quadrature signals. The serial communication interface supplies a gain control signal to the analog front end block when a switch disposed in the radio integrated circuit is in a first position. When the switch is in a second position, a gain control block disposed in the radio integrated circuit receives a gain control signal from the analog-to-digital converter and supplies the gain control signal to the analog front end block. The digital signal processor may be configured to interleave the in-phase and quadrature signals. | 10-08-2009 |
20090098845 | METHOD AND APPARATUS FOR EFFICIENT DC CALIBRATION IN A DIRECT-CONVERSION SYSTEM WITH VARIABLE DC GAIN - A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated. | 04-16-2009 |
20090098844 | LOW-COMPLEXITY DIVERSITY USING COARSE FFT AND SUBBAND-WISE COMBINING - A wireless diversity receiver includes, in part, N signal processing paths, a bin-wise combiner, and an inverse transformation module. Each signal processing path includes, in part, a mixer adapted to downconvert a frequency of an RF signal received by that path, an analog-to-digital converter adapted to convert the downconverted signal from an analog signal to a digital signal, and a transformation block adapted to transform the digital signal represented in time domain to an associated frequency domain signal having M subband signals. The bin-wise combiner is configured to combine the corresponding subband signals of the N paths. The inverse transformation block is configured to transform the output of the bin-wise combiner to an associated time-domain signal. | 04-16-2009 |
20090088120 | I/Q Calibration Techniques - A receiver includes a static I/Q calibration block and a correlation/integration block. The static I/Q calibration block is configured to substantially eliminate mismatches between in-phase and quadrature components of a portion of the spectrum having associated I/Q mismatches that are relatively frequency-independent. The correlation/integration block is configured to substantially eliminate mismatches between the in-phase and quadrature components of portions of the spectrum having associated I/Q mismatches that are relatively frequency-dependent in accordance with a pair of signals generated by the static I/C calibration block. | 04-02-2009 |
20090052541 | METHOD AND APPARATUS FOR PRESERVING DEINTERLEAVING ERASURE INFORMATION OF BLOCK INTERLEAVED CODED SIGNAL - Erasure information associated with a received group of encoded and interleaved data in a digital video broadcasting system is stored in a much compacted form. An erasure flag and an address of a last byte associated with the received group of encoded and interleaved data (a record) encapsulated in an MPE-FEC column will be stored in an erasure table. All bytes in the column preceding the last byte of the record will have the same erasure flag as the last byte. Erasure information deinterleaver | 02-26-2009 |
20090041115 | TS Packet Grooming - Received data packets are groomed to improve performance of MPEG-2 transport stream packet in a digital video broadcasting system. Multitude of crosschecking techniques are applied to ensure that crucial pieces of information such as the packet identifier (PID) field, the continuity counter (CC) field, table ID, section length, IP header checksum, table and frame boundaries, application data table size are corrected if necessary. | 02-12-2009 |
20090040391 | TUNER FOR CABLE, SATELLITE AND BROADCAST APPLICATIONS - A tuner includes, in part, one or mixers, one or more filters, one or more variable gain stages, one or more analog to digital converters, and a baseband processor. Each filter is responsive to an associated mixer's output signal. Each variable gain stage is responsive to an associated filter's output. Each analog-to-digital converter is adapted to convert the output signal of an associated variable gain stage to a digital signal. The baseband processor is responsive to the digital signal supplied by the analog-to-digital converter(s). The baseband processor is further configured to supply a signal to be demodulated by a processing unit external to the integrated circuit. The baseband processor performs no or a fraction of the required demodulation functions. The processing unit may be a central processing unit or a graphical processing unit. | 02-12-2009 |
20080209499 | CHANNEL CHANGE LATENCY REDUCTION - A wireless communication system is enhanced to allow for low-latency channel surfing and to enable a user to quickly see the content carried over a selected channel while searching channels for desired content. The techniques for reducing the channel change latency may be implemented in a transmitter, receiver, or in a combination of transmitter and receiver. The wireless communication system is optionally a DVB-H communication system. The transmitter may generate and transmit one or more auxiliary channels, where each auxiliary channel contains reduced resolution content corresponding to one or more channels. The receiver may process the one or more auxiliary channels to present the reduced resolution content while processing the full resolution channel for display. The receiver caches portions of content from one or more non-selected channels and presents the cached content when the channel is selected while concurrently searching and processing the full resolution channel content. | 08-28-2008 |
20080204143 | WIDE DYNAMIC RANGE AMPLIFIER GAIN CONTROL - Linear wide dynamic range variable gain amplifiers can be configured using a variable gain amplifier having an abbreviated gain control range in combination with a discrete attenuator controlled to select an attenuation from a predetermined set of attenuation values. The variable gain amplifier is configured to provide substantially linear gain control over the abbreviated gain control range, where the abbreviated gain control range is less than a total desired gain control range. The difference between adjacent attenuation values in the set of attenuation values is configured to be approximately less than or equal to the abbreviated gain control range. | 08-28-2008 |
20080198942 | LONG ECHO DETECTION AND CHANNEL ESTIMATION FOR OFDM SYSTEMS - A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile. | 08-21-2008 |