INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW Patent applications |
Patent application number | Title | Published |
20120069645 | MULTIPLE BIT PHASE CHANGE MEMORY CELL - A phase change memory cell has more than one memory region ( | 03-22-2012 |
20120018696 | VERTICAL PHASE CHANGE MEMORY CELL - A vertical phase change memory cell ( | 01-26-2012 |
20110198671 | GRINGO HETEROJUNCTION BIPOLAR TRANSISTOR WITH A METAL EXTRINSIC BASE REGION - The invention relates to a semiconductor device ( | 08-18-2011 |
20110080781 | PHASE CHANGE MEMORY DEVICE AND CONTROL METHOD - The present invention relates to a phase change memory device comprising a plurality of phase change memory cells, each cell comprising a phase change material ( | 04-07-2011 |
20110049634 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate ( | 03-03-2011 |
20090173937 | METHOD FOR THE PRODUCTION OF A LAYER OF ORGANIC MATERIAL - The present invention provides a method for producing a layer of organic material. The method comprises
| 07-09-2009 |
20090166753 | Semiconductor Device and Method of Manufacturing Such a Device - The invention relates to a semiconductor device ( | 07-02-2009 |
20090135652 | Method for Extracting the Distribution of Charge Stored in a Semiconductor Device - The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimised value in said sets of programming parameters and repeating steps b) to e) at least once. | 05-28-2009 |
20090134521 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF COPPER GERMANIDE AND COPPER SILICIDE AS COPPER CAPPING LAYER - A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH | 05-28-2009 |
20090102051 | METHOD TO CREATE SUPER SECONDARY GRAIN GROWTH IN NARROW TRENCHES - The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices. | 04-23-2009 |
20090079016 | METHOD FOR FORMING A DIELECTRIC STACK - The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen. | 03-26-2009 |
20080208268 | Means for Functional Restoration of a Damaged Nervous System - The present invention relates generally to a method and device of partial or complete functional restoration of the damaged nervous system by bridging a cavity in the central or peripheral nervous tissue and, more particularly to a system and method for repairing the nerve signal transduction by bridging of the cavity with microelectrode elements more particular microelectrodes for stimulation and microelectrodes for recording. | 08-28-2008 |