INOTERA MEMORIES, INC. Patent applications |
Patent application number | Title | Published |
20150349072 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion. | 12-03-2015 |
20150348963 | CYLINDER-SHAPED STORAGE NODE WITH SINGLE-LAYER SUPPORTING STRUCTURE - A semiconductor structure includes a substrate having thereon a conductive region, at least one cylinder-shaped container on the conductive region, and a supporting structure having at least two stripe shaped portions arranged in parallel to each other and at least one retaining ring between the two stripe shaped portions. The retaining ring retains and structurally supports the cylinder-shaped container electrode. | 12-03-2015 |
20150348871 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having a first side and a second side opposite to the first side; a through substrate via (TSV) structure protruding from a surface of the substrate on the second side; a block layer conformally covering the surface of the substrate and the TSV structure; a first dielectric layer covering the block layer except for a portion of the block layer that is directly on the TSV structure; a second dielectric layer on the first dielectric layer; and a damascened circuit pattern in the second dielectric layer. The second dielectric layer is in direct contact with the first dielectric layer. The damascened circuit pattern is in direct contact with the TSV structure. | 12-03-2015 |
20150270144 | PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention is directed to a method for fabricating a patterned structure of semiconductor device. First, a target layer and a hard mask layer are sequentially formed on a substrate. Then, a patterned photoresist layer having at least one photoresist stripe is formed to partially cover the hard mask layer. Thereafter, an ion-implant process is performed on hard mask layer with the patterned photoresist layer as a mask to form doped regions therein. Afterwards, at least one acid-crosslinked polymer spacer is formed on the sidewalls of at least one photoresist stripe to surpass a resolution limit of the patterned photoresist layer. Specifically, the patterned photoresist layer and the at least one acid-crosslinked polymer spacer are configured to define a plurality of first openings in the hard mask layer, and the doped regions of the hard mask layer is configured to further define a plurality of second openings therein. | 09-24-2015 |
20150270141 | METHOD FOR INCREASING PATTERN DENSITY - A method of fabricating a semiconductor device includes the steps of providing a hard mask cover using a patterned photoresist layer, wherein the patterned photoresist layer comprises at least four first holes arranged in two rows and two columns. Part of the hard mask is removed to form at least four second holes by taking the pattered photoresist layer as a mask. Next, each of the first holes is widened, and the widened first holes and the second holes are filled up by a filler. Later, the patterned photoresist layer is removed entirely. Part of the hard mask is removed to form at least a fourth hole by taking the filler as a mask. Finally, the filler is removed entirely. | 09-24-2015 |
20150243597 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING - A semiconductor device includes a substrate having a front side and a rear side, a plurality of dielectric layers on the front side, a plurality of interconnection circuit structures in the dielectric layers, and at least one backside passivation layer on the rear side. The backside passivation layer and the top passivation layer are made of the same material and have substantially the same thickness. | 08-27-2015 |
20150214233 | MANUFACTURING METHOD OF CAPACITOR LOWER ELECTRODE AND SEMICONDUCTOR STORAGE DEVICE USING THE SAME - A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings. | 07-30-2015 |
20150214231 | DYNAMIC RANDOM ACCESS MEMORY UNIT AND FABRICATION METHOD THEREOF - A dynamic random access memory unit includes a substrate having a trench disposed therein, a self-aligned trench isolation structure formed in the bottom portion of the trench, and a first trenched gate formed in the bottom portion of the trench and above the self-aligned trench isolation structure. The substrate includes at least one pillar-shaped active body having a drain region, a body region atop the drain region, and a source region atop the body region. The first trenched gate includes a first spacer formed on the side-wall in the bottom portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the drain region, such for defining the width of the self-aligned trench isolation structure. | 07-30-2015 |
20150206883 | MANUFACTURING METHOD OF CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE USING THE SAME - The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes. | 07-23-2015 |
20150198942 | CARRIER ARRANGEMENT SYSTEM AND METHOD OF ARRANGING CARRIERS - A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines. | 07-16-2015 |
20150104276 | OVERHEAD HOIST TRANSPORT SYSTEM - The present invention provides an overhead hoist transport system, which includes a rail, a stocker disposed under the rails, wherein the stocker can move along the direction of the rail, and a cleaning station, disposed on the rail to clean the stocker directly when the stocker is moving. | 04-16-2015 |
20150090684 | LIFTING DEVICE AND AUTOMATIC HANDLING SYSTEM THEREOF - The instant disclosure relates to a lifting device for transporting a wafer carrier to an automatic handling system including a suspension rail and an automatic guiding vehicle configured to move along the suspension rail, comprising an elevating holder, a plurality of suspension modules, and a plurality of first drive modules. Specially, the elevating holder has a motion sensor configured to detect whether the elevating holder is in a horizontal state or a non-horizontal state. The first drive modules can be used to synchronously drive the suspension modules according the horizontal state detected by the motion sensor, and the first drive modules can also be used to individually drive each of the suspension modules according the non-horizontal state detected by the motion sensor to recover the elevating holder from the non-horizontal state as the horizontal state. | 04-02-2015 |
20150076696 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines. | 03-19-2015 |
20150076666 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA - A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface. | 03-19-2015 |
20140312460 | STACKED CAPACITOR STRUCTURE AND A FABRICATING METHOD FOR FABRICATING THE SAME - A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode. | 10-23-2014 |
20140312401 | MEMORY CELL HAVING A RECESSED GATE AND MANUFACTURING METHOD THEREOF - A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate. | 10-23-2014 |
20140308807 | METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY - A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure. | 10-16-2014 |
20140306731 | METHOD OF TESTING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TESTING SYSTEM - A method of testing semiconductor devices is provided includes: exposing one end of the device contact on the surface of the semiconductor; using a scanning probe microscopy apparatus to scan a diagnostic area on the semiconductor; applying a direct current bias between the conductive probe and a substrate of the semiconductor; directing a testing radiation at the diagnostic area to increase amount of free carriers in the device contacts and in the semiconductor layer under the device contacts; and detecting the current flowing through the conductive probe and the substrate, wherein a defect current signal is measured when the probe is in contact with a defective device contact and a normal current signal is measured when the probe is in contact with a normal device contact, wherein the testing radiation increases the current measured to increase the difference between the defect signal and the normal signal. | 10-16-2014 |
20140291738 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines. | 10-02-2014 |
20140264774 | WAFER AND FILM COATING METHOD OF USING THE SAME - The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region. | 09-18-2014 |
20140252550 | STACK CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a stack capacitor structure and a manufacturing method thereof, adapted for a random access memory. The stack capacitor structure is formed on a semiconductor substrate. The stack capacitor structure includes an oxide layer and a circular-shaped stopping layer. The oxide layer is disposed on the semiconductor substrate. The oxide layer has a capacitor trench therein. The circular-shaped stopping layer surrounds an edge of an opening of the capacitor trench. The disclosed stack capacitor structure and the manufacturing method thereof may thereby prevent the occurrence of the stack capacitor structure from having CD variation and belly region causing cell to cell leakage as result of manufacturing process limitation. | 09-11-2014 |
20140220762 | METHOD OF MANUFACTURING ISOLATION STRUCTURE - A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity. | 08-07-2014 |
20140124844 | SEMICONDUCTOR LAYOUT STRUCTURE - A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction. | 05-08-2014 |
20140117442 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source. | 05-01-2014 |
20140112740 | OVERHEAD BUFFER DEVICE AND WAFER TRANSPORT SYSTEM - An overhead buffer device used for disposing in a semi-conductor factory includes a strut module and a plurality of buffer modules. The strut module disposed on the top wall of the factory has a horizontal beam and a plurality of overhead strut. The overhead strut is set on the horizontal beam and spaced arranged along the horizontal beam. The buffer modules are installed on the overhead strut respectively. Each buffer module has a plurality of buffers arranged in sequence and along a vertical direction. Each buffer is used for receiving one front opening unified pod (FOUP). Thus, the instant disclosure can be used for using the space of the factory efficiently. Besides, the instant disclosure also provides a wafer transport system having the overhead buffer device. | 04-24-2014 |
20140110818 | RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD FOR NODES THEREOF - A manufacturing method for the nodes of the RAM device, includes the steps as follows: forming a STI layer on a substrate to divide the substrate into several active areas; sequentially forming a first insulating layer and a hard mask layer on the substrate; etching the first insulating layer to form a first hole for exposing the STI layer and partial of the active areas; filling a conductive material in the first hole to form a conductor; forming a protective layer on the top surface of the conductor, wherein each protective layer has an opening aligning the STI layer; etching the conductor from the opening until the STI layer to form a second hole for exposing the STI layer, wherein each conductor is divided into two nodes by the second hole arranged therebetween; and forming a second insulating layer in the second hole for electrically isolating the nodes. | 04-24-2014 |
20140084419 | CAPACITOR STRUCTURE - A DRAM capacitor structure is disposed on the interior surface of a vertical hollow cylinder of a support structure overlying a semiconductor substrate. The support structure further includes a horizontal supporting layer that is integrally connected with the vertical hollow cylinder. A fabrication method for forming the DRAM capacitor structure is also provided. | 03-27-2014 |
20130252397 | MANUFACTURING METHOD FOR HIGH CAPACITANCE CAPACITOR STRUCTURE - A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers. | 09-26-2013 |
20130234280 | SHALLOW TRENCH ISOLATION IN DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time. | 09-12-2013 |
20130217237 | SPIN-ON DIELECTRIC METHOD WITH MULTI-STAGE RAMPING TEMPERATURE - A Spin-On Dielectric (SOD) method with multi stage ramping temperature for coating a dielectric material onto a substrate, comprising the steps of: (a) placing the substrate on a chill plate to decrease the temperature; (b) fixing the chilled substrate on a spinning device; (c) rotating the spinning device to drive the substrate rotating; (d) injecting the dielectric material onto the center of the substrate; (e) spreading the dielectric material on the upper surface of the substrate by spinning; (f) baking the substrate and the dielectric material by a heat plate to achieve multi stages ramping temperature, where the temperature of each stage has a steady state temperature for a predetermined time and the posterior stage has higher temperature than the anterior stage; (g) placing the substrate on the chill plate for cooling down; (h) spreading a film of dielectric material and finishing the coating. | 08-22-2013 |
20130203233 | MANUFACTURING METHOD OF MEMORY CAPACITOR WITHOUT MOAT STRUCTURE - A manufacturing method of a memory capacitor without a moat structure includes the steps of: providing a semiconductor substrate defined with an array region and a peripheral region; forming a first oxidized layer on the array region; forming a second oxidized layer on the peripheral region; planarizing the first and the second oxidized layers; forming an insulating layer on the first and the second oxidized layers; forming a plurality of trenches on the array region, where the trenches pass through the first oxidized layer and the insulating layer on the first oxidized layer; forming a conductive layer on the side and base surfaces of each trench; removing a portion of the conductive layer and a portion of the insulating layer to form a plurality of notches to expose the first oxidized layer; and removing the first oxidized layers which are exposed from the notches. | 08-08-2013 |
20130203232 | MANUFACTURING METHOD OF RANDOM ACCESS MEMORY - A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads. | 08-08-2013 |
20130168812 | MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF - A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches. | 07-04-2013 |
20130168811 | CAPACITOR HAVING MULTI-LAYERED ELECTRODES - The instant disclosure relates to a capacitor having multi-layered electrodes. The capacitor includes a dielectric layer having a first surface and a second surface oppositely arranged, a first electrode formed on the first surface, and a second electrode formed on the second surface. At least one of the first and second electrodes having a low band gap material layer formed on the dielectric layer and a conducting layer formed on the low band gap material layer. The band gap of the low band gap material layer is lower than the band gap of the conducting layer. | 07-04-2013 |
20130168801 | METHOD OF FORMING ISOLATION AREA AND STRUCTURE THEREOF - The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area. | 07-04-2013 |
20130168751 | HIGH-K METAL GATE RANDOM ACCESS MEMORY - The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer. | 07-04-2013 |
20130138237 | METHOD FOR OPERATING AN AUTOMATIC HANDLING SYSTEM APPLIED TO MANY WAFER PROCESSING APPARATUSES - The instant disclosure provides a method for operating an automatic handling system applied to many wafer processing apparatuses. When a OHT vehicle is moved to one of the wafer processing apparatuses, the OHT vehicle can ask a OHT control module whether a wafer carrier device can be unloaded from the OHT vehicle onto the wafer processing apparatus. There are two judgment methods as follows: (1) If there is another wafer carrier device already disposed on the wafer processing apparatus, the OHT control module will inform the OHT vehicle that the wafer carrier device cannot be unloaded from the OHT vehicle onto the wafer processing apparatus; (2) If there is no any wafer carrier device disposed on the wafer processing apparatus, the OHT control module will inform the OHT vehicle that the wafer carrier device can be unloaded from the OHT vehicle onto the wafer processing apparatus. | 05-30-2013 |
20130071219 | DOOR DETECTION SYSTEM - A door detection system includes a robot arm unit and a movable unit. The robot arm unit includes at least one bearing platform and at least one level sensing structure disposed on the at least one bearing platform. The level sensing structure includes a plurality of contact sensors, and the wafer carrier device is disposed on the at least one level sensing structure. The movable unit includes at least one movable structure disposed on the robot arm unit. The wafer carrier device has a wafer pick-and-place opening corresponding to the door, and one end of the at least one movable structure can selectively contact the door of the wafer carrier device or been inserted into the wafer carrier device from the wafer pick-and-place opening. | 03-21-2013 |
20130068948 | METHOD OF PLANAR IMAGING ON SEMICONDUCTOR CHIPS USING FOCUSED ION BEAM - A method of planar imaging on semiconductor chips using focused ion beam is provided, comprising the steps of: (A)disposing at least a positioning symbol to designate a testing area thereon; (B)disposing a metal membrane on the testing area; (C)trimming the testing chip to form a first testing chip; (D)cutting a blind opening proximate the testing area on the first testing chip to form a second testing chip; (E)disposing and erecting the second testing chip on an inclinable platform; (F)rotating the erected second testing chip with the inclinable platform, thereby allowing ion beams from the FIB to emit into the opening in an angle of inclination; (G)emitting ion beams in the direction of the incident ray to form planar images of different depths parallel to the metal membrane on the testing area. | 03-21-2013 |
20130062674 | SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit. | 03-14-2013 |
20130061772 | OVERHEAD HOIST TRANSPORT SYSTEM - An overhead wafer transport system includes an over head transportation (OHT) rail and at least one shuttle. The OHT rail includes a main track and two lateral tracks, each having a hollow transverse cross-section, each lateral track being in corresponding connection with the main track through the two sides thereof, constituting an approximate tri-directional branch form. The shuttle has a track-interface assembly and a docking unit, the track-interface assembly being adapted to travel along the OHT rail. The track-interface assembly being arranged at the junction of the two lateral tracks and the main track, wherein the track-interface assembly is adapted to selectively travel along at least one of the main track and the lateral tracks. Therefore, the overhead wafer transport system can be applied to a clean room with higher transfer efficiency and clean room space utilization. | 03-14-2013 |
20130059442 | METHOD FOR ADJUSTING TRENCH DEPTH OF SUBSTRATE - A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer. | 03-07-2013 |
20130029465 | MANUFACTURING METHOD OF MEMORY STRUCTURE - The instant disclosure relates to a manufacturing method of memory structure for dynamic random-access memory (DRAM). The method includes the steps of: (a) providing a substrate having a plurality of parallel trenches formed on a planar surface thereof each defining a buried gate, where a first insulating layer is formed on the planar surface of the substrate; (b) forming a gate oxide layer on the surface of each trench that defines the buried gate; (c) disposing a metal filler on the gate oxide layer to fill each of the trenches; (d) removing the metal filler in the upper region of each trench to selectively expose the gate oxide layer; (e) implanting ions at an oblique angle toward the exposed portions of the gate oxide layer in each trench to respectively form a drain electrode and a source electrode in the substrate abreast the gate oxide layer. | 01-31-2013 |
20130026556 | NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY - A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates. | 01-31-2013 |
20130026554 | NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY - A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate. | 01-31-2013 |
20120331357 | METHOD AND SYSTEM OF COMPRESSING RAW FABRICATION DATA FOR FAULT DETERMINATION - The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data. | 12-27-2012 |
20120330591 | FAULT DETECTION METHOD OF SEMICONDUCTOR MANUFACTURING PROCESSES AND SYSTEM ARCHITECTURE THEREOF - A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method. | 12-27-2012 |
20120325105 | BIDIRECTIONAL WAFER CARRYING POD AND WAFER TRANSFER SYSTEM - A wafer transfer system includes a bidirectional wafer carrying pod, an over-head transport (OHT) rail, an OHT, two platforms, and two loading ports respectively connected to the two platforms. The bidirectional wafer carrying pod has a loading housing and two doors respectively and detachably installed on the two opposite sides of the loading housing. The OHT rail has a single rail section and a double rail section. The two ends of the double rail section are connected to the single rail section. The platforms are respectively disposed beside the double rail section. The loading ports are disposed under the double rail section. Through the OHT, The bidirectional wafer carrying pod can selectively be transferred to one rail of the double rail section and disposed on the loading port of the tool corresponding to the one rail of the double rail section. | 12-27-2012 |
20120313157 | DRAM CELL HAVING BURIED BIT LINE AND MANUFACTURING METHOD THEREOF - A dram cell having buried bit line includes a substrate having fin structures thereon, a plurality of deep trenches in the substrate, a buried stripe, a plurality of word lines formed on the substrate and a plurality of capacitors formed on the fin structures. Each of the deep trenches is arranged between two adjacent fin structures. Each of the deep trenches has a metal layer and a poly-silicon layer thereinside to define a buried bit line. The buried stripe is formed in the substrate and next to each of the deep trenches. The bit line is electrically connected to the corresponding fin structure via the buried stripe. The word lines are alternatively arranged with the bit lines, and each of the word lines are disposed cross on the fin structures to construct double gate structures. | 12-13-2012 |
20120279415 | AUTOMATIC HANDLING SYSTEM APPLIED TO MANY WAFER PROCESSING DEVICES - An automatic handling system applied to many wafer processing devices includes a handling rail unit and a transport vehicle unit. The handling rail unit includes at least one handling rail. The transport vehicle unit includes a plurality of OHT vehicles disposed under the handling rail and mated with the handling rail, wherein each OHT vehicle includes at least one sliding portion slidably disposed on the handling rail, at least one rotatable portion for clamping at least one wafer carrier device, and at least one suspended portion connected between the sliding portion and the rotatable portion, wherein the wafer carrier device has a wafer pick-and-place opening, and the wafer carrier device is rotated by the rotatable portion of the OHT vehicle according to the position of the wafer processing device for adjusting the direction of the wafer pick-and-place opening to face the wafer processing device. | 11-08-2012 |
20120270402 | METHOD OF MAKING AN ARRAY COLUMNAR HOLLOW SEMICONDUCTOR STRUCTURE - A method of making an array columnar hollow semiconductor structure includes: providing an oxide layer; placing a chromeless mask on the oxide layer, wherein the chromeless mask is a bank-shaped frame; forming a silicone nitride layer to cover the first partial top surface of the oxide layer and the whole outer surface of the bank-shaped frame; removing one part of the silicone nitride layer to expose a second partial top surface of the oxide layer and a top surface of the bank-shaped frame; removing the bank-shaped frame to expose a third partial top surface of the oxide layer; removing a first part of the oxide layer under the second partial top surface and a second portion of the oxide layer under the third partial top surface to form a plurality of columnar hollow bodies; and removing the other silicone nitride layer to completely expose the columnar hollow bodies. | 10-25-2012 |
20120248309 | SPECIMEN GRID HOLDER AND FOCUSED ION BEAM SYSTEM OR DUAL BEAM SYSTEM HAVING THE SAME - A specimen grid holder includes a base and two holding members disposed thereon. Each holding member has at least one inserting portion and at least one holding portion formed adjacently. The specimen grid can be inserted into the inserting portion and moved to the holding portion for securement. The two holding members can be used to secure specimens at different orientations for analyses. | 10-04-2012 |
20120193706 | VERTICAL TRANSISTOR FOR RANDOM-ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved. | 08-02-2012 |
20120193532 | SEMICONDUCTOR STRUCTURE AND FAULT LOCATION DETECTING SYSTEM - A semiconductor structure includes a grounding unit, a P-type substrate, a P-type well area, an NMOS structure, a P-type well contact area, a shallow trench isolation structure, and a charge guiding groove. The P-type substrate is formed above the grounding unit. The P-type well area is formed on the P-type substrate. The NMOS structure is formed on the P-type well area, and the NMOS structure includes at least one exposed N-type source area, at least one exposed N-type drain area, and at least one exposed N-type gate area. The P-type well contact area is formed on the P-type well area. The shallow trench isolation structure is disposed between the NMOS structure and the P-type well contact area. The charge guiding groove passes through the P-type well contact area and one part of the P-type well area and is electrically connected with the grounding unit. | 08-02-2012 |
20120114452 | TRANSPORT SYSTEM HAVING MULTILAYER TRACKS AND CONTROLLING METHOD THEREOF - A transport system having multilayer tracks is presented. The system has a bottom track and at least one top track disposed above on the bottom track. Shuttle carriages are moving along the top and bottom tracks. The shuttle body of each shuttle carriage has a first locking portion on the top end thereof, and has a second locking portion on the bottom end thereof. The second locking portion of the shuttle carriage on the top track can be locked with the first locking portion of the shuttle carriage on the bottom track. Therefore, the two transports on different tracks are locked so that the object can be transported between the top and bottom tracks. | 05-10-2012 |
20120104549 | MEMORY DEVICE AND FABRICATION THEREOF - The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing capacitance. | 05-03-2012 |
20120102052 | SPECIFICATION ESTABLISHING METHOD FOR CONTROLLING SEMICONDUCTOR PROCESS - A specification establishing method for controlling semiconductor process, the steps includes: providing a database and choosing a population from the database; sampling a plurality of sample groups from the population, each sample group being a non-normal distribution and having a plurality of samples; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value. | 04-26-2012 |
20120097499 | ROTARY TRANSPORT SYSTEM AND CONTROLLING METHOD THEREOF - A rotary transport system has a main track with transport(s) or shuttle(s) moving along the main track and an auxiliary storage unit. The auxiliary storage unit has a plurality of storing positions, and the storing positions are rotating around the main track. Therefore, the object, such as a FOUP (Front Opening Unified Pod) can be loaded on or unloaded from the storing positions. | 04-26-2012 |
20120033191 | DEVELOPER SPRAYING DEVICE FOR REDUCING USAGE QUANTITY OF DEVELOPER - A developer spraying device for reducing usage quantity of developer includes a hollow inner tube unit and a hollow outer tube unit. The hollow inner tube unit includes a hollow inner tube and a plurality of nozzles communicating an inner portion of the hollow inner tube with external world. The hollow inner tube has at least one liquid receiving space formed therein, and the liquid receiving space is filled with the developer. The hollow outer tube unit includes a hollow outer tube disposed around the hollow inner tube and tightly mated with the hollow inner tube and an opening formed on the hollow outer tube and communicating with an inner portion of the hollow outer tube. The hollow outer tube is selectively rotated clockwise or anticlockwise relative to the hollow inner tube, thus the nozzles are selectively exposed from the opening or shaded by the hollow outer tube. | 02-09-2012 |
20120012905 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased. | 01-19-2012 |
20120004890 | METHOD FOR AUTOMATICALLY SHIFTING A BASE LINE - A method for automatically shifting the base line has the following steps. First step is inserting the PM data into the processing data and calculating the original mean value of each section. Depending on the absolute value of the difference between each data point and the first mean value of each section, the data points are ranked. Next step is selecting the data points in the front N % of the ranked data points and then calculating the mean value and standard deviation. Next step is filtering the outlier data and calculating the base lines of each section. At last, the base lines are shifted and corrected into the same level so that the correlation error caused by base line shift is eliminated | 01-05-2012 |
20110318903 | MANUFACTURING METHOD FOR FIN-FET HAVING FLOATING BODY - A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide. | 12-29-2011 |
20110260230 | CELL WITH SURROUNDING WORD LINE STRUCTURES AND MANUFACTURING METHOD THEREOF - A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor. | 10-27-2011 |
20110257932 | METHOD FOR DETECTING VARIANCE IN SEMICONDUCTOR PROCESSES - A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is. | 10-20-2011 |
20110156285 | INTEGRATED ALIGNMENT AND OVERLAY MARK, AND METHOD FOR DETECTING ERRORS OF EXPOSED POSITIONS THEREOF - An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process. | 06-30-2011 |
20110153660 | METHOD OF SEARCHING FOR KEY SEMICONDUCTOR OPERATION WITH RANDOMIZATION FOR WAFER POSITION - A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor process. | 06-23-2011 |
20110139174 | METHOD OF CLEANING SHOWERHEAD - A showerhead cleaning rack is disclosed. The showerhead cleaning rack includes a frame and a support body, wherein the support body is located and connected with the frame. The support body has a plurality of positioning parts. The positioning parts are used for holding the showerhead. The showerhead cleaning rack is used in an ultrasonic cleaning trough. By utilizing the oscillation of the ultrasonic wave generated in the ultrasonic cleaning trough, the pollutants on the showerhead is cleaned. An ultrasonic cleaning method with the showerhead cleaning rack is also provided. | 06-16-2011 |
20110133248 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 06-09-2011 |
20110127574 | DEVICE FOR PREVENTING CURRENT-LEAKAGE - A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem. | 06-02-2011 |
20110112999 | METHOD FOR PREDICTING AND WARNING OF WAFER ACCEPTANCE TEST VALUE - A method for predicting and warning of WAT value includes the steps as follows. A key process is selected and a WAT value after finishing the key process is used as a predictive goal. A predicting model is built. One batch or plural batches of predictive wafers are prepared, and a Fault Detection and Classification data (FDC data) and a metrology data from the predictive wafers of the key process are collected. The FDC data and the metrology data collected from the predictive wafers are inputted into the predicting model for processing a normal predicting procedure, and a predictive WAT value by the predicting model is outputted. The present invention can accurately predict the WAT value, effectively monitor some specific defective wafers and continuously perform the improvement for the specific defective wafer. | 05-12-2011 |
20110111573 | LOW PARASITIC CAPACITANCE BIT LINE PROCESS FOR STACK DRAM - A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicons; applying a multi layer resist coat; removing the multi layer resist coat and further removing parts of the oxide located on the polysilicon to form contact holes exposing the plural polysilicons; depositing an oxide layer; etching the oxide layer to form the oxide layer spacer; depositing a polysilicon layer; performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer that is column-shaped to form capacitor contacts; and using another oxide to fill into the space among the word line stacks and the capacitor contacts. | 05-12-2011 |
20110101448 | VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is disposed on the substrate, and the bottom-oxide layer has a gate recess concavely formed thereof. The substrate has a first doped area in an upper part corresponding to the gate recess. The epitaxial silicon layer is formed on the gate recess, and the epitaxial silicon layer has a second doped area in an upper part. The insulating oxide layer is disposed on the epitaxial silicon layer. The gate-oxide films are respectively formed on two opposite sides of the epitaxial silicon layer. The gate-stacked layer is formed on the two gate-oxide layers and the bottom-oxide layer. Whereby, the lateral area of transistor is reduced, and the integration and the performance of the device are improved. | 05-05-2011 |
20110093226 | FAULT DETECTION AND CLASSIFICATION METHOD FOR WAFER ACCEPTANCE TEST PARAMETERS - A fault detection and classification (FDC) method for wafer acceptance test (WAT) parameters includes the following steps. A plurality of fault detection and classification parameters is collected. A plurality of wafer acceptance test parameters that are corresponded by the fault detection and classification parameters is collected. The fault detection and classification parameters are grouped. A contingency table of the wafer acceptance test parameters corresponding to the fault detection and classification parameters is built. A probability model of the contingency table is built. Finally, a safety range of the probability model is determined. | 04-21-2011 |
20110092044 | METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY - A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer. | 04-21-2011 |
20110086490 | SINGLE-SIDE IMPLANTING PROCESS FOR CAPACITORS OF STACK DRAM - A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film. | 04-14-2011 |
20110084843 | MANAGEMENT SYSTEM AND MANAGEMENT SYSTEM FOR JUDGING CORRECTNESS OF SUBSTANCE IN A BOTTLE - A management system includes a container unit, a sensing unit, a control unit, a signal display unit and a liquid pumping unit. The container unit has a container, a liquid substance and an information storing element. The liquid substance has material information recorded in the information storing element. The sensing unit has an information reader for sensing the material information when the sensing unit joined with the container unit. The control unit electrically connects the information reader to receive the material information. The control unit has a material judging module for judging whether the material information is correct in order to generate a judgment result. The signal display unit has a signal display module for outputting a predetermined signal according to the judgment result. The liquid pumping unit has a liquid pumping module selectively inserted into the container to pump the liquid substance according to the judgment result. | 04-14-2011 |
20110081763 | PROCESS USING OXIDE SUPPORTER FOR MANUFACTURING A CAPACITOR LOWER ELECTRODE OF A MICRO STACKED DRAM - A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer. | 04-07-2011 |
20110081222 | MULTI-TRACK HANDLING AND STORAGE APPARATUS AND METHOD THEREOF - A multi-track handling and storage apparatus includes at least two main tracks, at least two cranes and an intelligent integrated logic system. The main tracks are arranged separately, and every two adjacent main tracks are connected by at least one switching track. Bottoms of the cranes are slidably disposed on the main tracks. The intelligent integrated logic system includes a command receiving unit, a database unit, an analyzing unit, a crane dispatching unit and a route selection unit which are integrated with each other. The above-mentioned main tracks, switching tracks and cranes are controlled by the units of the intelligent integrated logic system. The present invention further provides a multi-track handling and storage method. | 04-07-2011 |
20110077767 | SYSTEM FOR TEMPORARILY SUPPLYING POWER AND A METHOD THEREOF - The method for temporarily supplying electric power includes steps of: providing a system which has a power supplying unit and a controlling unit for applying a temporary power to a broken semiconductor carrier of the semiconductor carrying facility; utilizing the power supplying unit to supply electric power to the broken semiconductor carrier; and utilizing the controlling unit to control movements of the broken semiconductor carrier. Thereby, the broken semiconductor carrier can be driven to a maintain area efficiently and safely. | 03-31-2011 |
20110076828 | METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY - A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes. | 03-31-2011 |
20110065253 | MANUFACTURING METHOD FOR DOUBLE-SIDE CAPACITOR OF STACK DRAM - A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors. | 03-17-2011 |
20110053337 | SELF-ALIGNMENT METHOD FOR RECESS CHANNEL DYNAMIC RANDOM ACCESS MEMORY - A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer. | 03-03-2011 |
20110010132 | METHOD FOR EVALUATING EFFICACY OF PREVENTION MAINTENANCE FOR A TOOL - A method for evaluating efficacy of prevention maintenance for a tool includes the steps of: choosing a tool which has been maintained preventively and choosing a productive parameter of the tool; collecting values of the productive parameter generated from the tool during a time range for building a varying curve of the productive parameter versus time, modifying the varying curve with a moving average method; transforming the varying curve into a Cumulative Sum chart; and judging whether the values of the productive parameter generated from the tool after the prevention maintenance are more stable, compared with the values of the productive parameter generated from the tool before the prevention maintenance, according to the Cumulative Sum chart. Thereby, if the varying of the values of the productive parameter after the prevention maintenance isn't stable, then the efficacy of this prevention maintenance for the tool is judged not good. | 01-13-2011 |
20100270599 | TRANSISTOR STRUCTURE WITH HIGH RELIABILITY AND METHOD FOR MANUFACTURING THE SAME - A transistor structure with high reliability includes a substrate unit, a solid ozone boundary layer, a gate oxide layer and a gate electrode. In addition, the substrate unit has a substrate body, a source electrode exposed on a top surface of the substrate body, and a drain electrode exposed on the top surface of the substrate body and separated from the source electrode by a predetermined distance. The solid ozone boundary layer is gradually grown on the top surface of the substrate body by continually mixing gaseous ozone into deionized water under 40˜95□, and the solid ozone boundary layer is formed between the source electrode and the drain electrode and formed on the substrate body. The gate oxide layer is formed on a top surface of the solid ozone boundary layer. The gate electrode is formed on a top surface of the gate oxide layer. | 10-28-2010 |
20100269856 | WAFER CLEANING MACHINE AND CLEANING METHOD THEREOF - The present invention provides a wafer cleaning machine, which includes a machine base, a rotating disk for bearing and driving a wafer, a first nozzle for spraying ion water to the surface of wafer, a brushing module, and a second nozzle. The rotating disk is connected with the machine base. The first nozzle is connected with the machine base and it is above the rotating disk. The brushing module is connected with the machine base and it is above the rotating disk. The second nozzle is connected with the machine base and it is above the rotating disk. | 10-28-2010 |
20100233830 | METHOD FOR MONITORING FABRICATION PARAMETER - A method for monitoring fabrication parameters comprises steps of: obtaining a normal parameter variance curve and a comparing parameter variance curve; defining a plurality of normal parameter points on the normal parameter variance curve; defining a plurality of comparing parameter points on the comparing parameter variance curve; finding out the corresponding comparing parameter points nearest to the normal parameter points; calculating the distances between the normal parameter points and the corresponding comparing parameter points thereof; summing up the distances so as to receive a total distance; and determining whether or not the total distance exceeds a limit. Via this arrangement, when fabrication parameter of tool is abnormal, it can be efficiently and immediately determined. | 09-16-2010 |
20100228382 | IN-LINE WAFER MEASUREMENT DATA COMPENSATION METHOD - An in-line wafer measurement data compensation method is presented, and the steps of the method includes: acquire a pre-wafer measurement data, a current wafer measurement data, and a current offset; establish an auto regressive integrated moving average (ARIMA) model and an exponential weighted integrated moving average (EWIMA) model, and input the pre-wafer measurement data, the current wafer measurement data, and the current offset to the ARIMA model and the EWIMA model; then get outputs of the ARIMA model and EWIMA model, wherein the outputs are wafer estimation data. Thereby, the semiconductor manufacturer could reduce the sampling time of an in-line measurement and still maintain an acceptable production performance and maintain control process stability. | 09-09-2010 |
20100223027 | MONITORING METHOD FOR MULTI TOOLS - A monitoring method for multi tools is disclosed. The method includes the steps of providing a plurality of measurement tools for measuring the testing points of standard wafers, calculating a vector for representing a measurement tool, calculating the angle between every two of the vectors and determining the measurement tools having the same performance or not. Thereby, the measurement tools can be efficiently grouped and the measuring stability of the measurement tool is analyzed. | 09-02-2010 |
20100215464 | AUTOMATIC PRODUCT DISTRIBUTION SYSTEM AND A METHOD THEREOF - An automatic product distribution system is disclosed. The product distribution system includes a distribution platform and a transportation platform. The distribution platform is used for distributing the products in the main storage unit into the secondary storage unit. The transportation platform is used for transporting the main storage unit and the secondary storage unit. The transportation platform transports the main storage unit and the secondary storage unit to the distribution platform and the distribution platform executes a distribution operation. After the distribution operation is finished, the transportation platform transports the secondary storage unit out of the distribution platform and transports another secondary storage unit to the distribution platform so that the distribution platform executes a distribution operation again. Thereby, the distribution platform can continuously execute the distribution operations. | 08-26-2010 |
20100205127 | METHOD FOR PLANNING A SEMICONDUCTOR MANUFACTURING PROCESS BASED ON USERS' DEMANDS - A method for planning a semiconductor manufacturing process based on users' demands includes the steps of: establishing a genetic algorithm model and inputting data; establishing a fuzzy system and setting one output parameter representing percent difference of each cost function in neighbor generations; setting to have a modulation parameter corresponding to each input parameter for adjusting fuzzy sets of the output parameter; executing genetic algorithm actions; executing fuzzy inference actions; eliminating chromosomes that produce output parameter smaller than a defined lower limit, and the remaining chromosomes that produces the largest output parameter is defined as the optimum chromosome, wherein the genetic algorithm actions stops being executed upon the optimum chromosome; then determining whether or not a defined number of generations has been reached, if yes, executing the optimum chromosome of the last generation; if no, continuing executing the genetic algorithm actions, thereby finding the optimum semiconductor manufacturing process for users. | 08-12-2010 |
20100196606 | LIQUID SUPPLYING DEVICE AND METHOD OF USING THE SAME - A liquid supplying device includes: a first liquid supplying element, a second liquid supplying element inside the first liquid supplying element, a first driving element connecting to the first liquid supplying element, and a second driving element connecting to the second liquid supplying element. The first liquid supplying element contains a first liquid, and the second liquid supplying element contains a second liquid. Therein the first driving element and the second driving element selectively control the first liquid or the second liquid to spray out from the liquid supplying device. A method of using a liquid supplying device is also provided. | 08-05-2010 |
20100175712 | SHOWERHEAD CLEANING RACK AND AN ULTRASONICCLEANING METHOD THEREFOR - A showerhead cleaning rack is disclosed. The showerhead cleaning rack includes a frame and a support body, wherein the support body is located and connected with the frame. The support body has a plurality of positioning parts. The positioning parts are used for holding the showerhead. The showerhead cleaning rack is used in an ultrasonic cleaning trough. By utilizing the oscillation of the ultrasonic wave generated in the ultrasonic cleaning trough, the pollutants on the showerhead is cleaned. An ultrasonic cleaning method with the showerhead cleaning rack is also provided. | 07-15-2010 |
20100150427 | PORTABLE WAFER INSPECTION SYSTEM - A portable wafer inspection system is applied on an inspection window of a manufacturing tool for wafers. The portable wafer inspection system comprises: a housing, a lighting unit, and an inspection unit. The housing has a receiving room therein, and a plurality of fixing members is disposed at the opening of the housing. The fixing members are used for fixing the housing on the inspection window of the manufacturing tool. The lighting unit and the inspection unit are disposed in the receiving room of the housing, wherein the inspection unit is for capturing images of the wafers. Thereby the inspection unit may be used for inspecting the wafers in the manufacturing tool through the inspection window | 06-17-2010 |
20100122771 | CHEMICAL TREATMENT APPARATUS - A chemical treatment apparatus includes an outer bath; an inner bath, located inside the outer bath; a circulation system, connecting the outer bath to the inner bath; and a draining system, having a first draining pipe and a connecting pipe, wherein the connecting pipe connects the first draining pipe to the circulation system. The suction force generated by a pump of the circulation system is thereby transferred to the first draining pipe. Therefore when the chemical solution is to be drained out from the inner bath, the draining of the chemical solution into the first draining pipe can be quickly done with the aid of the suction force. | 05-20-2010 |
20100117132 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor. | 05-13-2010 |
20100098855 | FURNACE TEMPERATURE CONTROL METHOD FOR THERMAL BUDGET BALANCE - A furnace temperature control method for thermal budget balance includes the steps of: placing a plurality of batches of wafers in the furnace; processing the wafers in the furnace via a heat deposition process; adjusting temperature in the furnace during the heat deposition process so that the temperature in the furnace has a temperature gradient; and controlling and inverting the temperature gradient so that the wafers in the furnace have the same thermal budget, whereby the electric parameters of the processed wafers tend to become uniform. Accordingly, considering the influence of the thermal budget, the present invention adjusts the temperature in the furnace and balances the thermal budget of the wafers in the furnace to avoid that the electric parameters of the processed wafers have extreme values, thereby improving the yield rate. | 04-22-2010 |
20100093114 | METHOD OF SEARCHING FOR KEY SEMICONDUCTOR OPERATION WITH RANDOMIZATION FOR WAFER POSITION - A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor process. | 04-15-2010 |
20100087968 | AUTOMATIC RECOVERY AND TRANSPORT SYSTEM AND EXECUTION METHOD THEREFOR - An automatic recovery and transport system includes a manufacture execution system, a path planning system electrically connected with the manufacture execution system, a vehicle control system electrically connected with the path planning system, a plurality of vehicles electrically connected with the vehicle control system; and an alarm system electrically connected with the path planning system and the vehicle control system. The alarm system will command the path planning system to command the vehicle control system to drive the vehicle about to stop to enter the maintenance area immediately. Accordingly, the stability and the work efficiency of the whole system are improved. The present invention also provides a method for executing an automatic recovery and transport system. | 04-08-2010 |
20100084555 | PREPARATION METHOD FOR AN ELECTRON TOMOGRAPHY SAMPLE WITH EMBEDDED MARKERS AND A METHOD FOR RECONSTRUCTING A THREE-DIMENSIONAL IMAGE - A manufacturing method for an electron tomography specimen with embedded fiducial markers includes the following steps. A chip of wafer is provided. The chip includes at least one inspecting area. At least one trench is produced beside the inspecting area. A liquid with the markers is filled into the trenches. A first protection layer is coated on the chip, and then a second protection layer is deposited on the first protection layer. Therefore, the markers can be embedded into the electron tomography specimen. The embedded markers can improve the alignment process, due to those embedded markers are easily tracked during feature tracking procedure. In addition, our novel invention also successfully provides a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3D reconstruction. | 04-08-2010 |
20100079296 | SYSTEM FOR MONITORING TEMPERATURE AND SLOPE OF A WAFER AND A METHOD THEREOF - A method for monitoring the temperature and slope of a wafer is presented, and the steps of the method comprises: (a) providing a cooling machine, a monitoring system, a sensing module, and a wafer; (b) cooling the wafer by the cooling machine; (c) sensing all regions of the wafer by the sensing module, and detecting the temperature and slope of the wafer relative to the cooling machine; (d) if the wafer's temperature is higher than a set temperature, the monitoring system outputs a first alarm signal, if the wafer's slope is greater than a set slope, the monitoring system outputs a second alarm signal. | 04-01-2010 |
20100076725 | METHOD FOR AUTOMATICALLY SHIFTING A BASE LINE - A method for automatically shifting the base line has the following steps. First step is inserting the PM data into the processing data and calculating the original mean value of each section. Depending on the absolute value of the difference between each data point and the first mean value of each section, the data points are ranked. Next step is selecting the data points in the first N % of the ranked data points and then calculating the mean value and standard deviation. Next step is filtering the outlier data and calculating the base lines of each section. At last, the base lines are shifted and corrected into the same level so that the correlation error caused by base line shift is eliminated | 03-25-2010 |
20100074718 | AUTOMATIC WAFER STORAGE SYSTEM AND A METHOD FOR CONTROLLING THE SYSTEM - An automatic wafer storage system and a method of controlling the system are disclosed. The automatic wafer storage system includes an analysis module and a storage unit. The analysis module estimates the locations between an idle equipment, a transport tool, and the storage unit, so as to control the storage unit and the transport tool to move to the best location for the transport tool to receive wafers from the storage unit. After that, the transport tool carries the wafers to the idle equipment for processing. | 03-25-2010 |
20100074717 | AUTOMATIC TRANSPORT SYSTEM AND CONTROL METHOD THEREOF - An automatic transport system includes: an overhead rail module having a plurality of transport rail sets, the transport rail sets each defining a bay; a plurality of overhead hoist transport vehicles movably disposed in the overhead rail module; and a control module electrically connected to the overhead hoist transport vehicles, the control module being used to control the number of the overhead hoist transport vehicles in the bays. Via this arrangement, the control module keeps some overhead hoist transport vehicles staying in each bay, thereby preventing one of the bays from having no overhead hoist transport vehicle to immediately use. This invention further provides a control method of the automatic transport system. | 03-25-2010 |
20100072400 | METHOD FOR CLEANING A HIGH RESOLUTION SCANNING ELECTRON MICROSCOPE SAMPLE WITH A LOW POWER ION BEAM - A method for cleaning a high resolution electron microscope sample with a low power ion beam includes the following steps. One sample is transmitted to a dual beam system to perform the milling operation. The sample includes at least one cross-sectional area. The cross-sectional area includes a plurality of active areas (AA), a plurality of gates, and a plurality of gate oxides (GOx). During the milling process, re-deposition is generated, and the re-deposition covers the active area of the cross-sectional area and the gate oxide in the middle of the gate. An ion beam is applied to the cross-sectional area to remove the re-deposition. An oxide etching operation is performed to the surface of the cross-sectional area to generate surface topography. A high resolution scanning electron microscope is used to obtain an image from the cross-sectional area. The active area and the gate oxide are checked and analyzed. | 03-25-2010 |
20100071513 | DEVICE FOR REMOVING A STOPPER OF A PHOTORESIST BOTTLE - A device for removing a stopper of a photoresist bottle is used for removing a stopper disposed on a photoresist bottle. The stopper includes a stopper element and at least two push buttons. The device includes a casing covering the stopper element and at least two levering units corresponding to the two push buttons. Each levering unit includes a lever pivotally disposed on the casing and a lifting element of which one end is pivotingly disposed on the lever and the other end abuts against a bottom of the stopper element. Under action of the moment, the stopper can be removed from a bottle mouth of the photoresist bottle. So users can remove the stopper with reduced effort and increased efficiency based on the present invention. | 03-25-2010 |
20100068010 | MINI CLEAN ROOM FOR PREVENTING WAFER POLLUTION AND USING METHOD THEREOF - A mini clean room for preventing wafer pollution includes a robot arm, a clean room body slidably disposed on the robot arm and at least one lock unit which is rotatably connected with the clean room body. During operation, the robot arm extends out of the clean room body to carry a wafer waiting to be processed, and then moves back into the clean room body which can provide an isolated and protected space for the wafer to avoid that the wafer is polluted. The present invention also discloses a method of using a mini clean room for preventing wafer pollution. | 03-18-2010 |
20100049680 | METHOD FOR PROJECTING WAFER PRODUCT OVERLAY ERROR AND WAFER PRODUCT CRITICAL DIMENSION - A method for projecting wafer product overlay error of the present invention is disclosed, the steps of the method comprises:(a) sample equipment overlay error data, equipment condition data, and actual wafer product overlay error data; (b) establish a neural network, the equipment overlay error data and the equipment condition data are inputs of the neural network, the generated output of the neural network is projected wafer product overlay error data, and the actual wafer product overlay error data is the target output of the neural network; and (c) set a mean square error target, train the neural network continuously until the mean square error of the neural network is no longer bigger than the mean square error target. Additionally a method for projecting wafer product critical dimension is also presented in the present invention. | 02-25-2010 |
20100049355 | METHOD FOR DETERMINING TOOL'S PRODUCTION QUALITY - A method for determining manufacturing tool production quality includes providing a table with manufacturing process data. The table is analyzed and a contingency table is established. The contingency table comprises several manufacturing tools, manufacturing processes, and the number of occurrences of bad lots. Split the contingency table up into a plurality of sub-tables. Use Cochran-Mantel-Haenszel test for determining the number of bad lots produced by the manufacturing tools and getting a plurality of statistics. Translate the statistics into a plurality of P-values. Sort the P-values for examining data automatically. Draw a line chart for detecting substandard manufacturing tools. As a result, users can diagnose the quality of the manufacturing tools. | 02-25-2010 |
20100025340 | GAS-LIQUID SEPARATION SYSTEM AND METHOD THEREOF - A gas-liquid separation system and a method thereof are disclosed. The said system comprises a gas-liquid separation conduit and a drain pipe. The drain pipe is curled and one side of the drain pipe connects to the gas-liquid separation conduit and the other side connects to a sewage pipe. According to the U-Tube principle, the gas and the liquid which both are exhausted by a machinery can be separated in the said system and therefore the said system can prevent related processes causing exhaust piping jam. | 02-04-2010 |
20100023160 | CROSS-FAB MATERIAL CONTROL SYSTEM AND CONTROL METHOD THEREOF - A cross-fab control system and a method for using the said system are disclosed. The said system comprises a first transport system, a second transport system, a cross-area control system, and a stocker. The first transport system connects the cross-area control system. The stocker connects the second transport system and the cross-area control system. The cross-area control system is utilized to identify Front Opening Unified Pod (FOUP) data on the stocker. By the assistance of the cross-area control system, the first transport system will transport the FOUP to destination through optimize path and avoid FOUP staying on the stocker with no transport command. | 01-28-2010 |
20100023158 | WAFER CASSETTE TRANSPORTATION METHOD AND SYSTEM THEREOF - A wafer cassette transportation method includes the steps: (a) Provide a monitoring system, overhead platforms, a detection system, and a plurality of transportation systems; (b) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits first signals to the monitoring system; (c) The monitoring system reads the first signals and instructs one of the transportation systems to move the wafer cassette to an empty overhead platform; (d) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits second signals to the monitoring system; and (e) The monitoring system reads the second signals and instructs another transportation system to move the wafer cassette away from the overhead platform, so as to enhance the transportation speed of the wafer cassette and lower the manufacturing cost. The present invention further provides a wafer cassette transportation system. | 01-28-2010 |
20100022101 | METHOD FOR CHANGING PHYSICAL VAPOR DEPOSITION FILM FORM - A method for changing a physical vapor deposition film form comprises: providing at least one sample with an active area; delivering the sample to a physical vapor deposition machine with one adjustable angle of one collimator; changing the angle of the collimator in the physical vapor deposition machine; performing physical vapor deposition operation, forming a uniform thin film disposed on one active area of the sample. | 01-28-2010 |
20100015735 | OBSERVATION METHOD OF WAFER ION IMPLANTATION DEFECT - An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability. | 01-21-2010 |
20100015536 | PHOTORESIST SOLUTION DISPENSING VOLUME MONITORING SYSTEM AND METHOD THEREOF - A photoresist solution dispensing volume monitoring system comprises: a photoresist solution dispensing apparatus having a photoresist bottle storing photoresist solution; and a weight scale being installed at the circumferential surface of the photoresist bottle, the weight scale measuring the weight of photoresist solution within the photoresist bottle. Via this arrangement, the monitoring system can monitor the practical photoresist solution dispensing volume and the predefined photoresist solution dispensing volume. If the two volumes are not the same, an alarm message will be produced to inform users. So the users can immediately examine or repair the photoresist solution dispensing apparatus. This present invention further provides a photoresist solution dispensing volume monitoring method. | 01-21-2010 |
20100010763 | METHOD FOR DETECTING VARIANCE IN SEMICONDUCTOR PROCESSES - A method of detecting variance by regression model is disclosed. Said method comprising: preparing the FDC and WAT data for analysis, figuring out what latent variable effect WAT by Factor Analysis, utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components, demonstrating how the tool and FDC affect WAT by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is. | 01-14-2010 |
20100004882 | FAULT DETECTION AND CLASSIFICATION METHOD FOR WAFER ACCEPTANCE TEST PARAMETERS - A fault detection and classification (FDC) method for wafer acceptance test (WAT) parameters includes the following steps. A plurality of fault detection and classification parameters is collected. A plurality of wafer acceptance test parameters that are corresponded by the fault detection and classification parameters is collected. The fault detection and classification parameters are grouped. A contingency table of the wafer acceptance test parameters corresponding to the fault detection and classification parameters is built. A probability model of the contingency table is built. Finally, a safety range of the probability model is determined. | 01-07-2010 |
20090327173 | METHOD FOR PREDICTING CYCLE TIME - A method for predicting cycle time comprises the steps of: collecting a plurality of known sets of data; using a clustering method to classify the known sets of data into a plurality of clusters; using a decision tree method to build a classification rule of the clusters; building a prediction model of each cluster; preparing data predicted set of data; using the classification rule to determine that to which clusters the predicted set of data belongs; and using the prediction model of the cluster to estimate the objective cycle time of the predicted set of data. Therefore, engineers can beforehand know the cycle time that one lot of wafers spend in the forward fabrication process, which helps engineers to properly arrange the following fabrication process of the lot of wafer. | 12-31-2009 |
20090306804 | METHOD FOR PROGNOSTIC MAINTENANCE IN SEMICONDUCTOR MANUFACTURING EQUIPMENTS - A method for prognostic maintenance in semiconductor manufacturing equipments is disclosed. The said method comprising: collecting a plurality of raw data from the default detection and classification system for equipments, preprocessing the raw data, using the neural network model (NN model) to find a plurality of health indices, generating health information by using the principal component analysis (PCA) to identify the health indices, and using the partial least square discriminated analysis (PLS-DA) to find a health report. The health report provides the engineers with current risk levels of equipments. By the health report, the engineers can initiate prognostic maintenance and repair the equipments early. | 12-10-2009 |
20090276261 | ASSESSMENT METHOD FOR PROCESS IMPROVEMENT DECISIONS - A risk assessment method for process improvement decisions applying for semiconductor process change comprises: performing a risk assessment evaluation to compute a polarity (plurality?) of items corresponding to their values, generating a risk assessment evaluation value to determine if the risk assessment evaluation value is in a risk setting value, go to next two steps; not, go to next step; performing an active inspect for the polarity (plurality?) of items corresponding to their item setting values, if not satisfied with the active inspect, repeat the above step; if not, transferring the semiconductor process change to online process. | 11-05-2009 |
20090276182 | MACHINE FAULT DETECTION METHOD - A machine fault detection method is applied to a plurality of machines. The machines are used for processing at least one wafer-in-process (WIP). The method includes the flowing steps. A statistical database of the wafer-in-process is provided. An association rules is used to search and survey the statistical database in order to calculate a support degree and a reliability degree. A threshold is selected to determine whether the support degree and the reliability degree have surpassed the threshold or not. When the support degree and the reliability degree have surpassed the threshold, a root cause error in the statistical database corresponded by the support degree and the reliability degree is determined. When the support degree and the reliability degree have not surpassed the threshold, the above steps are repeated. | 11-05-2009 |
20090259332 | FUZZY CONTROL METHOD FOR ADJUSTING A SEMICONDUCTOR MACHINE - A method of fuzzy control for adjusting a semiconductor machine comprising: providing measurement values from first the “parameter of a pre-semiconductor manufacturing process”, second the “parameter of the semiconductor manufacturing process”, and third the “operation parameter of the semiconductor manufacturing process”; performing a fuzzy control to define two inputs and one output corresponding to the measurement values, wherein the difference between the first and third values, and the difference between the second and third values, forms the two inputs, then from the two inputs one target output is calculated by fuzzy inference; finally, determining if the target output is in or out of an acceptable range. Whereby the target output is the “machine control parameter of the semiconductor manufacturing process” and when within an acceptable range is used for adjusting the semiconductor machine. | 10-15-2009 |
20090254208 | METHOD AND SYSTEM FOR DETECTING TOOL ERRORS TO STOP A PROCESS RECIPE FOR A SINGLE CHAMBER - A method for detecting tool errors to stop a process recipe for a single chamber is disclosed. When a recipe error for one of chamber of a process tool is detected, only the chamber with the recipe error is terminated and other chambers are allowed to proceed with their recipe processes for preventing excursions. | 10-08-2009 |
20090242954 | MEMORY DEVICE AND FABRICATION THEREOF - The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacitor, and in alternative embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing capacitance. | 10-01-2009 |
20090209100 | FABRICATION METHOD FOR MEMORY DEVICE - The invention provides a method for fabricating a memory device. At first, a substrate having a plurality of gate electrode stacks and a source/drain region is provided, and a barrier layer and a sacrificial layer are sequentially formed on the substrate and cover the gate electrode stacks. A portion of the sacrificial layer is removed to form a sacrificial plug between the gate electrode stacks, and then a filling layer is formed over the substrate. Next, the sacrificial plug is removed, and a contact hole is formed. A clean step with a solution containing ammonia is carried out. The barrier layer at the bottom of the contact hole is removed, and a metal plug is then formed in the contact hole to electrically contact with the source/drain region. | 08-20-2009 |
20090197354 | SYSTEM AND METHOD FOR MONITORING MANUFACTURING PROCESS - A system and method for monitoring a manufacturing process are provided. A wafer is provided. Process parameters of a manufacturing machine are in-situ measured and recorded if the wafer is processed in the manufacturing machine. A wafer measured value of the wafer is measured after the wafer has been processed. The process parameters are transformed into a process summary value. A two dimensional orthogonal chart with a first axis representing the wafer measured value and a second axis representing the process summary value is provided. The two dimensional orthogonal chart includes a close-loop control limit. A visualized point representing the wafer measured value and the process summary value is displayed on the two dimensional orthogonal chart. | 08-06-2009 |
20090196718 | HOLDING APPARATUS - A holding apparatus for holding a semiconductor wafer comprises a pneumatic cylinder, a plunger movably connected to the pneumatic cylinder, an inlet pipe connected to the pneumatic cylinder, and a relief valve connected to the inlet pipe. Clean dry air is pumped into the pneumatic cylinder through the inlet pipe to impel the plunger in a first direction to contact the wafer. A part of the air in the inlet pipe is discharged through the relief valve to regulate air pressure to the pneumatic cylinder. | 08-06-2009 |
20090188849 | COOLANT RECYCLING SYSTEM - A coolant recycling system is disclosed, including a chiller and a coolant filtering unit. The chiller includes a coolant tank, a compressor, a condenser and an expansion valve. The coolant tank includes an evaporator, a coolant outlet and an coolant inlet. The evaporator, the compressor, the condenser and the expansion valve are connected in sequence to form a refrigerant loop. The coolant filtering unit includes an unfiltered storage container, a dehydration filter and a filtered storage container. The unfiltered storage container is connected to the coolant outlet and the filtered storage container is connected to the coolant inlet. | 07-30-2009 |
20090137090 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. A first active region and a second active region are defined in a substrate. An electrode covering the first active region and the second active region is formed on the substrate. A first sacrificial layer is formed on the second active layer. A first work function electrode is formed on the first active layer by performing a first doping process to a portion of the electrode. The first sacrificial layer is removed. A second sacrificial layer is formed on the first active layer. | 05-28-2009 |
20090125853 | CIRCUIT STRUCTURE OF INTEGRATED CIRCUIT - A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved. | 05-14-2009 |