| GLOBALFOUNDRIES INC. Patent applications |
| Patent application number | Title | Published |
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| 20220238386 | METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF A VERTICAL TRANSISTOR - A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process. | 07-28-2022 |
| 20200119000 | FINFET HAVING UPPER SPACERS ADJACENT GATE AND SOURCE/DRAIN CONTACTS - Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts. | 04-16-2020 |
| 20190319112 | METHODS, APPARATUS AND SYSTEM FOR A SELF-ALIGNED GATE CUT ON A SEMICONDUCTOR DEVICE | 10-17-2019 |
| 20190280114 | METHODS, APPARATUS, AND SYSTEM FOR REDUCING GATE CUT GOUGING AND/OR GATE HEIGHT LOSS IN SEMICONDUCTOR DEVICES | 09-12-2019 |
| 20190280105 | FIN-TYPE TRANSISTORS WITH SPACERS ON THE GATES | 09-12-2019 |
| 20190279840 | SYSTEM AND METHOD FOR PERFORMING FAILURE ANALYSIS USING VIRTUAL THREE-DIMENSIONAL IMAGING | 09-12-2019 |
| 20190279708 | WRITE ASSIST | 09-12-2019 |
| 20190278166 | PHOTOLITHOGRAPHY SYSTEM AND METHOD USING A RETICLE WITH MULTIPLE DIFFERENT SETS OF REDUNDANT FRAMED MASK PATTERNS | 09-12-2019 |
| 20190271918 | SELF-ALIGNED QUADRUPLE PATTERNING PITCH WALKING SOLUTION - A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures. | 09-05-2019 |
| 20190004114 | REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS - A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal. | 01-03-2019 |
| 20180374946 | METHODS OF FORMING A BULK FIELD EFFECT TRANSISTOR (FET) WITH SUB-SOURCE/DRAIN ISOLATION LAYERS AND THE RESULTING STRUCTURES - Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage. | 12-27-2018 |
| 20180374857 | VERTICAL SRAM STRUCTURE - A vertical SRAM cell includes a first (1 | 12-27-2018 |
| 20180374851 | SINGLE-DIFFUSION BREAK STRUCTURE FOR FIN-TYPE FIELD EFFECT TRANSISTORS - A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method. | 12-27-2018 |
| 20180374753 | STACKED ELONGATED NANOSHAPES OF DIFFERENT SEMICONDUCTOR MATERIALS AND STRUCTURES THAT INCORPORATE THE NANOSHAPES - Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively. | 12-27-2018 |
| 20180374749 | MECHANICALLY STABLE COBALT CONTACTS - A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal. | 12-27-2018 |
| 20180108654 | FINFET DEVICE WITH LOW RESISTANCE FINS - A method of forming a FinFET device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin prior to a dopant activating anneal. The implanted carbon, which can be incorporated into the fin in conjunction with a replacement metal gate process after defining a sacrificial gate but prior to forming sidewall spacers on the gate, forms a barrier that impedes dopant diffusion across the barrier, which enables abrupt junctions and higher overall dopant concentrations within the semiconductor fin. | 04-19-2018 |
| 20180108571 | METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL - At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature. | 04-19-2018 |
| 20170263733 | FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME - The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps. | 09-14-2017 |
| 20170263707 | EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR - After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type. | 09-14-2017 |
| 20170263506 | METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE - At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area. | 09-14-2017 |
| 20170200786 | FABRICATION OF TRANSISTOR-BASED SEMICONDUCTOR DEVICE USING CLOSED-LOOP FINS - Shaped mandrels are used to form closed-loop spacer(s) around the shaped mandrels, after which the shaped mandrels are removed, leaving a closed-loop fin. A transistor includes U-shaped portion(s) of a closed-loop fin, and a gate across channel region(s) of the U-shaped portion(s) of a closed-loop fin. A semiconductor structure includes portion(s) of closed-loop fin(s), and transistors formed from the portion(s) of closed-loop fin(s). | 07-13-2017 |
| 20170200500 | CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO REDUCE LATENCY - Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word. | 07-13-2017 |
| 20170179248 | HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION - A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate. | 06-22-2017 |
| 20170178953 | METHODS AND DEVICES FOR BACK END OF LINE VIA FORMATION - Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed. | 06-22-2017 |
| 20170170293 | INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING - Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed. | 06-15-2017 |
| 20170170048 | WAFER HANDLER FOR INFRARED LASER RELEASE - A wafer handler includes a substrate having a front surface and a back surface, an antireflective layer formed over the back surface, a silicon nitride compensation layer formed over the front surface, and a release layer formed over the compensation layer. The wafer handler can be bonded to a device wafer for processing of the device wafer, and debonded from the device wafer using infrared radiation without damaging the device wafer or devices formed thereon. | 06-15-2017 |
| 20170162688 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 06-08-2017 |
| 20170162508 | STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS - Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall. | 06-08-2017 |
| 20170162234 | DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY - A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT. | 06-08-2017 |
| 20170154995 | REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS - After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin. | 06-01-2017 |
| 20170154816 | AMORPHOUS METAL INTERCONNECTIONS BY SUBTRACTIVE ETCH - A method of fabricating amorphous metal interconnections includes forming an amorphous metal layer over a base insulating layer on a semiconductor device using an amorphous metal having a non-crystalline structure. A portion of the amorphous metal layer is selectively removed to form a three dimensional pattern within a remaining portion of the amorphous metal layer. A fill insulating layer is disposed over the remaining portion of the amorphous metal layer and base insulating layer to fill the three dimensional pattern to form amorphous metal interconnects between semiconductor devices. | 06-01-2017 |
| 20170141031 | SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF - Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy. | 05-18-2017 |
| 20170139324 | ADDITIONS OF ORGANIC SPECIES TO FACILITATE CROSSLINKER REMOVAL DURING PSPI CURE - A formulation comprising an esterified polyamide resin with a photosensitive linkage, a polymerizable crosslinker, and an organic species is provided. The organic species is selected such that (a) when exposed to UV radiation, it copolymerizes with the polymerizable crosslinker and the photosensitive linkage on the esterified polyamide resin forming the crosslinking network, (b) during thermal cure the copolymer thus formed drops from polyimide backbones, and (c) wherein the thermal degradation temperature of the copolymer thus formed is lower than the thermal degradation temperature of the homopolymer formed from the polymerizable crosslinker and the thermal degradation temperature of the copolymer formed from the polymerizable crosslinker and the photosensitive linkage on the esterified polyamide resin. The formulation is useful in forming a semiconductor passivation layer and facilitates more complete removal of crosslinker using less stringent conditions. | 05-18-2017 |
| 20170047404 | SEMICONDUCTOR STRUCTURE WITH MULTILAYER III-V HETEROSTRUCTURES | 02-16-2017 |
| 20170047290 | METHODS AND DEVICES FOR METAL FILLING PROCESSES | 02-16-2017 |
| 20170047282 | REDUCING LINER CORROSION DURING METALLIZATION OF SEMICONDUCTOR DEVICES | 02-16-2017 |
| 20170047247 | SELF-ALIGNED BACK END OF LINE CUT | 02-16-2017 |
| 20170025347 | METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION - Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions. | 01-26-2017 |
| 20170025270 | METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL) - A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench. | 01-26-2017 |
| 20160380065 | SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) - Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods. | 12-29-2016 |
| 20160379972 | ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE - Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion. | 12-29-2016 |
| 20160379872 | METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS - A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation. | 12-29-2016 |
| 20160378906 | METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS - Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern. | 12-29-2016 |
| 20160336399 | GATE CONTACT STRUCTURE HAVING GATE CONTACT LAYER - There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length. | 11-17-2016 |
| 20160336183 | METHODS, APPARATUS AND SYSTEM FOR FABRICATING FINFET DEVICES USING CONTINUOUS ACTIVE AREA DESIGN - At least one method, apparatus and system disclosed herein for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the second layer. | 11-17-2016 |
| 20160336172 | LITHOGRAPHY STACK AND METHOD - Lithography stack, intermediate semiconductor devices, and methods of fabrication are provided. The method includes obtaining an intermediate semiconductor device with a substrate, applying a spin on carbon layer over the substrate, and applying a hardmask layer over the spin on carbon layer. The intermediate semiconductor device includes a substrate, a spin on carbon layer over the substrate, and a hardmask layer over the spin on carbon layer. The lithography stack includes a spin on carbon layer, an invisible hardmask layer over the spin on carbon layer, and a photoresist layer over the invisible hardmask layer. | 11-17-2016 |
| 20160335389 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVED STANDARD CELL DESIGN AND ROUTING FOR IMPROVING STANDARD CELL ROUTABILITY - At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value. | 11-17-2016 |
| 20160301534 | METHOD, APPARATUS AND SYSTEM FOR SECURITY APPLICATION FOR INTEGRATED CIRCUIT DEVICES | 10-13-2016 |
| 20160300922 | INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING | 10-13-2016 |
| 20160190324 | CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS - Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface. | 06-30-2016 |
| 20160190289 | METHODS OF FORMING TRANSISTOR STRUCTURES - Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure. | 06-30-2016 |
| 20160190262 | CONFINED EARLY EPITAXY WITH LOCAL INTERCONNECT CAPABILITY - A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material. | 06-30-2016 |
| 20160190255 | METHODS FOR FORMING FinFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE - A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer. | 06-30-2016 |
| 20160190140 | CAPACITOR STRAP CONNECTION STRUCTURE AND FABRICATION METHOD - Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor. | 06-30-2016 |
| 20160190014 | FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES - Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal. | 06-30-2016 |
| 20160190003 | REDUCING DEFECTS AND IMPROVING RELIABILITY OF BEOL METAL FILL - A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal. Protecting the other via(s) may include, prior to the removing, filling the other via(s) with an Energy Removal Film (ERF) up to a top surface of the first hard mask layer, and, after the removing, removing the ERF material. | 06-30-2016 |
| 20160165710 | METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER PROCESSING - At least one method, apparatus and system for providing an extreme ultraviolet beam for processing semiconductor wafers are disclosed. A level of the EUV beam is monitored. A determination is made as to whether the level of the EUV beam is below a predetermined level. In response to determining that the level of the EUV beam is below the predetermined level, a determination is made as to whether the output of at least one of the first or second laser devices has decreased from an initial level. The output of the at least one of the first or second laser devices is increased in response to determining that the output of at least one of the first or second laser devices has decreased from an initial level. | 06-09-2016 |
| 20160163862 | EPITAXIAL BLOCK LAYER FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate. | 06-09-2016 |
| 20160163850 | LDMOS FINFET DEVICE AND METHOD OF MANUFACTURE USING A TRENCH CONFINED EPITAXIAL GROWTH PROCESS - A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material. | 06-09-2016 |
| 20160163705 | FINFET WORK FUNCTION METAL FORMATION - An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities. | 06-09-2016 |
| 20160163645 | SEMICONDUCTOR STRUCTURE WITH BOTTOM-FREE LINER FOR TOP CONTACT - A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material. | 06-09-2016 |
| 20160163559 | METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE - Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region. | 06-09-2016 |
| 20160141379 | INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region. | 05-19-2016 |
| 20160141368 | TALL STRAINED HIGH PERCENTAGE SILICON-GERMANIUM FINS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (SiGe) fins on a semiconductor on insulator (SOI) substrate. The fins have a germanium (Ge) concentration which may differ from the Ge concentration within the top layer of the SOI substrate. The difference in Ge concentration between the fins and the top layer of the SOI substrate may range from approximately 10 atomic percent to approximately 40 atomic percent. This Ge concentration differential may be used to tailor a strain on the fins. The strain on the fins may be tailored to increase the critical thickness and allow for a greater height of the fins as compared to conventional strained fins of the same SiGe concentration formed from bulk material. | 05-19-2016 |
| 20160133716 | ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS - Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al | 05-12-2016 |
| 20160126352 | HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR - A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed. | 05-05-2016 |
| 20160126316 | TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF - Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure. | 05-05-2016 |
| 20160126141 | METHODS FOR FORMING FINFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE - A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer. | 05-05-2016 |
| 20160124308 | ALTERNATING SPACE DECOMPOSITION IN CIRCUIT STRUCTURE FABRICATION - Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material. | 05-05-2016 |
| 20160118473 | NON-PLANAR SCHOTTKY DIODE AND METHOD OF FABRICATION - A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs. | 04-28-2016 |
| 20160118468 | MULTIPLE LAYER INTERFACE FORMATION FOR SEMICONDUCTOR STRUCTURE - There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form. | 04-28-2016 |
| 20160118458 | METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES - Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues. | 04-28-2016 |
| 20160118414 | DUAL THREE-DIMENSIONAL AND RF SEMICONDUCTOR DEVICES USING LOCAL SOI - Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s). | 04-28-2016 |
| 20160118386 | SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY AND METHODS OF FABRICATION THEREOF - In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins. | 04-28-2016 |
| 20160118341 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 04-28-2016 |
| 20160118298 | OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION - Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure. | 04-28-2016 |
| 20160116435 | NANOCHANNEL ELECTRODE DEVICES - A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string. | 04-28-2016 |
| 20160111539 | HIGH MOBILITY PMOS AND NMOS DEVICES HAVING Si-Ge QUANTUM WELLS - At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer. | 04-21-2016 |
| 20160111514 | ULTRA-LOW RESISTANCE GATE STRUCTURE FOR NON-PLANAR DEVICE VIA MINIMIZED WORK FUNCTION MATERIAL - A non-planar semiconductor structure includes an ultra-low resistance gate structure. The non-planar structure includes a semiconductor substrate and raised semiconductor structures coupled to the substrate, a lower portion of the raised structures surrounded by a layer of isolation material. The structure further includes gate structures surrounding an upper portion of the raised structures, the gate structures including a conductive material and a layer of work function material present only in a limited area surrounding each raised structure. The limited area of work function material is achieved in fabrication by including dummy gate structures covering a layer of selectively removable material above the raised structures and a layer of hard mask material above the selectively removable layer, removing the selectively removable layer with the dummy gate structures, filling the resulting gate openings with work function material and then removing most of it, using the layer of hard mask material to delimit the limited area of work function material. | 04-21-2016 |
| 20160111406 | TOP-SIDE INTERCONNECTION SUBSTRATE FOR DIE-TO-DIE INTERCONNECTION - At least one method, apparatus and system disclosed involves a multi-die integrated circuit device. A first substrate portion having a first height is formed. A first device over the first substrate portion is formed. A second substrate portion having a second height is formed. A second device is formed over the second substrate portion. An interconnect substrate feature is formed above the first and second devices. The interconnect substrate is configured to accommodate a plurality of interconnect lines electrically coupling the first and second devices. | 04-21-2016 |
| 20160111339 | CONTACT LINERS FOR INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor. | 04-21-2016 |
| 20160111322 | FINFET SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE - There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin. | 04-21-2016 |
| 20160111320 | T-SHAPED FIN ISOLATION REGION AND METHODS OF FABRICATION - Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure. | 04-21-2016 |
| 20160110489 | METHODS, APPARATUS, AND SYSTEM FOR USING FILLER CELLS IN DESIGN OF INTEGRATED CIRCUIT DEVICES - At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout. | 04-21-2016 |
| 20160105179 | LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 04-14-2016 |
| 20160104774 | NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS) - A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure. | 04-14-2016 |
| 20160104707 | METHOD AND STRUCTURE FOR TRANSISTORS USING GATE STACK DOPANTS WITH MINIMAL NITROGEN PENETRATION - Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer. | 04-14-2016 |
| 20160104644 | PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE - Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode. | 04-14-2016 |
| 20160104621 | SEMICONDUCTOR DEVICE HAVING COMMON CONTACT AND GATE PROPERTIES - In one aspect there is set forth herein a semiconductor device wherein a contact conductive layer and a gate conductive layer include a common conductive material. In one aspect a source/drain region contact conductive layer of an nFET, and a gate conductive layer of a gate of the nFET can be fabricated to include an n material. In one aspect a source/drain region contact conductive layer of a pFET, and a gate conductive layer of the pFET can be fabricated to include an p material. | 04-14-2016 |
| 20160104541 | NOVEL OTPROM FOR POST-PROCESS PROGRAMMING USING SELECTIVE BREAKDOWN - At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data. | 04-14-2016 |
| 20160099333 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION - An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. | 04-07-2016 |
| 20160099329 | SUSPENDED BODY FIELD EFFECT TRANSISTOR - A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor. | 04-07-2016 |
| 20160099239 | METHODS, APPARATUS AND SYSTEM FOR REDUCTION OF POWER CONSUMPTION IN A SEMICONDUCTOR DEVICE - At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement. | 04-07-2016 |
| 20160099171 | DIMENSION-CONTROLLED VIA FORMATION PROCESSING - Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench. | 04-07-2016 |
| 20160099168 | METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE - Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure. | 04-07-2016 |
| 20160086952 | PREVENTING EPI DAMAGE FOR CAP NITRIDE STRIP SCHEME IN A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process. | 03-24-2016 |
| 20160086886 | NANOWIRE COMPATIBLE E-FUSE - An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion. | 03-24-2016 |
| 20160079397 | PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 03-17-2016 |
| 20160079242 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 03-17-2016 |
| 20160079168 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 03-17-2016 |
| 20160071962 | SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS - A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric. | 03-10-2016 |
| 20160071932 | FINFET STRUCTURES HAVING UNIFORM CHANNEL SIZE AND METHODS OF FABRICATION - Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof. | 03-10-2016 |
| 20160071742 | PHOTORESIST COLLAPSE METHOD FOR FORMING A PHYSICAL UNCLONABLE FUNCTION - An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function. | 03-10-2016 |
| 20160064523 | SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS - A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron. | 03-03-2016 |
| 20160064372 | ESD SNAPBACK BASED CLAMP FOR FINFET - There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate. | 03-03-2016 |
| 20160064371 | NON-PLANAR ESD DEVICE FOR NON-PLANAR OUTPUT TRANSISTOR AND COMMON FABRICATION THEREOF - Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit. | 03-03-2016 |
| 20160061880 | METHODS, APPARATUS AND SYSTEM FOR TDDB TESTING - At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) on a plurality of devices. A first device and a second device are provided for testing. A test signal is provided for performing a time-dependent dielectric breakdown (TDDB) test on the first and second devices. A selection signal for selecting said first and second devices for performing said TDDB test. The first and second devices are arranged in series with a first resistor such that based upon said selecting, the test signal is applied substantially simultaneously to the first and second devices through the first resistor. A determination is made as to whether a breakdown and/or a failure of at least one of the first and second devices has occurred based upon a change in voltage across the first resistor. | 03-03-2016 |
| 20160056231 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier. | 02-25-2016 |
| 20160054383 | SEMICONDUCTOR STRUCTURE HAVING TEST DEVICE - There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle. | 02-25-2016 |
| 20160049495 | SEMICONDUCTOR STRUCTURES WITH COPLANAR RECESSED GATE LAYERS AND FABRICATION METHODS - Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers. | 02-18-2016 |
| 20160049488 | SEMICONDUCTOR GATE WITH WIDE TOP OR BOTTOM - A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled. | 02-18-2016 |
| 20160049481 | TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS - Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them. | 02-18-2016 |
| 20160049427 | INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACT STRUCTURES FOR IMPROVED WINDOWS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates. | 02-18-2016 |
| 20160049401 | HYBRID CONTACTS FOR COMMONLY FABRICATED SEMICONDUCTOR DEVICES USING SAME METAL - A non-planar semiconductor structure, for example, a dual FinFET structure, includes a n-type semiconductor device and a p-type semiconductor device. Metal-insulator-semiconductor (MIS) contacts provide electrical connection to the n-type device, and metal-semiconductor (MS) contacts provide electrical connection to the p-type device. The metal of both MIS and MS contacts is a same n-type work function metal. In one example, the semiconductor of the MIS contact includes epitaxial silicon germanium with a relatively low percentage of germanium, the insulator of the MIS contact includes titanium dioxide, the semiconductor for the MS contact includes silicon germanium with a relatively high percentage of germanium or pure germanium, and the metal for both contacts includes a n-type work function metal. | 02-18-2016 |
| 20160049400 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 02-18-2016 |
| 20160049327 | METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES - Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s). | 02-18-2016 |
| 20160044023 | AUTHENTICATION POLICY ENFORCEMENT - A method of operating a network message interceptor for enforcing an authentication policy for communication over a network between first and second network endpoints, the interceptor being in communication with the network and external to the first and second endpoints, the network including transport layer security, the method comprising the steps of: intercepting a handshake message transmitted over the network between the first and second endpoints; extracting a certificate for an authenticating one of the endpoints from the handshake message; determining a validity status of the certificate for confirming an identity of the authenticating endpoint; and preventing communication between the first and second endpoints based on a negatively determined validity status of the certificate. | 02-11-2016 |
| 20160043190 | SEMICONDUCTOR STRUCTURE(S) WITH EXTENDED SOURCE/DRAIN CHANNEL INTERFACES AND METHODS OF FABRICATION - Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET. | 02-11-2016 |
| 20160043081 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 02-11-2016 |
| 20160035906 | PLANAR SEMICONDUCTOR ESD DEVICE AND METHOD OF MAKING SAME - An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit. | 02-04-2016 |
| 20160035820 | UNIAXIALLY-STRAINED FD-SOI FINFET - Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance. | 02-04-2016 |
| 20160035743 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other. | 02-04-2016 |
| 20160035728 | RETROGRADE DOPED LAYER FOR DEVICE ISOLATION - Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins. | 02-04-2016 |
| 20160035631 | Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices | 02-04-2016 |
| 20160027905 | BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION - A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region. | 01-28-2016 |
| 20160025805 | WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES - Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure. | 01-28-2016 |
| 20160020277 | THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE - Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current. | 01-21-2016 |
| 20160020204 | THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE - Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current. | 01-21-2016 |
| 20160005867 | SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact. | 01-07-2016 |
| 20160005657 | SEMICONDUCTOR STRUCTURE WITH INCREASED SPACE AND VOLUME BETWEEN SHAPED EPITAXIAL STRUCTURES - A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume. | 01-07-2016 |
| 20160005598 | INHIBITING DIFFUSION OF ELEMENTS BETWEEN MATERIAL LAYERS OF A LAYERED CIRCUIT STRUCTURE - Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer. | 01-07-2016 |
| 20150380510 | STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS - Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET. | 12-31-2015 |
| 20150380502 | METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET - Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs. | 12-31-2015 |
| 20150380409 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 12-31-2015 |
| 20150380405 | REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS - After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions. | 12-31-2015 |
| 20150380404 | NON-PLANAR STRUCTURE WITH EXTENDED EXPOSED RAISED STRUCTURES AND SAME-LEVEL GATE AND SPACERS - A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication. | 12-31-2015 |
| 20150380316 | UNIFORM EXPOSED RAISED STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICES - The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures. | 12-31-2015 |
| 20150380258 | METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE - Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights. | 12-31-2015 |
| 20150380246 | DIMENSION-CONTROLLED VIA FORMATION PROCESSING - Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench. | 12-31-2015 |
| 20150372140 | FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS - Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET. | 12-24-2015 |
| 20150372107 | SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS - Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions. | 12-24-2015 |
| 20150372084 | RAISED FIN STRUCTURES AND METHODS OF FABRICATION - A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench. | 12-24-2015 |
| 20150371899 | MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES - Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure. | 12-24-2015 |
| 20150364578 | METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE - Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions. | 12-17-2015 |
| 20150364540 | CAPACITOR AND CONTACT STRUCTURES, AND FORMATION PROCESSES THEREOF - Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor. | 12-17-2015 |
| 20150364336 | UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing. | 12-17-2015 |
| 20150357425 | BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions. | 12-10-2015 |
| 20150357332 | DEVICES AND METHODS OF FORMING BULK FINFETS WITH LATERAL SEG FOR SOURCE AND DRAIN ON DIELECTRICS - Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer. | 12-10-2015 |
| 20150357292 | METHODS OF FABRICATING DEFECT-FREE SEMICONDUCTOR STRUCTURES - Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure. | 12-10-2015 |
| 20150357285 | FORMATION OF CARBON-RICH CONTACT LINER MATERIAL - Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate. | 12-10-2015 |
| 20150349085 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers. | 12-03-2015 |
| 20150349083 | METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material. | 12-03-2015 |
| 20150348913 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS IN A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers. | 12-03-2015 |
| 20150348849 | TRANSISTOR WITH EMBEDDED STRESS-INDUCING LAYERS - A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities. | 12-03-2015 |
| 20150348830 | SHALLOW TRENCH ISOLATION - A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance. | 12-03-2015 |
| 20150348787 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING A GATE WITH REDUCED DEFECTS - A method for forming a gate of a semiconductor device includes providing a semiconductor substrate, forming an active region with trench isolation in the semiconductor substrate, providing a polysilicon layer disposed on the semiconductor substrate, and providing a hard mask layer disposed on the polysilicon layer. An ash resistant layer is disposed on the hard mask layer. Patterned portions of the ash resistant layer, the hard mask, and the polysilicon layer are moved, and the remaining portions of the ash resistant layer is wherein the patterned polysilicon layer defines the gate. The resistant layer inhibits or reduces the likelihood of pitting of the polysilicon layer and substrate during subsequent etching processes. | 12-03-2015 |
| 20150346271 | METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT - At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted. | 12-03-2015 |
| 20150340501 | FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE - Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. | 11-26-2015 |
| 20150340500 | SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS - Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation. | 11-26-2015 |
| 20150340497 | METHODS OF INCREASING SILICIDE TO EPI CONTACT AREAS AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer. | 11-26-2015 |
| 20150340491 | SPACER CHAMFERING FOR A REPLACEMENT METAL GATE DEVICE - Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching. | 11-26-2015 |
| 20150340471 | RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH - A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions. | 11-26-2015 |
| 20150340468 | RECESSED CHANNEL FIN DEVICE WITH RAISED SOURCE AND DRAIN REGIONS - A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin. | 11-26-2015 |
| 20150340467 | MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE - Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged. | 11-26-2015 |
| 20150340461 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 11-26-2015 |
| 20150340457 | METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE WITH A LARGER METAL SILICIDE CONTACT AREA AND THE RESULTING DEVICES - One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material. | 11-26-2015 |
| 20150340319 | E-FUSE STRUCTURE FOR AN INTEGRATED CIRCUIT PRODUCT - An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor. | 11-26-2015 |
| 20150340296 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area. | 11-26-2015 |
| 20150340289 | METHODS OF FABRICATING SEMICONDUCTOR FIN STRUCTURES - Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride. | 11-26-2015 |
| 20150340274 | METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AN INSULTATING LAYER - Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less. | 11-26-2015 |
| 20150340229 | TRANSISTOR(S) WITH DIFFERENT SOURCE/DRAIN CHANNEL JUNCTION CHARACTERISTICS, AND METHODS OF FABRICATION - Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics. | 11-26-2015 |
| 20150339429 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY (DSA) USING DSA TARGET PATTERNS - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary. | 11-26-2015 |
| 20150333162 | METHODS OF FORMING NANOWIRE DEVICES WITH METAL-INSULATOR-SEMICONDUCTOR SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES - A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner. | 11-19-2015 |
| 20150333155 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES - A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions. | 11-19-2015 |
| 20150333121 | SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 11-19-2015 |
| 20150333086 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS - A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions. | 11-19-2015 |
| 20150333067 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 11-19-2015 |
| 20150333062 | FINFET FABRICATION METHOD - Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins. | 11-19-2015 |
| 20150333057 | MEANDER RESISTOR - The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin. | 11-19-2015 |
| 20150332972 | FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES - A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure. | 11-19-2015 |
| 20150332963 | T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE - A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling. | 11-19-2015 |
| 20150332959 | METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION - Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions. | 11-19-2015 |
| 20150332934 | LITHOGRAPHIC STACK EXCLUDING SiARC AND METHOD OF USING SAME - A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess. | 11-19-2015 |
| 20150331988 | WIDE PIN FOR IMPROVED CIRCUIT ROUTING - Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size. | 11-19-2015 |
| 20150325692 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS - Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process. | 11-12-2015 |
| 20150325635 | METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES - Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues. | 11-12-2015 |
| 20150325622 | INTEGRATED CIRCUITS HAVING MAGNETIC TUNNEL JUNCTIONS (MTJ) AND METHODS FOR FABRICATING THE SAME - Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact. | 11-12-2015 |
| 20150325525 | FORMING INTERCONNECT STRUCTURE WITH POLYMERIC LAYER AND RESULTING DEVICE - Methods for forming an interconnect structure using a carbon-rich polymeric layer and the resulting devices are disclosed. Embodiments may include forming a carbon-rich polymeric layer above a semiconductor element, forming a silicon oxide material layer above the carbon-rich polymeric layer, and forming an interconnect through the silicon oxide material layer and the carbon-rich polymeric layer. | 11-12-2015 |
| 20150325482 | INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures. | 11-12-2015 |
| 20150325473 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 11-12-2015 |
| 20150325467 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner. | 11-12-2015 |
| 20150325445 | REDUCED SILICON GOUGING DURING OXIDE SPACER FORMATION - An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer. | 11-12-2015 |
| 20150325436 | SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN AND METHODS OF FORMING THE SAME - Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate. | 11-12-2015 |
| 20150318398 | METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches. | 11-05-2015 |
| 20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 11-05-2015 |
| 20150318345 | SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING - In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting. | 11-05-2015 |
| 20150318288 | VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL - Various methods of forming a vertical static random access memory cell and the resulting devices are disclosed. One method includes forming a plurality of pillars of semiconductor material on a substrate, forming first source/drain regions on a lower portion of each of the pillars, forming a gate electrode around each of the pillars above the first source/drain region, forming a second source/drain region on a top portion of each of the pillars above the gate electrode, wherein the first and second source/drain regions and the gate electrode on each pillar defines a vertical transistor, and interconnecting the vertical transistors to define a static random access memory cell. | 11-05-2015 |
| 20150318280 | WIDE-BOTTOM CONTACT FOR NON-PLANAR SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A wide-bottom contact to epitaxial structures in a non-planar semiconductor structure is provided. A starting structure includes a non-planar semiconductor structure, the structure including a semiconductor substrate, fins coupled to the substrate, and epitaxial structures (e.g., diamond-shaped silicon epitaxy) on the fins. Trenches to the epitaxial structures with roughly vertical sidewalls are created from a field oxide and photoresist. Silicide is formed on the epitaxial structures, and bottom contact portions (of metal, e.g., tungsten) are conformally created on the silicide. The vertical sidewalls allow for a wider bottom. Contact bodies are then formed on the bottom contact portions. | 11-05-2015 |
| 20150318215 | METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity. | 11-05-2015 |
| 20150318204 | SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT - Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch. | 11-05-2015 |
