| FUJITSU MICROELECTRONICS LIMITED Patent applications |
| Patent application number | Title | Published |
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| 20130010628 | SYSTEM AND METHOD FOR COOPERATIVE DATA TRANSFER - A method for cooperative data transfer includes establishing a primary wireless connection with a primary access station. The primary wireless connection uses a primary synchronization channel that is transmitted during a first frame of a super frame. The super frame comprises a plurality of frames. The method also includes detecting a secondary synchronization channel generated by an alternate access station during a subsequent frame of the super frame. The method further includes determining whether the detected secondary synchronization channel has a signal strength greater than a threshold signal strength. The method additionally includes receiving permission to begin a cooperative data transfer operation with both the primary access station and the alternate access station. | 01-10-2013 |
| 20120300559 | SEMICONDUCTOR MEMORY INCLUDING PADS COUPLED TO EACH OTHER - A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal. | 11-29-2012 |
| 20110217940 | Radio-Frequency Transmitter and Amplifier - A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal. | 09-08-2011 |
| 20110148495 | DATA HOLDING CIRCUIT - A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element. | 06-23-2011 |
| 20110049675 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode. | 03-03-2011 |
| 20110006803 | LATCH CIRCUIT - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 01-13-2011 |
| 20100321983 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS - A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit. | 12-23-2010 |
| 20100316003 | System And Method For Adjusting Channels In Wireless Communication - According to one embodiment, a method for wireless communication includes performing a first scan of a plurality of wireless channels of a wireless communication network by simultaneously utilizing at least two radios of a base station. The method also includes determining a channel quality metric for at least two of the wireless channels in response to the first scan. The method further includes selecting a first wireless channel of the plurality of wireless channels in response to determining the channel quality metrics. In addition, the method includes communicating on the first wireless channel utilizing the at least two radios of the base station. | 12-16-2010 |
| 20100308420 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film. | 12-09-2010 |
| 20100283879 | Solid-State Image Pickup Apparatus Including A Global Shutter Function and Control Method Therefor - A solid-state image pickup apparatus includes a pixel unit consisting of a plurality of pixels; a pixel control unit for controlling the plurality of pixels; a readout unit for reading a signal of each pixel output from the pixel unit; a shutter unit for establishing a state of a light incident to the pixel unit and that of shielding the pixel unit from the light; and a control unit. The control unit includes an exposure mode changeover unit for changing over an exposure mode to either a first exposure mode performing a simultaneous exposure for all pixels or a second exposure mode performing an exposure for each of a predetermined unit of pixels. The control unit controls the pixel control unit, readout unit and shutter unit according to an exposure mode changed over by the exposure mode changeover unit. | 11-11-2010 |
| 20100283440 | POWER SUPPLY DEVICE, CONTROL CIRCUIT AND METHOD FOR CONTROLLING POWER SUPPLY DEVICE - A power supply device including a converter having a switch circuit to which an input voltage is supplied and a coil coupled between the switch circuit and an output end from which an output voltage is output; and a control circuit comparing between a feedback voltage and a reference voltage, and on/off controls the switch circuit according to a comparison result; wherein, the control circuit includes a current gradient detection circuit performs detection of a gradient of a coil current flows thorough the coil during an off period of the switch circuit and generates a slope voltage according to a result of the detection; and an adder circuit performs one of generating the feedback voltage by adding the slope voltage to a voltage according to the output voltage and generating the reference voltage by adding the slope voltage to a standard voltage that is set according to the output voltage. | 11-11-2010 |
| 20100271054 | INTEGRATED CIRCUIT DEVICE HAVING GROUND OPEN DETECTION CIRCUIT - An integrated circuit device includes a chip having a power supply terminal, a ground terminal, an input terminal, and an internal circuit formed therein. The chip comprises: a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal. | 10-28-2010 |
| 20100270623 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor. | 10-28-2010 |
| 20100259972 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory has a short transistor coupling complementary storage nodes of a latch circuit of a memory cell. A transfer transistor and the short transistor have a diffusion layer in common coupled to one of the storage nodes. The short transistor and a driver transistor have a diffusion layer in common coupled to the other storage node. The transfer transistor, the short transistor, and the driver transistor are continuously disposed via the diffusion layers in common, and thereby, variation of characteristics of the transfer transistor can be prevented. Accordingly, it may be possible to prevent that current supplying ability of the transfer transistor changes depending on a layout in the memory cell, and that an operation margin of the memory cell deteriorates. | 10-14-2010 |
| 20100253795 | IMAGE PROCESSING DEVICE - When a still picture is picked up by a digital camera, the still picture is divided into a plurality of areas and is processed for each area. After the process of one divided area is completed, then the process of a motion picture obtained from an imaging device. After the process of the motion picture is completed, another divided area of the still picture is processed again. Such switching between a motion picture process and a still picture process is performed until the process of the entire still picture is completed. Thus, after a still picture is picked up by a digital camera, a motion picture can be promptly displayed and a live image picked up by the camera can be displayed on a back LCD screen. | 10-07-2010 |
| 20100253419 | SEMICONDUCTOR DEVICE AND SYSTEM - A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased. | 10-07-2010 |
| 20100253414 | SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. | 10-07-2010 |
| 20100251022 | INTEGRATED CIRCUIT, DEBUGGING CIRCUIT, AND DEBUGGING COMMAND CONTROL METHOD - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 09-30-2010 |
| 20100250872 | INTERFACE, MEMORY SYSTEM, AND ACCESS CONTROL METHOD - An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle. | 09-30-2010 |
| 20100248453 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element. | 09-30-2010 |
| 20100246978 | DATA VERIFICATION METHOD, DATA VERIFICATION DEVICE, AND DATA VERIFICATION PROGRAM - A data verification method includes extracting a first graphic and a second graphic from a first circuit pattern, extracting a third graphic and a fourth graphic from a second circuit pattern, the second circuit pattern being in a layer different than a layer including the first circuit pattern; performing transformation on the first graphic; comparing the first graphic having undergone the transformation with the second graphic; performing the transformation on the third graphic; comparing the third graphic having undergone the transformation with the fourth graphic; when the first graphic having undergone the transformation matches the second graphic, and the third graphic having undergone the transformation matches the fourth graphic, performing grouping for the first and second graphics and setting the first graphic as a first representative graphic; and verifying a shape of the first circuit pattern based on the first representative graphic. | 09-30-2010 |
| 20100246079 | POWER SUPPLY CLAMP CIRCUIT - A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other. | 09-30-2010 |
| 20100244952 | GAIN CONTROL CIRCUIT AND ELECTRONIC VOLUME CIRCUIT - A gain control circuit includes a comparator that compares an input gain value with a count value to generate a comparison result signal, a counter that counts up or counts down the count value in accordance with the comparison result signal, and a gain modulator circuit that modulates the count value to generate a gain control signal which changes in a time-divided manner. The gain modulator circuit modulates the count value so that a gain obtained by time-averaging a gain corresponding to the gain control signal matches a gain based on the count value. | 09-30-2010 |
| 20100244933 | ELECTRIC FUSE CUTOFF CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit. | 09-30-2010 |
| 20100244909 | LOW-SPEED DRIVER CIRCUIT - A driver circuit includes an output transistor circuit that includes a first transistor of a first conductivity type and a second transistor of a second conductivity type disposed between a supply voltage source and a reference voltage source, and that outputs an output signal from a connection node between the first transistor and the second transistor, a first pre-buffer circuit that drives a gate of the first transistor in response to an input signal, and a second pre-buffer circuit that drives a gate of the second transistor in response to the input signal. | 09-30-2010 |
| 20100244199 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring. | 09-30-2010 |
| 20100240211 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device. | 09-23-2010 |
| 20100240177 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate. | 09-23-2010 |
| 20100237905 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor. | 09-23-2010 |
| 20100237841 | POWER SUPPLY AND POWER CONTROL DEVICE - A power supply includes a first switch and a second switch coupled in series between an input voltage terminal to which an input voltage is applied and a reference voltage terminal to which a reference voltage lower than the input voltage is applied, an inductor disposed between a junction coupling the first and second switches and an output terminal from which an output voltage is output, and a controller controlling the first and second switches to be alternately switched at a given switching cycle depending on an error of the output voltage with respect to a target voltage, wherein the controller changes the switching cycle from a first cycle to a second cycle longer than the first cycle, depending on a voltage at the junction when the second switch is in a turned-on state. | 09-23-2010 |
| 20100235796 | VERIFICATION APPARATUS - A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions. | 09-16-2010 |
| 20100235686 | EXECUTION HISTORY TRACING METHOD - An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target. | 09-16-2010 |
| 20100232679 | PATTERN VERIFICATION METHOD, PATTERN VERIFICATION APPARATUS, AND PATTERN VERIFICATION PROGRAM - A pattern verification apparatus includes a correction section creating a plurality of first data pieces; a determination section performing light intensity simulation to create a plurality of plots, determine whether or not each of the plurality of simulation result plots falls within an allowable range, and recognize two or more simulation result plots which do not fall within the allowable range as a plurality of second data pieces; an extraction section extracting a reference pattern of the plurality of original design patterns corresponding to the plurality of second data pieces; and a classifying section classifying the plurality of second data pieces into categories of the reference pattern. | 09-16-2010 |
| 20100232530 | COMMUNICATION APPARATUS - A communication apparatus includes a transmitter for transmitting an outgoing radio signal, a receiver for receiving an incoming radio signal, and a controller for controlling a direct current carrier leakage, and the transmitter includes a first multiplier for multiplying a first carrier-wave signal by an In-phase signal, a second multiplier for multiplying a signal having the similar frequency as and a phase shifted by 90 degree with respect to the first carrier-wave signal by a Quadrature-phase signal, and a transmitting amplifier for amplifying a composite signal multiplied by the In-phase signal and the Quadrature-phase signal, respectively, and outputting the composite signal for forming the outgoing radio signal. | 09-16-2010 |
| 20100231766 | IMAGING DEVICE - An imaging device includes an image sensing device provided on a semiconductor substrate; a transparent member provided on a light-receiving area of the image sensing device; and a circuit element provided on the transparent member, wherein the image sensing device and the circuit element are electrically coupled to each other. | 09-16-2010 |
| 20100231759 | IMAGE PROCESSING APPARATUS - An image processing apparatus includes, a color correction unit performing color correction on RGB signals to generate color-corrected RGB signals; a YC conversion unit converting the color-corrected RGB signals into a first luminance signal and a color-difference signal; a Y conversion unit generating a second luminance signal based on the RGB signals; an edge combination unit combining the first luminance signal with the second luminance signal; an edge adjustment unit obtaining an edge-adjusted signal based on a result of the combining by the edge combination unit; and an adder adding the first luminance signal to the edge-adjusted signal. | 09-16-2010 |
| 20100229134 | LAYOUT VERIFICATION METHOD - A layout verification method for verifying a layout of a semiconductor device by a computer having a memory storing layout data and information of operation conditions for a plurality of operation modes in which the semiconductor device is expected to assume during its testing and practical use, the semiconductor device including a semiconductor substrate of one conductivity type, a plurality of wells accommodating at least one of the circuit elements and being applicable to a plurality of different bias voltages in dependence of the operation modes, the method includes specifying combination of all the adjacent pairs of the wells located adjacently to each other within the semiconductor substrate, and the distance of each of all the adjacent pairs of the wells in reference to the layout data, determining, for each of the wells. | 09-09-2010 |
| 20100225356 | LATCH CIRCUIT - A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit. | 09-09-2010 |
| 20100225354 | LOOKUP TABLE, SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR MAKING LOOKUP TABLE AND METHOD FOR MAKING SEMICONDUCTOR INTEGRATED CIRCUIT - A lookup table includes a single via layer having 2 | 09-09-2010 |
| 20100225292 | CONTROL CIRCUIT FOR DC-DC CONVERTER, DC-DC CONVERTER, AND METHOD FOR CONTROLLING DC-DC CONVERTER - A DC-DC converter control circuit includes: a slope signal generation circuit that generates a reference voltage by superimposing a slope voltage onto a standard voltage; a comparator that performs comparison of the reference voltage with an output voltage and generates a signal according to a result of the comparison; an oscillator that generates a pulse signal with a substantially constant cycle; and a control signal generation circuit that generates a control signal that turns on a switch based on a comparator output signal and turns off the switch based on the pulse signal. | 09-09-2010 |
| 20100224997 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer. | 09-09-2010 |
| 20100224921 | SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AO | 09-09-2010 |
| 20100220928 | IMAGE PROCESSING METHOD - An image processing method performed by a processor for processing a plurality of pixel values in an image data representing a two-dimensional image, the image processing method including defining a block representing a part of the two-dimensional image corresponding to a predetermined number of pixels in rows and columns, obtaining an average of a gradient of pixel value on the basis of the pixel values of adjacent pixels in the block along each of at least one of rows and at least one of columns, generating a product of the average of the gradient pixel value along each of at least one of the rows and the average of the gradient pixel value along each of at least one of the columns, and generating a double summation of the products of the gradient pixel values of each of the rows and the columns. | 09-02-2010 |
| 20100219869 | SEMICONDUCTOR INTERGRATED CIRCUIT AND SIGNAL ADJUSTING METHOD - A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings, a second signal generator that generates a third signal having a delay relative to the first signal, and a detector that detects, when a state of the third signal changes, a delay state of a signal based on the states of the second signals, wherein the first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state. | 09-02-2010 |
| 20100219508 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion. | 09-02-2010 |
| 20100218166 | COMPUTER PRODUCT, IP MODEL GENERATING APPARATUS, AND IP MODEL GENERATING METHOD - A computer-readable recording medium stores therein an IP model that combines source code of IPs that include an interface representing input/output of data; a register storing the data; a behavior executing processing based on the data; and a state performing wait processing according to time information from the interface and a connection code indicative of a connecting relation between the IPs. | 08-26-2010 |
| 20100218057 | CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal. | 08-26-2010 |
| 20100217914 | MEMORY ACCESS DETERMINATION CIRCUIT, MEMORY ACCESS DETERMINATION METHOD AND ELECTRONIC DEVICE - A memory access determination circuit includes a counter that outputs a first value counted by using a first reference value, and a control unit that makes a cache determination of an address corresponding to an output of the counter, wherein, when a cache miss occurs for the address, the counter outputs a second value by using a second reference value. | 08-26-2010 |
| 20100214823 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR - A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer. | 08-26-2010 |
| 20100214446 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - An image processing apparatus includes an image pickup circuit that performs photoelectric conversion on an optical image, and a chromatic aberration correcting circuit that calculates an amount of shift by chromatic aberration based on a linear function to perform chromatic aberration correction on captured image data in accordance with the amount of shift. The chromatic aberration correcting circuit performs the chromatic aberration correction on a first pixel in a first area including an optical center of the captured image data with a first linear function using a distance from the optical center, and performs the chromatic aberration correction on a second pixel in a second area that does not include the optical center and that is different from the first area with a second linear function using the distance from the optical center. | 08-26-2010 |
| 20100214143 | deltasigma MODULATION CIRCUIT AND SYSTEM - A ΔΣ modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators. | 08-26-2010 |
| 20100214004 | ANALOG SWITCH CIRCUIT - An analog switch circuit that includes a first field-effect transistor, a source of which is coupled to a first switch terminal, and a drain of which is coupled to a second switch terminal; a first capacitance storing electric charge; a second capacitance storing electric charge; a first switch circuit that couples the first capacitance between a direct current voltage node and a reference potential node; a second switch circuit that couples the first capacitance and the second capacitance in parallel; and a third switch circuit that couples the second capacitance between a gate and the source of the first field-effect transistor. | 08-26-2010 |
| 20100213979 | SEMICONDUCTOR DEVICE AND METHOD FOR LAYOUTING SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the power source voltage line and the ground line, including at least two second MOS transistors coupled in series. The gate length and the gate width of the first MOS transistor are adjusted so that the first MOS transistor has a gate area allowing a first characteristic variation of the first MOS transistor to be substantially equal to a second characteristic variation of the second MOS transistor. | 08-26-2010 |
| 20100213970 | Semiconductor integrated circuit and method for testing the same - A semiconductor integrated circuit includes a plurality of clock gating circuits, a plurality of flip-flops to which transmission of a clock signal is controlled by a respective clock gating circuit, and a clock gating control circuit that controls an active state and an inactive state of the plurality of clock gating circuits, wherein during a test operation mode, the clock gating control circuit controlling the active state and the inactive state of the plurality of clock gating circuits according to a user logic signal, and controlling setting of an arbitrary combination of clock gating circuits to an inactive state regardless of the user logic signal. | 08-26-2010 |
| 20100213911 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY DEVICE - A semiconductor integrated circuit includes: a first switching element and a second switching element that are provided in series between a first power line and a second power line; a power supply circuit that outputs a given output voltage by on/off controlling the first switching element and the second switch element; a current detection circuit that detects a current corresponding to an output load current of the power supply circuit; a switching time control circuit that controls a switching time defined by a power supply voltage and the output voltage based on a current value detected by the current detection circuit; and a switching element control circuit that controls the first switching element and the second switching element based on an output signal of the switching time control circuit. | 08-26-2010 |
| 20100211746 | CACHE DEVICE - A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory. | 08-19-2010 |
| 20100210083 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first cap film over gate electrodes formed in a first active region and a second active region, etching the first cap film over the first active region, forming a second cap film over the gate electrodes formed in the first active region and the second active region, etching the second cap film over the first active region, etching the first active region using the gate electrodes to form concave portions in the first active region, and embedding a semiconductor material in the concave portions. | 08-19-2010 |
| 20100208978 | METHOD OF INSPECTING MASK PATTERN AND MASK PATTERN INSPECTION APPARATUS - A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not. | 08-19-2010 |
| 20100208755 | SIGNAL PROCESSOR AND COMMUNICATION DEVICE - A signal processor includes a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller, configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of a frame, the controller to halt startup of communication action of the next frame, until the period being currently used for communication of a frame comes to the end, to thereby reduce an event such that frames are transmitted from a plurality of communication devices simultaneously, and to thereby allow the communication action for the next frame to proceed correctly. | 08-19-2010 |
| 20100207694 | PLL CIRCUIT AND OSCILLATOR DEVICE - A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal. | 08-19-2010 |
| 20100203682 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device including a semiconductor device, an integrated circuit chip, a sealing resin encapsulating the integrated circuit chip and an insulating waterproof film covering at least a portion of a surface of said sealing resin and preventing penetration of moisture into the sealing resin. | 08-12-2010 |
| 20100201449 | AMPLIFIER - An amplifier including a first transistor including a gate coupled to an input terminal and a grounded source; a load resistor provided between a drain of the first transistor and a power supply; an output terminal coupled to a node between the drain of the first transistor and the load resistor; a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor; a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal; a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path. | 08-12-2010 |
| 20100201448 | OUTPUT CIRCUIT OF RADIO-FREQUENCY TRANSMITTER - An output circuit including a fine-adjustment VGA and a rough-adjustment VGA, where the maximum gain of the fine-adjustment VGA, as attained when the minimum gain of the rough-adjustment VGA is attained, is lower than the maximum gain of the fine-adjustment VGA as attained when the maximum gain of the rough-adjustment VGA is attained, so that the power consumption of the rough-adjustment VGA is reduced | 08-12-2010 |
| 20100197251 | POWER AMPLIFIER COMPRISING A SLOTTED POWER COMBINER - According to one embodiment, a power combiner configured to receive at least two input signals and combine the input signals to generate an output signal. The power combiner may include at least two input layers and an output layer located between the input layers. Each layer may be in the shape of a slotted loop. | 08-05-2010 |
| 20100197046 | SEMICONDUCTOR DEVICE - A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film. | 08-05-2010 |
| 20100194620 | ANALOG/DIGITAL CONVERTER - An A/D converter includes a plurality of comparators that performs sampling of a plurality of reference voltages and analog input signals during a sampling time, and compares each of the plurality of reference voltages with each of the plurality of analog signals during a comparison time. The A/D converter detects bubbles in thermometer codes obtained from output signals of the plurality of comparators and adjusts a ratio of the sampling time and the comparison time of the plurality of comparators so as to reduce the bubbles. | 08-05-2010 |
| 20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 08-05-2010 |
| 20100194352 | CHARGING CIRCUIT, CHARGING APPARATUS, ELECTRONIC EQUIPMENT AND CHARGING METHOD - A charging circuit includes a monitoring part configured to monitor a battery voltage applied to a battery and configured to output an overvoltage signal when the battery is in an overvoltage condition a protection part configured to electrically disconnect the battery from an adaptor when receiving the overvoltage signal, and a switch which, when the battery is electrically disconnected from the adaptor, switches a monitoring node for an adaptor voltage outputted from the adaptor, from a supply node of the battery voltage to a supply node of a system voltage, which is applied to a system electrically connected with the battery and the adaptor, based on the overvoltage signal to cause a control command for controlling the adaptor voltage based on the system voltage to be outputted. | 08-05-2010 |
| 20100193965 | SEMICONDUCTOR DEVICE HAVING WIRINGS FORMED BY DAMASCENE - An insulating film is formed over a semiconductor substrate. A wiring trench formed in the insulating film reaches partway in a thickness direction of the insulating film. A via hole is disposed at an end of the wiring trench. A barrier metal film covers inner surfaces of the wiring trench and via hole. A bottom of the wiring trench and a sidewall of the via hole are connected via an inclined plane. A length of a portion of the inclined plane having an inclination angle range of 40° to 50° relative to a surface of the semiconductor substrate is equal to or shorter than a maximum size of a plan shape of the via hole, in a cross section which is parallel to a longitudinal direction of the wiring trench, passes a center of the via hole and perpendicular to the surface of the semiconductor surface. | 08-05-2010 |
| 20100193851 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring. | 08-05-2010 |
| 20100193846 | SEMICONDUCTOR DEVICE WITH STRAIN - A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region. | 08-05-2010 |
| 20100191982 | DEVICE - A device is provided which includes: a processor that outputs a command signal or an address signal and includes a bus module which inputs or outputs a data signal; and an encryption circuit that encrypts or decrypts the data signal in an encryption method using a common key and the address signal, wherein the processor and the encryption circuit are provided in a chip. | 07-29-2010 |
| 20100190327 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND DESIGN SUPPORT APPARATUS - A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode. | 07-29-2010 |
| 20100188922 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRIC APPARATUS - A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros. | 07-29-2010 |
| 20100188907 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state. | 07-29-2010 |
| 20100188542 | IMAGING DEVICE AND IMAGE SENSOR CHIP - An imaging device includes a pixel array that includes a plurality of pixels, a data read circuit that sequentially reads the data of a given line from the pixel array, a plurality of column analog-digital converters that perform analog-digital conversion on the data from the data read circuit, and a control signal generating circuit that generates a control signal to control the analog-digital conversion. | 07-29-2010 |
| 20100188277 | SUCCESSIVE APPROXIMATION A/D CONVERTER - A successive approximation A/D conversion circuit for simultaneously sampling N channels of analog signals and for A/D converting the sampled analog signals, includes: N capacitive main DACs; a resistive sub DAC; N comparators; and a successive approximation control circuit, wherein the successive approximation control circuit determines high-order bit values of A/D conversion results of the N channels of analog signals by controlling the N capacitive main DACs and the N comparators, and determines low-order bit values of the A/D conversion results of the N channels of analog signals by controlling the resistive sub DAC and the N comparators. | 07-29-2010 |
| 20100184240 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a plasma CVD method where, while a high-frequency bias electric power is applied toward the semiconductor substrate, a plasma-generating high frequency electric power is applied to first deposition gas containing oxygen and silicon compound gas. In the method, a condition by which moisture content in the capacitor protecting insulating film becomes less than that in the first insulating film is adopted as a film deposition condition for the capacitor protecting insulating film. | 07-22-2010 |
| 20100180053 | DIRECT MEMORY ACCESS CONTROLLER - A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section. | 07-15-2010 |
| 20100178744 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O - An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film. | 07-15-2010 |
| 20100173491 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of forming an insulating layer on an conductive layer; forming a first mask layer and a second mask layer on the insulating layer; forming a resist layer on the second mask layer; patterning the resist layer; patterning the second mask layer by using the resist layer as a mask; etching the first mask layer halfway through its thickness by using the resist layer and the second mask layer as a mask; removing the resist layer; etching a remaining portion of the first mask layer using the second mask layer as a mask; forming an interconnect groove by etching the insulating layer using the first mask layer as a mask; and forming an electrically conductive material into the interconnect groove, thereby forming an interconnect layer connected to the conductive layer. | 07-08-2010 |
| 20100172413 | VIDEO DECODER AND DIGITAL BROADCAST TRANSRECEIVER - A video decoder includes a storage unit that stores therein vector data; and a video generating unit that, when an input stream is abnormal, generates based on data before the input stream became abnormal and the vector data stored in the storage unit, an image that is an image displayed using the data before the input stream became abnormal and to which motion has been added. | 07-08-2010 |
| 20100172267 | System and Method for Cooperative Data Transfer - A method for cooperative data transfer includes establishing a primary wireless connection with a primary access station. The primary wireless connection uses a primary synchronization channel that is transmitted during a first frame of a super frame. The super frame comprises a plurality of frames. The method also includes detecting a secondary synchronization channel generated by an alternate access station during a subsequent frame of the super frame. The method further includes determining whether the detected secondary synchronization channel has a signal strength greater than a threshold signal strength. The method additionally includes receiving permission to begin a cooperative data transfer operation with both the primary access station and the alternate access station. | 07-08-2010 |
| 20100169889 | MULTI-CORE SYSTEM - A multi-core system includes: a first core that writes first data by execution of a first program, wherein the first core gives write completion notice after completion of the writing; a second core that refers to the written first data by execution of a second program; and a scheduler that instructs the second core to start the execution of the second program before the execution of the first program is completed when the scheduler is given the write completion notice from the first core by the execution of the first program. | 07-01-2010 |
| 20100169851 | SUPPORT METHOD AND DESIGN SUPPORT APPARATUS - A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step. | 07-01-2010 |
| 20100169607 | RECONFIGURABLE CIRCUIT, ITS DESIGN METHOD, AND DESIGN APPARATUS - A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration. | 07-01-2010 |
| 20100169532 | SYSTEM LSI HAVING PLURAL BUSES - A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories. | 07-01-2010 |
| 20100169068 | SIMULATION PROGRAM AND SIMULATION APPARATUS - A simulation program stored in a computer readable recording medium to execute a simulation of first and second simulation objects is provided. The simulation program includes a storage that stores one of an initial state, a read waiting state and a write waiting state for a channel used for data transfer between the first and second simulation objects; a receiver that receives a read request from the first simulation object to the second simulation object through the channel; a judgment unit which, upon reception of the read request, judges whether a state corresponding to the channel is the read waiting state; a transmitter which transmits data corresponding to the channel stored in a storage area to the first simulation object when judging to be the read waiting state; and a changer that changes the state to the initial state based on the data transmission. | 07-01-2010 |
| 20100167475 | SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF - A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator. | 07-01-2010 |
| 20100164565 | SEMICONDUCTOR START CONTROL DEVICE, METHOD, AND SYSTEM - A semiconductor device provided which includes: an external power supply detection circuit which detects that an external power supply is turned on and outputs a first detection signal; an internal power supply voltage generation circuit which generates an internal power supply voltage based on the external power supply; a reference voltage generation circuit which generates a first reference voltage in response to the first detection signal; a reference voltage detection circuit which detects that the first reference voltage reaches a given level and outputs a second detection signal; a bias voltage generation circuit which, in response to the second detection signal, generates a bias voltage based on a second reference voltage dependent on the first reference voltage; and a power supply voltage detection circuit which, in response to the second detection signal, compares the bias voltage with a third reference voltage and outputs a start signal. | 07-01-2010 |
| 20100164119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film. | 07-01-2010 |
| 20100164067 | CAPACITOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor element including a first comb-shaped interconnection formed over a substrate and including a first comb tooth, a second comb-shaped interconnection formed over the substrate and including a second comb tooth opposed to the first comb tooth, and a first electrode and a second electrode opposed to each other with opposed surfaces of the first electrode and the second electrode intersecting a longitudinal direction of the first comb tooth and the second comb tooth, a first dielectric layer formed between the first electrode and the second electrode, the first electrode being connected to the first comb tooth, and the second electrode being connected to the second comb tooth. | 07-01-2010 |
| 20100162198 | Exposure data generation method and device, exposure data verification method and device and storage medium - Exposure verification is applied to exposure data indicating a pattern to be exposed by a charged particle beam. If an error point is extracted from the exposure data by the exposure verification, the values of coefficients are modified and exposure data is regenerated taking into consideration the coefficients whose values have been modified. Thus, exposure data is re-generated by changing each of the coefficient values within its appropriate range. | 06-24-2010 |
| 20100161989 | COMMUNICATION APPARATUS, DATA COMMUNICATION METHOD, AND NETWORK SYSTEM - A communication apparatus includes a storage part configured to store a first key generated according to authentication with a transmission source, identification information of the transmission source, and first information remaining unchanged regardless of the initialization of a coupling status and corresponding to the transmission source, with the first key, the identification information and the first information mapped to each other, an acquisition part configured to acquire a public key from the transmission source holding the identification information responsive to the first information stored on the storage part if the identification information of the transmission source has changed in response to the initialization of the coupling status, and a calculation part configured to generate an encryption key for use in encryption and decryption of data transmitted by the transmission source, based on the first key responsive to the first information, and the public key. | 06-24-2010 |
| 20100161868 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus performing data communication by transmitting a bus use request to an arbiter between a plurality of nodes coupled in a tree shape through a bus is provided. The data transfer apparatus includes a request generation circuit which generates a highest priority request indicating that a priority level for using the bus is the highest, a determination circuit which determines the priority level of the highest priority request, and a priority level setting circuit which determines the highest priority request which takes priority based on a result of the determination circuit when a plurality of highest priority requests conflicts in a node. | 06-24-2010 |
| 20100161305 | PERFORMANCE EVALUATION DEVICE, PERFORMANCE EVALUATION METHOD AND SIMULATION PROGRAM - A performance evaluation device includes: a control timing model unit for outputting a timing for inputting a control signal input/output between plural function blocks contained in a simulation model corresponding to a hardware; a control signal transfer period calculation unit for calculating a transfer period of the control signal between the plural function blocks in accordance with the timing for inputting the control signal; a data timing model unit for outputting a timing for inputting a data signal corresponding to the control signal, which is input/output between the plural function blocks; and a data signal transfer period calculation unit for calculating a transfer period of the data signal between the plural function blocks in accordance with the timing for inputting the data signal. | 06-24-2010 |
| 20100157697 | SEMICONDUCTOR DEVICE AND SYSTEM - A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode. | 06-24-2010 |
| 20100156923 | GRAPHICS DISPLAY DEVICE AND GRAPHICS DISPLAY METHOD - A graphics display device and method performing display indicating that graphics software for graphics drawing is an evaluation version including storing a display pattern indicating that the graphics software is an evaluation version, storing a parameter indicating a display method of the display pattern and displaying the display pattern based on the parameter by a cursor display hardware. | 06-24-2010 |
| 20100156503 | ELECTRONIC CIRCUIT DEVICE - An electric circuit device operable under a power supply includes: a circuit; a first switch connected between the power supply and the circuit; a capacitor tending to produce a first leakage current; a second switch connected between the power supply and the capacitor, the second switch producing a second leakage current when it is cut off, the second leakage current being less than the first leakage current; and a switch controller for turning on the second switch while both the first switch and the second switch are turned off, and after a first time passes for turning on the first switch. | 06-24-2010 |
| 20100156190 | CURRENT PRODUCING CIRCUIT, CURRENT PRODUCING METHOD, AND ELECTRONIC DEVICE - A current producing circuit includes a first current source that applies a first current, the first current being changed at a first rate with respect to a temperature, a second current source that applies a second current, the second current being changed at a second rate with respect to the temperature, the second rate being different from the first rate, a third current source that applies a third current, the third current being changed at a third rate with respect to the temperature, a first differential output unit that supplies a first differential current based on a difference between the first current and the second current, and a computing unit that adds or subtracts the first differential current to or from the third current. | 06-24-2010 |
| 20100155941 | SEMICONDUCTOR DEVICE - A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads. | 06-24-2010 |
| 20100153602 | COMPUTER SYSTEM AND ABNORMALITY DETECTION CIRCUIT - A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module. | 06-17-2010 |
| 20100151654 | NITRIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD, CAPACITOR FABRICATION METHOD AND NITRIDE FILM FORMING APPARATUS - The nitride film forming method comprises the first step of loading a semiconductor substrate | 06-17-2010 |
| 20100146196 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 06-10-2010 |
| 20100146171 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 06-10-2010 |
| 20100144104 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of origin patterns ( | 06-10-2010 |
| 20100144064 | SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR - An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure. | 06-10-2010 |
| 20100142306 | SEMICONDUCTOR MEMORY, SEMICONDUCTOR DEVICE, AND SYSTEM - A semiconductor memory includes: a voltage supply circuit which supplies a first voltage to a word line when an internal circuit is in a standby state, and supplies a second voltage higher than the first voltage to the word line when the internal circuit is in an active state; and a control circuit changes a drive capacity of the voltage supply circuit when changing from the standby state to the active state and the second voltage is supplied to the word line. | 06-10-2010 |
| 20100142250 | SEMICONDUCTOR MEMORY AND SYSTEM - A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines when one of the access control circuits is used, and swaps the connections between a pair of data terminals and a pair of data lines when the other one of the access control circuits is used. Accordingly, it is possible to give a data signal at the same logic level to bit lines with different logics from each other. Stress can be given between a contact arranged between a pair of the access control circuits and bit lines adjacent to both sides of the contact. Consequently, designing of a test pattern can be simplified, and test efficiency can be improved. | 06-10-2010 |
| 20100141218 | CHARGING CIRCUIT - A charging circuit that prevents a system abnormality caused by removal of a battery. The charging circuit includes a constant voltage charge controller which detects charge voltage and performs a constant voltage charging operation. A constant current charge controller detects charge current and performs a constant current charging operation. A controller controls the constant voltage charge controller to perform the constant voltage charging operation during a period from when the charge voltage reaches a fully charged voltage to when the charge current decreases to a charge completion current. The controller suspends charging the battery when the constant voltage charging operation is being performed and detects whether or not the battery is coupled to the charging circuit based on the charge voltage during the charging suspension. | 06-10-2010 |
| 20100138934 | INFORMATION PROCESSOR - An information processor for controlling a storage device for storing content information, includes: a controller for receiving content information from the exterior and storing the content information in the storage device; and a generator for generating unique information that is unique to combination of the content information and the information processor through an operation of identification information of the content information and the information processor; wherein when the controller receives content information, the controller checks whether the content information includes information matching with the unique information and upon confirmation of both the information allows the content information to be stored in the storage device. | 06-03-2010 |
| 20100138707 | PROCESSOR AND METHOD FOR CONTROLLING STORAGE-DEVICE TEST UNIT - A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred. | 06-03-2010 |
| 20100138672 | RAID CONTROLLER, STORAGE CONTROL DEVICE, AND STORAGE CONTROL METHOD - A RAID controller selecting a plurality of storages forming RAID includes a data input part having a plurality of data input terminals; a control signal input part having a control signal input terminal to which a control signal related to path setting is inputted; a data output part having a plurality of data output terminals; and a path selection part connecting a data input terminal selected from among the plurality of data input terminals with a data output terminal selected from among the plurality of data output terminals based on the control signal when the control signal is inputted to the control signal input terminal. | 06-03-2010 |
| 20100138019 | METHOD OF PERFORMING OPTICAL PROXIMITY EFFECT CORRECTIONS TO PHOTOMASK PATTERN - A method of performing an optical proximity effect correction to a first photomask pattern for a wiring of a semiconductor device for use in combination with a second photomask pattern for a via, the wiring including an end portion coupled to the via, the method being performed by a computer including a memory storing layout data of the first photomask pattern and the second photomask pattern, including extracting a pattern of layout data of the first photomask pattern for the wiring corresponding to the end portion of the wiring and layout data of the second photomask pattern for the via. | 06-03-2010 |
| 20100136758 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction. | 06-03-2010 |
| 20100135399 | METHOD AND SYSTEM FOR OBTAINING MOTION VECTORS AND BOUNDARY STRENGTHS OF AN IMAGE - A method and a system for obtaining motion vectors and boundary strengths of an image are disclosed. The method comprises the steps of: S | 06-03-2010 |
| 20100134084 | OUTPUT VOLTAGE CONTROLLER, ELECTRONIC DEVICE, AND OUTPUT VOLTAGE CONTROL METHOD - An output voltage controller includes a first controller which controls current supply to a inductor based on an output voltage, and a second controller which controls current supply to the inductor by controlling a period when an input end to which an input voltage is inputted, the inductor, and an output end from which the output voltage is outputted are coupled based on the input voltage. | 06-03-2010 |
| 20100134081 | DC-DC CONVERTER - A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage is determined by the output voltage plus said phase compensation component. | 06-03-2010 |
| 20100133659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP - A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film. | 06-03-2010 |
| 20100133449 | ION IMPLANTATION APPARATUS, SUBSTRATE CLAMPING MECHANISM, AND ION IMPLANTATION METHOD - Provided is an ion implantation apparatus including a disk which rotates about a first axis, a pad which is rotatable about a second axis on the disk, and on which a substrate is placed with a holder attached to a circumference of the substrate, the holder including a weight, fixing pins which are each fixedly provided on a portion on the disk around the pad, a sliding piece which slides, by its own centrifugal force, on the disk with a rotational movement of the disk and thereby clamps the holder in cooperation with the fixing pins, and an ion beam generator which irradiates the substrate with ion beams. | 06-03-2010 |
| 20100130004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided. | 05-27-2010 |
| 20100129971 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region. | 05-27-2010 |
| 20100128539 | SEMICONDUCTOR MEMORY - A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal. | 05-27-2010 |
| 20100128535 | SEMICONDUCTOR MEMORY AND METHOD AND SYSTEM FOR ACTUATING SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line. | 05-27-2010 |
| 20100128515 | SEMICONDUCTOR MEMORY - A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin. | 05-27-2010 |
| 20100128119 | DEFECT REVIEW APPARATUS AND METHOD FOR WAFER - A defect review apparatus includes a storage device which stores data about a defect of an inspection target object; a first imaging device which captures an image located in a position on a surface of the inspection target object, the position being specified by information regarding the position of the inspection target object which has been input; and a control device which controls the first imaging device. The storage device stores: first defect detection data including a defect number as which the defect of the inspection target object detected by a first defect detection process is labeled, and information regarding the position of the defect; and second defect data including a defect number as which the defect of the inspection target object detected by a second defect detection process is labeled, and information regarding its position. | 05-27-2010 |
| 20100127678 | CONTROL CIRCUIT FOR DC-DC CONVERTER, CONTROL METHOD FOR DC-DC CONVERTER, AND ELECTRONIC DEVICE - A control circuit for a DC-DC converter includes a controller configured to control, based on a feedback voltage, a first switch provided between an inductor and a reference potential and a second switch provided between a coupling node of the first switch and the inductor and an output terminal, a third switch provided between the second switch and the output terminal and turned off when an overcurrent flows in a coupling path between the second switch and the output terminal, and a selector configured to select a voltage of a first position which is located on a side of the second switch in the coupling path as the feedback voltage when the third switch is turned off, or a voltage of a second position which is located on a side of the output terminal in the coupling path as the feedback voltage when the third switch is turned on. | 05-27-2010 |
| 20100125821 | Design support method - A method for a design support is provided. The method includes a computer that executes processes of detecting a combination of vias comprising a target via and a neighboring via-; calculating a distance between the combination of the target via and the neighboring via, replacing a shape of the target via and a shape of at least one of the neighboring via with a shape of an exposure pattern of the via, searching the adjacent wiring arranged within the distance between the vias or less from a position of the target via after the process of replacing, and converting the position of the neighboring via to which the process of replacing is applied to the position searched by the process of searching and storing the position in the database; and outputting the layout data converted by the process of converting. | 05-20-2010 |
| 20100123728 | MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM - A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit. | 05-20-2010 |
| 20100123490 | CONTROL CIRCUITRY - Control circuitry, comprising: first control means operable to generate a first control signal, the first control signal being indicative of a relationship between an output signal and a first reference signal, and to generate said output signal in dependence upon said first control signal, the first control means being configured to tend to maintain a first desired relationship between the output signal and the first reference signal in response to said first control signal; and second control means configured to influence operation of said first control means in response to said first control signal by way of a second control signal so as to tend to maintain a second desired relationship between said first control signal and a second reference signal. | 05-20-2010 |
| 20100123487 | DIVIDER CIRCUITRY - Divider circuitry for a phase-locked loop frequency synthesizer, the divider circuitry comprising
| 05-20-2010 |
| 20100123482 | PHASE DETECTOR CIRCUITRY - Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising
| 05-20-2010 |
| 20100123252 | LAYOUT DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region. | 05-20-2010 |
| 20100117084 | METHOD FOR SORTING AND ACQUIRING SEMICONDUCTOR ELEMENT, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map. | 05-13-2010 |
| 20100111295 | SWAP CIRCUIT FOR COMMON KEY BLOCK CIPHER AND ENCRYPTION/DECRYPTION CIRCUIT INCLUDING THE SAME - An encryption/decryption circuit includes a swap circuit for outputting each of text data and initialization vector data which are input from an input terminal to either a first or second output terminal in accordance with one of modes of operation, an encryption/decryption processing unit to which one of the text data and the initialization vector data are input from the first output terminal and which performs encryption processing and decryption processing on the data, and an exclusive OR processing unit to which another one of the initialization vector data and the text data are input from the second output terminal and which performs an exclusive OR operation on the data. | 05-06-2010 |
| 20100110818 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation. | 05-06-2010 |
| 20100110810 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals, and a refresh-target selecting circuit configured to successively select all the primary word lines and all the one or more redundant word lines one by one in response to the respective pulses of the refresh timing signal, wherein a refresh operation is performed with respect to the word lines that are successively selected by the refresh-target selecting circuit. | 05-06-2010 |
| 20100110809 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM WITH REDUNDANT ELEMENT - A semiconductor memory device includes a memory cell array, a redundant element, an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal, a decoder circuit configured to select the redundant element in response to an externally applied address that matches the redundancy address selected by the address specifying circuit, and a test mode setting circuit configured to change the switchover signal in response to an externally applied input, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses. | 05-06-2010 |
| 20100109082 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask. | 05-06-2010 |
| 20100106876 | MULTIPROCESSOR SYSTEM CONFIGURED AS SYSTEM LSI - A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state. | 04-29-2010 |
| 20100105184 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess. | 04-29-2010 |
| 20100105180 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING IMPROVED PUNCH-THROUGH RESISTANCE AND PRODUCTION METHOD THEREOF, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A LOW-VOLTAGE TRANSISTOR AND HIGH-VOLTAGE TRANSISTOR - An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well. | 04-29-2010 |
| 20100105173 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE PROVIDED WITH FLIP-CHIP MOUNTED SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor device by mounting a semiconductor element on a circuit board, the semiconductor element having a first electrode made of a first material on a semiconductor substrate, the circuit board having a second electrode made of a second material on an insulating substrate, the method includes
| 04-29-2010 |
| 20100105152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrO | 04-29-2010 |
| 20100102864 | TRANSMISSION CIRCUIT - A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors. | 04-29-2010 |
| 20100102863 | DELAY CLOCK GENERATOR - A delay clock generator includes a plurality of delay element arrays arranged in parallel; a feed side transfer line and a return side transfer line provided in each of the delay elements which make up the delay element arrays, and that transfer a clock signal in a feed direction and a return direction; a selector selecting a first transfer route that couples the feed side transfer lines to each other along the preceding and succeeding delay elements and a third transfer route that couples the return side transfer lines to each other along the preceding and succeeding delay elements, and a second transfer route that couples the feed side transfer lines and the return side transfer lines of each of the delay elements; and a decoder causing the selector to select the second transfer route for one of the delay elements in the delay element array. | 04-29-2010 |
| 20100102392 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEGRATED CIRCUIT DEVICE INCLUDING ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied. | 04-29-2010 |
| 20100102365 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material. a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall. | 04-29-2010 |
| 20100097502 | IMAGE PROCESSING APPARATUS, IMAGE CAPTURING APPARATUS, AND IMAGE DISTORTION CORRECTION METHOD - An image processing apparatus for correcting image distortion includes a storage which stores before-correction coordinates in a coordinate system of a before-correction image, corresponding to each pixel in a coordinate system of a corrected image; a coordinate output section which reads from the storage and outputs the before-correction coordinates corresponding to coordinates input to select each pixel of the corrected image; a pixel data output section which outputs the data of the before-correction image, corresponding to the before-correction coordinates, as the data of the pixel of the corrected image, corresponding to the before-correction coordinates; and a pixel data calculator which calculates, when the before-correction coordinates include a value after the decimal point, a weighted average based on the data of a plurality of pixels close to the before-correction coordinates in the before-correction image to output the weighted average as the data of the pixel of the corrected image. | 04-22-2010 |
| 20100097109 | RESET CIRCUIT AND SYSTEM HAVING RESET CIRCUIT - In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on. | 04-22-2010 |
| 20100097102 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit. | 04-22-2010 |
| 20100096684 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A semiconductor device includes non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. The semiconductor device has memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate ( | 04-22-2010 |
| 20100093163 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed. | 04-15-2010 |
| 20100091594 | SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on. | 04-15-2010 |
| 20100090705 | LSI TEST APPARATUS, LSI TEST METHOD, AND COMPUTER PRODUCT - An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit. | 04-15-2010 |
| 20100090673 | POWER SUPPLY APPARATUS AND POWER SUPPLY METHOD - A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor. | 04-15-2010 |
| 20100087014 | HEAT TREATMENT APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example. | 04-08-2010 |
| 20100086205 | NOISE FILTER - A noise removal circuit in an image signal includes a boundary determination unit configured to determine a position of a light-dark boundary on the basis of, or as a function of, a pixel value of a plurality of surrounding pixels, and a selection filter configured to perform filtering in a range of the plurality of surrounding pixels which belong to a range which does not cross a boundary determined by the boundary determination unit. | 04-08-2010 |
| 20100085370 | DISPLAY CONTROL DEVICE TO DISPLAY IMAGE DATA - In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data. | 04-08-2010 |
| 20100085070 | CARRIER TRAY FOR USE WITH PROBER - A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray includes a lowermost tray and an uppermost tray interposing therebetween an intermediate tray. The lowermost and uppermost trays and are each of a circular shape having a diameter D | 04-08-2010 |
| 20100082914 | RECORDING MEDIUM, DRIVE DEVICE, AND MOUNTING METHOD - A recording medium coupled to a drive device includes a management information storage area and a master boot record. Management information used for a mounting process of the recording medium by the drive device is stored in the management information storage area and a starting location and an area size of a drive area is stored in the master boot record. | 04-01-2010 |
| 20100081269 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING ELECTRODE FOR EXTERNAL CONNECTION - A method for manufacturing semiconductor device which includes forming a first metal film over an electrode pad disposed on a substrate, forming a second metal film on the first metal film, forming a first oxide film on a surface of the first metal film and a second oxide film on a surface of the second metal film by oxidizing the surfaces of the first metal film and the second metal film, removing the first oxide film, and melting the second metal film after removing the first oxide film. | 04-01-2010 |
| 20100080073 | SEMICONDUCTOR MEMORY - A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy program circuit, second defect position information indicating a position of a second defective regular memory cell being programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell. | 04-01-2010 |
| 20100080066 | MEMORY, MEMORY OPERATING METHOD, AND MEMORY SYSTEM - A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed. | 04-01-2010 |
| 20100079634 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor includes a pixel array, and an analog to digital converter for converting a voltage signal read from the pixel array from analog to digital form, wherein the analog to digital converter includes a counter counting a first clock signal for a period depending on a voltage value of the voltage signal, and wherein a least significant bit of a count value of the counter is determined based on an exclusive OR of outputs of two 1-bit counters operating at a frequency of the first clock signal. | 04-01-2010 |
| 20100079470 | SEMICONDUCTOR DEVICE, GRAPHICS CONTROLLER, AND INFORMATION PROCESSING METHOD - A semiconductor device includes a data acquisition unit which acquires first graphic data including a first drawing position in a drawing region, and acquires second graphic data including a second drawing position different from the first drawing position in the drawing region located later than the first graphic data, a detector which detects positions in a first direction in the drawing region of the first drawing position and the second drawing position, and a controller which causes drawing information at the first drawing position and drawing information at the second drawing position to be continuously stored in a memory when the positions of the first drawing position and the second drawing position in the first direction are similar. | 04-01-2010 |
| 20100079172 | DIFFERENTIAL OUTPUT CIRCUIT - A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other and a control circuit, wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and when the control signal has a second value, the control circuit supplies no current to the PMOS transistors and selectively turns on one of the NMOS transistors, thereby controlling the output driving circuits to output a second pair of differential signals. | 04-01-2010 |
| 20100079123 | OUTPUT-VOLTAGE CONTROL DEVICE, OUTPUT-VOLTAGE CONTROL METHOD, AND ELECTRONIC APPARATUS - An output-voltage control device includes a comparator which generates a comparison result after a given time passes from first timing of a first periodic signal, the comparison result being obtained by comparing a difference between an output voltage and a reference voltage with the first periodic signal, a first signal generator which generates a timing control signal which is at a first level before the given time passes from the first timing and which changes from the first level to a second level in a period in which the comparator outputs the comparison result after the given time passes, and a second signal generator which generates a control signal for controlling the output voltage in accordance with the comparison result and the timing control signal. | 04-01-2010 |
| 20100078762 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film. | 04-01-2010 |
| 20100078729 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode. | 04-01-2010 |
| 20100077388 | PROFILING METHOD, SYSTEM, AND RECORDING MEDIUM HAVING A PROFILING PROGRAM - A profiling method executed by a computer and system including generating a source code by adding a call instruction for a profile acquisition function to a source program of an application, generating an execution form of a profiling target program by linking a library of profile acquisition functions to the source code, executing the profiling target program in an operating system of a target system, calling a profile acquisition driver by executing the call instruction of the profile acquisition function via the library of the profile acquisition functions, and acquiring sampling information on an execution status of the profiling target program based on an interrupt occurrence by the profile acquisition driver. | 03-25-2010 |
| 20100077383 | SIMULATION METHOD AND STORAGE MEDIUM FOR STORING PROGRAM - A method for debugging software on a computer includes performing a simulation in which a signal undesired during normal operation is added to a signal value when the signal value is input to a plurality of external terminals included in hardware that executes the software and includes a processor and at least one input and output device, and judging whether or not a factor determining the signal value corresponding to the external terminal requested to display the signal value is the input from the outside to the hardware by checking whether or not the signal undesired during the normal operation is added. | 03-25-2010 |
| 20100072522 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process. | 03-25-2010 |
| 20100068829 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 03-18-2010 |
| 20100066339 | SEMICONDUCTOR DEVICE AND SYSTEM - A semiconductor device is provides which includes: a first boost circuit that generates a first boost voltage by boosting an external voltage and supplies the first boost voltage to an internal circuit; and a first circuit that supplies the external voltage to an output of the first boost circuit when power is turned on and supplies the first boost voltage to the output of the first boost circuit when the external voltage reaches a given voltage. | 03-18-2010 |
| 20100065947 | METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE - A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. | 03-18-2010 |
| 20100059828 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device formed by the steps of: forming a dummy electrode | 03-11-2010 |
| 20100057962 | ARBITRATION DEVICE, ARBITRATION METHOD, AND ELECTRONIC APPARATUS - An arbitration device and method including validating a second signal after a first signal is selected for a given number of times when the first signal and the second signal conflict, where the first signal has a first priority based on a priority order corresponding to a plurality of processes and the second signal has a second priority lower than the first priority. | 03-04-2010 |
| 20100055805 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first film made of a first metal to an upper portion of a substrate, forming a second film made of an amorphous metal oxide or an microcrystalline metal oxide on the first film, subjecting the second film to a heat treatment, subjecting the second film after the heat treatment to a reduction treatment, forming a third film made of a ferroelectric material on the second film, and forming a fourth film made of a second metal on the third film. | 03-04-2010 |
| 20100054052 | SEMICONDUCTOR MEMORY - A semiconductor memory is provided which includes a word line coupled to a transistor of a memory cell; a word driver configured to activate the word line; a first resistance portion configured to couple the word line to a low-level voltage line in accordance with an activation of the word line and to decouple the coupling after a first period in an activation period of the word line elapses; a second resistance portion configured to couple the word line to a high-level voltage line in a second period in the activation period; and a third resistance portion configured to couple the word line to the low-level voltage line in the second period, a resistance of the third resistance portion being higher than a resistance of the first resistance portion, wherein a high-level voltage of the word line in the second period is lower than that of the high-level voltage line. | 03-04-2010 |
| 20100052212 | METHOD OF RESIN SEALING ELECTRONIC PART - A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus. | 03-04-2010 |
| 20100047978 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE - A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers. | 02-25-2010 |
| 20100047931 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When adopting a stack-type capacitor structure for a ferroelectric capacitor structure ( | 02-25-2010 |
| 20100045560 | ANTENNA - An antenna includes a substrate made of a dielectric material, a first different dielectric constant region having a dielectric constant different from a dielectric constant of said substrate provided in said substrate, and a first antenna element provided on a front surface of said substrate. | 02-25-2010 |
| 20100040107 | TESTING DEVICE AND TESTING METHOD OF SEMICONDUCTOR DEVICES - A testing device of semiconductor devices includes a temperature detector detecting temperatures of semiconductor devices, and a temperature control unit controlling the temperatures of the semiconductor devices based on a detected temperature, in which the temperature control unit includes thermal heads cooling or heating the semiconductor devices, solution pipes through which solutions set to different temperatures flow, and a channel switching part switching whether or not to make the solution flow through the thermal head, and when a test is conducted, the solution flown through the thermal head is switched according to heating amount of the semiconductor device. | 02-18-2010 |
| 20100039851 | SEMICONDUCTOR MEMORY - A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented. | 02-18-2010 |
| 20100038792 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire. | 02-18-2010 |
| 20100038748 | ELECTRIC FUSE CIRCUIT AND ELECTRONIC COMPONENT - An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first transistor and a second transistor, which are connected in series between the capacitor and the write circuit. | 02-18-2010 |
| 20100038560 | LASER CLEANING APPARATUS AND LASER CLEANING METHOD - A probe cleaning apparatus includes a cleaning-conditions database. The probe cleaning apparatus removes contamination from a probe by irradiating the probe by a laser beam, refers to the cleaning-conditions database based on information about the probe, such as material and shape, and controls properties of the laser beam, such as output intensity, pulse interval, wavelength, and pulse width, so that the probe cleaning apparatus removes the contamination from the probe without damaging the probe by heat. | 02-18-2010 |
| 20100035523 | SEMICONDUCTOR DEVICE FABRICATING METHOD, AND SEMICONDUCTOR FABRICATING DEVICE - A method for fabricating a semiconductor device includes: supporting a semiconductor substrate formed with a polishing target film by a polishing head; and polishing the polishing target film while restricting movement in a radial direction of the semiconductor substrate by a retainer formed on the polishing head with a tilted surface formed on an inner peripheral section of the retainer, wherein when the polishing target film is polished, an outer peripheral surface of the semiconductor substrate comes into contact with the tilted surface formed on the inner peripheral section of the retainer. | 02-11-2010 |
| 20100034045 | SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups and the L data is read from the designated position, where L is an integer and L| 02-11-2010 | |
| 20100031208 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device includes density verification of layout data of the semiconductor device at a macro level. The method includes disposing virtual patterns each including a predetermined step width on a circumference of a verification frame; and moving the verification frame outside which the virtual patterns are disposed sequentially by the predetermined step width and performing the density verification of the layout data of the semiconductor device. | 02-04-2010 |
| 20100027721 | Method and System for Implementing a Multiple-Input Multiple-Output (MIMO) Decoder Scheme - The teachings of the present disclosure relate to a method for receiving “N” data streams (wherein “N” is a number greater than one) from “N” endpoints. Each of the data streams are received from a different respective endpoint. The method also includes decoding the “N” data streams by generating a decoding signal input comprising the “N” data streams and then iteratively repeating the following steps “N”−1 times: determine a most reliable stream; decode the most reliable stream using linear multiple-input and multiple-output (MIMO) decoding; output the decoded most reliable stream; estimate a signal estimate based on the most reliable stream and modulation information associated with the most reliable stream; and generate a residual signal that comprises the remaining data streams less the signal estimate. Upon the residual signal comprising two data streams, the method includes updating the decoding signal input to be the residual signal. Upon the residual signal comprising a single received stream, the method includes decoding the residual signal using a maximum likelihood decoder. | 02-04-2010 |
| 20100027319 | RESISTANCE CHANGE ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR MEMORY - A resistance change element including a first electrode; a second electrode; and an oxide film, including an oxide of the first electrode, formed at sides of the first electrode and sandwiched between the first electrode and the second electrode in a plurality of regions, wherein at least one of the regions includes a resistance part whose resistance value changes in accordance with a voltage applied to the first and second electrodes. | 02-04-2010 |
| 20100026335 | LEAK CURRENT DETECTION CIRCUIT, BODY BIAS CONTROL CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING METHOD - A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents. | 02-04-2010 |
| 20100025859 | METHOD FOR DESIGNING SEMICONDUCTOR DEVICE, PROGRAM THEREFOR, AND SEMICONDUCTOR DEVICE - A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling a first power supply line and the second power supply line and the contact resistance value. | 02-04-2010 |
| 20100025817 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern. | 02-04-2010 |
| 20100025744 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region. | 02-04-2010 |
| 20100023656 | Data transfer method - There is provided a data transfer method in an IEEE1394 system including a band request node and a transfer band management node. The method includes generating, at the band request node, a transfer request that can detect a data amount of transfer data and transmitting the transfer request from the band request node to the transfer band management node, determining, by the transfer band management node, whether a transfer band requested by the transfer request is ensured or not, notifying, from the transfer band management node, the band request node of the determination result, and transferring data from the band request node according to the determination result. | 01-28-2010 |
| 20100022080 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes nitridizing a silicon substrate with ammonia while heating the silicon substrate, then heating the silicon substrate in an atmosphere containing nitrogen and oxygen to form a gate insulating film including a silicon-based insulating film containing nitrogen and oxygen, then annealing the silicon substrate in an oxygen atmosphere, and forming a gate electrode on the gate insulating film. | 01-28-2010 |
