| FREESCALE SEMICONDUCTOR, INC Patent applications |
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| 20160143012 | CARRIER AGGREGATION CONTROLLER AND METHOD - A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. The selector is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal. | 05-19-2016 |
| 20160142458 | METHOD AND DEVICE FOR DATA STREAMING IN A MOBILE COMMUNICATION SYSTEM - Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface. | 05-19-2016 |
| 20160142175 | ADAPTIVE CYCLIC CHANNEL CODING FOR ORTHOGONAL FREQUENCY DIVISION MULTIPLEXED (OFDM) SYSTEMS - A method and apparatus for an orthogonal frequency division multiplexed (OFDM) communication system for communication in the presence of cyclostationary noise is provided. A receiver receives from a medium a channel measurement packet of a communication channel. The channel measurement packet has a measured transmission characteristic. The measured transmission characteristic of the received channel measurement packet is compared to a defined transmission characteristic to provide a comparison. A modulation coding scheme (MCS) map referenced to a phase of a cyclostationary noise period of the medium is generated based upon the comparison. The MCS map is sent to a transmitter via the medium. Signals including packets that have been mapped to subcarriers based on the MCS map are received from the medium. Subcarriers of the signals received from the medium are demapped using the MCS map referenced to the phase of the cyclostationary noise period of the medium. | 05-19-2016 |
| 20160142025 | INTEGRATED MATCHING CIRCUIT FOR A HIGH FREQUENCY AMPLIFIER - An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The integrated matching circuit comprises an inductive element, and a capacitive element arranged in a series arrangement with the inductive element. The series arrangement has a first terminal end connected to the input terminal or to the output terminal and a second terminal end connected to the reference terminal. The first terminal end and the second terminal end are arranged at a same lateral side of the integrated matching circuit to obtain a geometry with the first terminal end adjacent to the input terminal or to the output terminal and the second terminal end adjacent to the reference terminal. | 05-19-2016 |
| 20160142015 | HIGH FREQUENCY AMPLIFIER - A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die. | 05-19-2016 |
| 20160139944 | Method and Apparatus for Combined Hardware/Software VM Migration - A method and apparatus are provided for migrating one or more hardware devices ( | 05-19-2016 |
| 20160139174 | TRIMMING CIRCUIT FOR A SENSOR AND TRIMMING METHOD - An on-board trimming circuit suitable for trimming an accelerometer provides offset trim and gain trim modules for determining correct trim codes for subsequent programming into the trimming circuit. The correct trim codes may be determined by comparing sensor outputs which have been adjusted by successive trim codes, with a reference voltage in a comparator until the comparator toggles or by using a successive approximation technique. The reference voltage is supplied form a tap of a feedback resistance divider circuit which forms a part of an on-board voltage reference generator which may be used to provide a full scale reference for an analog to digital converter which converts a sensor output voltage into a digital signal. Using these reference voltages significantly lessens the impact of any offsets inherent in the voltage reference generator on the trimming process. | 05-19-2016 |
| 20160138968 | APPARATUS AND METHOD FOR CHECKING THE INTEGRITY OF VISUAL DISPLAY INFORMATION - The invention provides an apparatus and method for checking the integrity of visual display information and has particular application to checking images displayed in an automotive vehicle, such images containing safety critical information. The image intensity is checked only to an extent commensurate with a human being able to interpret its correct meaning. Hence, images which are defective in some way yet still recognisable by the human eye are not classified as failures. In one embodiment, a part of the image containing safety critical information is segmented into smaller areas and the luminance of pixels in each segmented area is compared with a threshold brightness level and a threshold darkness level. A histogram for each area is generated and compared with a reference. | 05-19-2016 |
| 20160135223 | EFFICIENT SCHEDULING IN ASYNCHRONOUS CONTENTION-BASED SYSTEM - In an operation scheduler adapted to schedule in an asynchronous contention-based system a first FIFO queue is adapted to store one trigger message or one operation request. A message router is coupled to the first FIFO queue and is adapted to route instructions to a second FIFO queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorise execution of the suspended operation. An arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended. | 05-12-2016 |
| 20160134521 | DEVICE AND METHOD FOR PROCESSING IN A MOBILE COMMUNICATION SYSTEM - A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited. | 05-12-2016 |
| 20160134279 | METHOD AND CIRCUIT FOR RECHARGING A BOOTSTRAP CAPACITOR USING A TRANSFER CAPACITOR - A circuit including and a method utilizing an improved bootstrap topology provide power to a high side (HS) driver for high efficiency applications. The improved bootstrap topology includes a transfer capacitor to store charge and to recharge a bootstrap capacitor, which provides power to the HS driver. The improved bootstrap topology also includes a resistor connected to the transfer capacitor to charge the transfer capacitor from a voltage source and to isolate the transfer capacitor from high voltage pulses. | 05-12-2016 |
| 20160134273 | EMITTER FOLLOWER BUFFER WITH REVERSE-BIAS PROTECTION - The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor. | 05-12-2016 |
| 20160132628 | METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT - A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. | 05-12-2016 |
| 20160132374 | DETECTION OF DATA CORRUPTION IN A DATA PROCESSING DEVICE - A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature. | 05-12-2016 |
| 20160132332 | SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION - A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register. | 05-12-2016 |
| 20160132093 | METHOD AND APPARATUS FOR CONTROLLING AN OPERATING MODE OF A PROCESSING MODULE - A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period. | 05-12-2016 |
| 20160132070 | OSCILLATOR CIRCUIT AND METHOD OF GENERATING A CLOCK SIGNAL - An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator. | 05-12-2016 |
| 20160131713 | SYSTEMS AND METHODS FOR SWITCH HEALTH DETERMINATION - The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch. | 05-12-2016 |
| 20160128040 | METHOD AND DEVICE FOR INTERFACING IN A MOBILE COMMUNICATION SYSTEM - Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided. | 05-05-2016 |
| 20160126963 | PHASE DETECTOR AND PHASE-LOCKED LOOP - A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1≦F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2≦F1 and the level “0” in response to F2>F1. | 05-05-2016 |
| 20160126841 | BUCK CONVERTER AND METHOD OF OPERATING A BUCK CONVERTER - A buck converter has an output node and a ground node, wherein a load is connected between the output node and the ground node and is arranged to drive an output current I_out through the output node, generating an output voltage V_out. A current control unit arranged to control the output current I_out in dependence on a control voltage V_ctl provided at a control node; and a voltage control unit arranged to provide the control voltage V_ctl. The voltage control unit comprises: an integrator unit arranged to control the control voltage V_ctl in dependence on a time integral of a difference between the output voltage and the reference voltage; at least one of an overshoot detector arranged to detect an overshoot of the output voltage V_out, and an undershoot detector arranged to detect an undershoot of the output voltage V_out. | 05-05-2016 |
| 20160126206 | THICK-SILVER LAYER INTERFACE - A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer. | 05-05-2016 |
| 20160124904 | PROCESSING DEVICE AND METHOD FOR PERFORMING A ROUND OF A FAST FOURIER TRANSFORM - A data processing device and a method for performing a round of an N point Fast Fourier Transform are described. The round comprises computing N output operands on the basis of N input operands by applying a set of N/P radix-P butterflies to the N input operands, wherein P is greater or equal two and the input operands are representable as N/(M*P)̂ | 05-05-2016 |
| 20160124853 | DIAGNOSTIC APPARATUS, CONTROL UNIT, INTEGRATED CIRCUIT, VEHICLE AND METHOD OF RECORDING DIAGNOSTIC DATA - A diagnostic apparatus comprises a diagnostic data buffer constituting a volatile memory, and a non-volatile memory capable of receiving data from the buffer. A data buffer controller is also provided and is operably coupled to the buffer and has an event alert input and a data channel monitoring input for receiving diagnostic data. The buffer receives, when the state of a buffer status memory indicates that the buffer is in an unprotected state, at least part of the diagnostic data received by the controller via the data channel monitoring input to the buffer and the controller sets the state of the buffer status memory to indicate the protected state in response to receipt of an event alert received via the event alert input. A controller monitors the buffer status memory and copies a portion of the buffer to the non-volatile memory in response to the buffer status memory being set to be indicative of the protected state. | 05-05-2016 |
| 20160124800 | MICROCONTROLLER UNIT AND METHOD OF OPERATING A MICROCONTROLLER UNIT - A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed. | 05-05-2016 |
| 20160119887 | SIGNAL PROCESSING METHOD FOR UPLINK IN SMALL CELL BASE STATION - A base station and method of synchronizing with a user equipment (UE) in a cell of the base station. The base station signals to the UE an indication relating to a subset of preambles chosen for synchronization with the cell from a set of preambles derivable from one or more given root sequences. The subset of preambles is chosen to provide an increased cell radius compared to the cell radius achievable if the specified full set of preambles for random access procedures was generated from the given root sequences using a given cyclic shift value. | 04-28-2016 |
| 20160118705 | PACKAGED INTEGRATED CIRCUIT WAVEGUIDE INTERFACE AND METHODS THEREOF - The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization. | 04-28-2016 |
| 20160118469 | INTEGRATED CIRCUIT DEVICES WITH COUNTER-DOPED CONDUCTIVE GATES - Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices. | 04-28-2016 |
| 20160118373 | MULTIPLE DIE LEAD FRAME PACKAGING - First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame. | 04-28-2016 |
| 20160118313 | FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure. | 04-28-2016 |
| 20160117255 | DEVICE HAVING A CACHE MEMORY - A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror. | 04-28-2016 |
| 20160117183 | SYSTEM-ON-CHIP DEVICE, METHOD OF PERIPHERAL ACCESS AND INTEGRATED CIRCUIT - A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. The conflict detection unit is arranged to detect, when in use, an access conflict caused by more than one virtual machine image attempting to access initially the shareable resource. The conflict detection unit is arranged to refer, when in use, the access conflict in response to detection thereof to the virtual machine monitoring unit for resolving of the access conflict, thereby handling the access conflict before the virtual machine monitoring unit. | 04-28-2016 |
| 20160117007 | VISUAL DISPLAY CONTENT SOURCE IDENTIFIER AND METHOD - The invention provides an apparatus and method which allows identification of the system which provided images for each pixel of a touchscreen display which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. Colour keying may be used to superimpose one image onto another. The invention finds particular application in the automotive field where images produced by an infotainment system may be merged with those produced by a mobile phone onto the in-vehicle display screen. | 04-28-2016 |
| 20160112012 | RADIO FREQUENCY POWER AMPLIFIER - A radio frequency power amplifier comprises an input and output terminals, a main and peak amplifier stages, and an output power combiner for combining a main output signal and a peak output signal into an output signal. The output power combiner comprises a first combiner terminal electrically coupled to a main output terminal, a second combiner terminal electrically coupled to a peak output terminal, a first transition structure extending from the first combiner terminal in a first direction to a first end, a second transition structure extending from the second combiner terminal in the first direction to a second end, a first electrical conductor arranged between the first and the second ends, and a second electrical conductor arranged between the second combiner terminal and the output terminal. The first electrical conductor extends in a second direction perpendicular to the first direction. The second electrical conductor extends in the first direction. | 04-21-2016 |
| 20160111403 | LEADFRAME-BASED SYSTEM-IN-PACKAGES HAVING SIDEWALL-MOUNTED SURFACE MOUNT DEVICES AND METHODS FOR THE PRODUCTION THEREOF - Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall. | 04-21-2016 |
| 20160110275 | METHOD AND APPARATUS FOR OFFLOADING FUNCTIONAL DATA FROM AN INTERCONNECT COMPONENT - An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data. | 04-21-2016 |
| 20160109559 | INTEGRATED CIRCUIT, RADAR DEVICE AND METHOD OF CALIBRATING A RECEIVER - An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver. | 04-21-2016 |
| 20160109510 | TEST BOARD SUPPORT PLATFORM FOR SUPPORTING A TEST BOARD - The invention provides a test board support platform for supporting a test board during tests, the platform comprising a heat conductive interface arranged to contact a bottom side of the test board at a first side of the heat conductive interface. The support platform also comprises a thermal conditioner coupled to a second side of the heat conductive interface, the second side being opposite the first side. By using this test board support platform a test board can be supported and thermally controlled in a way so that a DUT positioned on the test board can be probed from above, while the temperature is controlled from below. | 04-21-2016 |
| 20160105876 | COMMUNICATIONS ENABLED APPARATUS WITH A MULTI-MAC MANAGER AND A METHOD OF OPERATING THEREOF - The present application relates to a networking device with multi-MAC manager and a method of operating thereof. The multi-MAC manager receiving a request issued in the context of a medium access control, MAC, instance, determines the MAC, instance, to which the request relates and determines whether the PHY part is available for allocation or already allocated to the MAC instance. If the PHY is available, at least the PHY part of the communications interface is allocated to the MAC instance and the received request is passed to the PHY part for further processing thereat. At least the allocated PHY part is released once a service requested by the received request is completed. | 04-14-2016 |
| 20160105861 | ANTENNA DELAY BUFFERING IN TELECOMMUNICATION RECEIVERS - A telecommunication receiver is arranged for receiving related data originating from multiple antennas, which data have different times of arrival due to, for example, different delays. The receiver comprises an input buffer for buffering data, a transform unit for Fourier transforming the data received from the input buffer into transformed data, and an output buffer for buffering the transformed data received from the transform unit. The input buffer is arranged for passing each set of data items to the transform unit when the relevant data item has been received in the input buffer, while the transform unit is arranged for removing redundant parts of the data. In addition, the output buffer is arranged for synchronizing the transformed data. Thus the buffering for delay compensation is carried out in the output buffer. | 04-14-2016 |
| 20160105200 | APPARATUS AND METHOD FOR PROCESSING TRACE DATA STREAMS - An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronisation logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronisation event; and decoding logic configured to use the synchronisation event to synchronise decoding of the received first data stream to produce the trace data. | 04-14-2016 |
| 20160104380 | CYCLING SAFETY SYSTEM - A safety system comprising:
| 04-14-2016 |
| 20160103940 | METHOD OF GENERATING A TARGET LAYOUT ON THE BASIS OF A SOURCE LAYOUT - Generating a target layout of an integrated circuit includes providing a source layout comprising one or more source pcells having one or more shapes; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit; for each shape of each source pcell, determining a corresponding target shape having a contour composed of edges with defined lengths, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, determining a corresponding edge of the corresponding target shape; for each edge, defining an edge length constraint for constraining the edge to have the length of the edge of the corresponding target shape; applying a legalization procedure to the source layout based on the connectivity constraints, the target design constraints, and the edge length constraints. | 04-14-2016 |
| 20160103858 | DATA MANAGEMENT SYSTEM COMPRISING A TRIE DATA STRUCTURE, INTEGRATED CIRCUITS AND METHODS THEREFOR - A data management system comprises a trie data structure. The trie data structure comprises a plurality of interconnected nodes wherein at least a portion of said plurality of interconnected nodes is configured as parent nodes and child nodes, wherein at least one child node comprises an identifier of its parent node. | 04-14-2016 |
| 20160103769 | PROCESSING DEVICE AND METHOD THEREOF - A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. | 04-14-2016 |
| 20160103686 | APPARATUS AND METHOD FOR DETERMINING A CUMULATIVE SIZE OF TRACE MESSAGES GENERATED BY A PLURALITY OF INSTRUCTIONS - An apparatus comprising: at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform static code analysis of a plurality of instructions comprising, for each instruction: determining whether a trace message is generated by the instruction; determining whether a size of the trace message generated by the instruction is dependent on a context; determining a size of the trace message generated by the instruction; and updating the context; and to perform determining a cumulative size of trace messages generated by the plurality of instructions. | 04-14-2016 |
| 20160103206 | RADAR DEVICE UTILIZING PHASE SHIFT - A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift. | 04-14-2016 |
| 20160102979 | SYSTEM COMPRISING A MECHANICAL RESONATOR AND METHOD THEREFOR - A system comprises a mechanical resonator; an analog circuit operably coupled to the mechanical resonator; the analog circuit arranged to receive a mechanical resonator measurement signal and to output a mechanical resonator actuation signal to the mechanical resonator; and a digital actuator operably coupled to the analog circuit and configured to provide a frequency sweep of signals to the analog circuit that induces movement of the mechanical resonator. | 04-14-2016 |
| 20160100367 | POWER MANAGEMENT MODULE AND METHOD THEREFOR - A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component. | 04-07-2016 |
| 20160099709 | CURRENT MODE LOGIC CIRCUIT FOR HIGH SPEED INPUT/OUTPUT APPLICATIONS - A CML latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage. | 04-07-2016 |
| 20160099656 | NON-ISOLATED AC-DC CONVERSION POWER SUPPLY - A non-isolated capacitive AC-DC conversion power supply includes a current limiting input module that receives AC input power and has an output capacitor that supplies DC power. Charge storage stages have charge storage capacitors, a rectifier supplying rectified current from the input module to charge the charge storage capacitors and the output capacitor during a first part-cycle of the AC input power. The charge storage stages also include current amplifiers and unidirectional elements that conduct discharge current from the charge storage capacitors to charge the output capacitor during a second part-cycle of the AC input power. Ground of the DC output can be connected to the live AC input. | 04-07-2016 |
| 20160099349 | SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION - A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices. | 04-07-2016 |
| 20160099341 | HIGH BREAKDOWN VOLTAGE LDMOS DEVICE - A multi-region ( | 04-07-2016 |
| 20160099212 | Through Package Circuit in Fan-Out Wafer Level Package - A method and apparatus are provided for manufacturing a packaged electronic device ( | 04-07-2016 |
| 20160099199 | ELECTRONIC DEVICES WITH SOLDERABLE DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES - An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer. | 04-07-2016 |
| 20160098506 | SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION - A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell. | 04-07-2016 |
| 20160098326 | METHOD AND APPARATUS FOR ENABLING TEMPORAL ALIGNMENT OF DEBUG INFORMATION - A signal processing device includes at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further includes at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value. | 04-07-2016 |
| 20160098313 | WATCHDOG METHOD AND DEVICE - Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred. | 04-07-2016 |
| 20160098050 | VOLTAGE REGULATOR, APPLICATION-SPECIFIC INTEGRATED CIRCUIT AND METHOD FOR PROVIDING A LOAD WITH A REGULATED VOLTAGE - A voltage regulator for digital loads combines a closed loop regulation circuit with an open loop topology. A transistor and a bank of transistors share the same voltage source VDD and gate control current. Each of the bank of transistors is sized to match different current load requirements and one or more may be switched in or out as appropriate when the digital load transitions from one operating mode to another. The regulator has good DC load regulation and unconditional stability regardless of output capacitance. | 04-07-2016 |
| 20160098047 | VOLTAGE MONITORING SYSTEM - An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal. | 04-07-2016 |
| 20160094171 | METHOD AND APPARATUS FOR REGULATING AN OUTPUT VOLTAGE OF AN ALTERNATOR - A method of regulating an output voltage of an alternator. The method comprises measuring first and second external contacts of the alternator regulator module operably coupled to first and second output contacts of the alternator respectively during an ON state of an excitation cycle for the alternator, measuring a second voltage across the first and second external contacts of the alternator regulator module during an OFF state of an excitation cycle for the alternator, deriving an average voltage value of the first and second voltage measurements, and deriving an offset value based at least partly on the derived average voltage value. | 03-31-2016 |
| 20160093587 | FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF - A packaged RF device is provided that can provide improved performance and flexibility though the use of flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. | 03-31-2016 |
| 20160093549 | INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT - A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information. | 03-31-2016 |
| 20160093533 | SUBSTRATE FOR ALTERNATIVE SEMICONDUCTOR DIE CONFIGURATIONS - A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies. | 03-31-2016 |
| 20160092329 | Final Result Checking For System With Pre-Verified Cores - Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core. | 03-31-2016 |
| 20160092323 | MULTI-PARTITION NETWORKING DEVICE AND METHOD THEREFOR - A multi-partition networking device comprising a primary partition running on a first set of hardware resources and a secondary partition running on a further set of hardware resources. The multi-partition networking device is arranged to operate in a first operating state, whereby the first set of hardware resources are in an active state and the primary partition is arranged to process network traffic, and the further set of hardware resources are in a standby state. The multi-partition networking device is further arranged to transition to a second operating state upon detection of a suspicious condition within the primary partition, whereby the further set of hardware resources are transitioned from a standby state to an active state, and to transition to a third operating state upon detection of a failure condition within the primary partition, whereby processing of network traffic is transferred to the secondary partition. | 03-31-2016 |
| 20160092320 | ELECTRONIC FAULT DETECTION UNIT - An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit. | 03-31-2016 |
| 20160091908 | SENSED SWITCH CURRENT CONTROL - A circuit includes an evaluation node through which current flows from a voltage source node to a sensed switch when the sensed switch is closed. First and second control switches are disposed between the voltage source node and the evaluation node to switch between first and second current paths for the current. The current passes through the first control switch when flowing along the first current path. The second control switch is coupled to a control terminal of the first control switch to deactivate the first control switch and allow the current to flow through the second current path. Multiple passive circuit elements are configured to establish first and second current levels for the current. The passive circuit elements are disposed between the voltage source node and the evaluation node in a circuit arrangement in which no current path to ground is present when the sensed switch is open. | 03-31-2016 |
| 20160087741 | EQUALIZER FOR JOINT-EQUALIZATION - An equalizer for equalizing a composite signal originating from a given number of simultaneous data streams able to be received over a communication channel, on a given number of antennas, at one or more radio units, in a wireless communication system. The equalizer performs matrix operations when the number of receiving antennas associated with the composite signal is lower than the number of antennas supported by the equalizer. The channel matrix and the signal and interference covariance matrices are manipulated. The antenna dimension is increased, padding is then added and the transmitted signal vector is finally determined based on the altered matrices. | 03-24-2016 |
| 20160087737 | A NETWORK RECEIVER FOR A NETWORK USING DISTRIBUTED CLOCK SYNCHRONIZATION AND A METHOD OF SAMPLING A SIGNAL RECEIVED FROM THE NETWORK - A network receiver receives from a network an input signal which is sampled by a data sampler of the network receiver at sampling moments. Sampling moments have a relative position in time within a period of time of a single bit. The network receiver further includes a clock bit comparator and a sampling moment adaptor. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The sampling moment adaptor adapts the relative position of the sampling moment in dependence of a result of the comparison of the lengths to reduce a difference between the lengths. | 03-24-2016 |
| 20160087333 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package has a first side and an opposite second side. The integrated circuit package comprises: a stack of layers comprising at least a first and second electrically isolating layers, a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package, a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, and a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material. The first integrated antenna structure is arranged between the first and second electrically isolating layers and is surrounded by the electrically conductive vias which are electrically connected to respective first metal patches arranged on the dielectric material at the second side. | 03-24-2016 |
| 20160086930 | FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR - Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed. | 03-24-2016 |
| 20160086880 | COPPER WIRE THROUGH SILICON VIA CONNECTION - A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material. | 03-24-2016 |
| 20160085687 | MEMORY MANAGEMENT COMPONENT - A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme. | 03-24-2016 |
| 20160085618 | ELECTRONIC DEVICE HAVING A RUNTIME INTEGRITY CHECKER - An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. A mask unit is provided for processing a mask for defining the locations to be checked based on bits in the mask. The hardware enables selective monitoring of non contiguous storage locations or data areas. | 03-24-2016 |
| 20160085545 | METHOD AND APPARATUS FOR IMPLEMENTING INTER-COMPONENT FUNCTION CALLS - A method of implementing inter-component function calls. The method comprises generating a lower tier indirection data structure comprising an entry indicating a location in memory of a function within a first software component, a higher tier indirection data structure comprising an entry indicating a location in memory of the lower tier indirection data structure, and a configuration data structure comprising an entry defining an active version of the first software component. The method further comprises implementing executable computer program code for an inter-component function call by referencing entries within the configuration data structure, the higher tier indirection data structure and the lower tier indirection data structure. | 03-24-2016 |
| 20160085479 | INTERFACE SYSTEM AND METHOD - An interface system has a first media access controller having a first MAC buffer for storing at least one first-type frame in a first frame format according to a first communication protocol. A time synchronization module is arranged to, upon detecting the start of the first-type frame, determine a first timestamp from a master clock signal and latch the first timestamp into a first timestamp register. A processor is arranged to: retrieve the first timestamp from the first timestamp register, and transfer a first-type frame between the first MAC buffer and a first local memory in a block-wise manner as a plurality of blocks. The processor is arranged to process the plurality of blocks of the first-type frame using the first timestamp as retrieved from the first timestamp register. | 03-24-2016 |
| 20160085279 | METHOD FOR RESETTING AN ELECTRONIC DEVICE HAVING INDEPENDENT DEVICE DOMAINS - A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit. | 03-24-2016 |
| 20160085261 | LOW VOLTAGE SWING BUFFER - An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing. | 03-24-2016 |
| 20160084913 | CELL MONITORING APPARATUS, BATTERY MONITORING APPARATUS, INTEGRATED CIRCUIT AND METHOD OF MONITORING A RECHARGEABLE CELL - A cell monitoring apparatus includes a processor and memory arranged to execute code representing a linear time-invariant state transition model and a non-linear observation model are provided to model a rechargeable cell using at least a non-linear open circuit voltage, an internal resistance, a time-invariant distortion voltage across a reactive component block, and a distortion current component constituting an error of measurement of current flowing through the reactive component block. An estimator unit performs extended Kalman filtering in respect of the state transition model and the observation model using the input state data in order to generate output state data. The processor is arranged to evaluate a criterion associated with at least part of the output state data and to generate a control signal in response to evaluation of the criterion. | 03-24-2016 |
| 20160084903 | INTEGRATED CIRCUIT AND METHOD OF OPERATING AN INTEGRATED CIRCUIT - An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit. | 03-24-2016 |
| 20160084872 | THREE-AXIS MICROELECTROMECHANICAL SYSTEMS DEVICES - The embodiments described herein provide microelectromechanical systems (MEMS) devices, such as three-axis MEMS devices that can sense acceleration in three orthogonal axes (e.g., x-axis, y-axis, and z-axis). In general, the embodiments described can provide decoupling between the sense motions of all three axes from each other. This decoupling is facilitated by the use of an inner frame, and an outer frame, and the use of rotative spring elements combined with translatory spring elements that have asymmetric stiffness. Specifically, the translatory spring elements facilitate translatory motion in two directions (e.g., the x-direction and y-direction) and have an asymmetric stiffness configured to compensate for an asymmetric mass used to sense in the third direction (e.g., the z-direction). | 03-24-2016 |
| 20160084722 | Differential Pressure Sensor Assembly - A differential pressure sensor assembly includes a transducer having a first sensing surface and a second sensing surface. The second sensing surface is contained in a cavity. An Integrated Circuit (IC) is hermetically coupled to the transducer. The IC has a first aperture aligned to the cavity. A lead frame is coupled to the IC. The lead frame has a second aperture aligned to the first aperture of the IC. A package encapsulates the transducer, the IC and the lead frame. The package has a third aperture exposed to the first sensing surface. The package includes a molding compound providing a hermetic seal between the third aperture of the package and the first aperture of the IC. The molding compound is separated from the transducer by an encroachment distance. | 03-24-2016 |
| 20160080140 | A NETWORK RECEIVER FOR A NETWORK USING DISTRIBUTED CLOCK SYNCHRONIZATION AND A METHOD OF ADJUSTING A FREQUENCY OF AN INTERNAL CLOCK OF THE NETWORK RECEIVER - A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths. | 03-17-2016 |
| 20160078253 | DEVICE HAVING A SECURITY MODULE - A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data. | 03-17-2016 |
| 20160077984 | MECHANISM FOR MANAGING ACCESS TO AT LEAST ONE SHARED INTEGRATED PERIPHERAL OF A PROCESSING UNIT AND A METHOD OF OPERATING THEREOF - The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied. | 03-17-2016 |
| 20160077904 | INTEGRATED CIRCUIT AND METHOD OF DETECTING A DATA INTEGRITY ERROR - An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output. | 03-17-2016 |
| 20160077542 | METHOD AND APPARATUS FOR CONTROL OF A SWITCHED CURRENT CIRCUIT - An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an ON-state, waiting an amount of waiting an amount of time t | 03-17-2016 |
| 20160077537 | A LOW DROP-OUT VOLTAGE REGULATOR AND A METHOD OF PROVIDING A REGULATED VOLTAGE - A low drop-out voltage regulator, an integrated circuit, a sensor and a method of providing a regulated voltage are provided. The low drop-out voltage regulator comprises a regulated voltage driver for providing the regulated voltage in response to a control voltage, a feedback-loop circuit for generating the control signal such that the regulated voltage driving circuit provides the regulated voltage, and a pull-up circuit for pulling up the regulated voltage to a supply voltage when a difference between the supply voltage and the control voltage is smaller than a predetermined threshold value. In the feedback-loop circuit a first feedback voltage or a second feedback voltage is generated, respectively, on basis of a first ratio and a second ratio between the feedback voltage and the regulated voltage. The second feedback voltage is generated instead of the first feedback voltage when the regulated voltage is pulled-up to the supply voltage. | 03-17-2016 |
| 20160077533 | VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT - An integrated circuit (IC) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. A resistor-ladder network receives the feedback signal and generates a sense voltage signal. A voltage regulator compares the sense voltage signal with a reference voltage signal and regulates the first supply voltage signal at a first voltage level. | 03-17-2016 |
| 20160077196 | RECEIVER SYSTEM AND METHOD FOR RECEIVER TESTING - A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device. | 03-17-2016 |
| 20160075553 | Sensor Protective Coating - A microelectromechanical system (MEMS) sensor device includes a substrate, a support structure supported by the substrate, a membrane supported by the support structure and spaced from the substrate, and a polymer layer covering the membrane. | 03-17-2016 |
| 20160072488 | VOLTAGE-DRIVER CIRCUIT WITH DYNAMIC SLEW RATE CONTROL - A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal. | 03-10-2016 |
| 20160072484 | LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH - A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage. | 03-10-2016 |
| 20160072413 | METHOD, COMPUTER PROGRAM PRODUCT AND CONTROLLER FOR STARTING-UP A SWITCHED RELUCTANCE MOTOR, AND ELECTRICAL APPARATUS IMPLEMENTING SAME - A method of starting-up a switched reluctance, SR, motor is provided. The method comprises simultaneously energizing a plurality of phases at a first time point with respective phase voltages that are substantially the same, until the motor rotor is stabilized in alignment with either one of the plurality of phases; simultaneously de-energizing the plurality of phases at a second time point that follows the first time point; monitoring a decrease of respective phase currents in the plurality of phases from a third time point that follows the second time point by a first predetermined time interval; determining a phase of alignment of the rotor using evaluation of the decrease of the phase currents following simultaneous de-energizing of the plurality of phases; and, initiating rotation of the rotor from the determined phase of alignment of the rotor. | 03-10-2016 |
| 20160071943 | METHOD TO FORM SELF-ALIGNED HIGH DENSITY NANOCRYSTALS - Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided. | 03-10-2016 |
| 20160071789 | MOLDED INTERPOSER FOR PACKAGED SEMICONDUCTOR DEVICE - A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers. | 03-10-2016 |
| 20160071495 | DISPLAY CONTROLLER DEVICE HAVING A DEBUG INTERFACE - A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image. | 03-10-2016 |
| 20160071228 | DATA LOGGING SYSTEM AND METHOD - A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution. | 03-10-2016 |
| 20160070934 | MEMORY CONTROLLER - A memory controller used to verify authenticity of data stored in a first memory unit. The memory controller includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value which is representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value in order to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating in case the data written to the first memory unit is not authentic. | 03-10-2016 |
| 20160070846 | SYSTEM FOR TESTING IC DESIGN - A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design. | 03-10-2016 |
| 20160070669 | MULTI-PORT TRANSMITTER DEVICE FOR TRANSMITTING AT LEAST PARTLY REDUNDANT DATA, AN ASSOCIATED CONTROL SYSTEM, AN ASSOCIATED METHOD AND AN ASSOCIATED COMPUTER PROGRAM PRODUCT - A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block. | 03-10-2016 |
| 20160070666 | METHOD OF CONTROLLING DIRECT MEMORY ACCESS OF A PERIPHERAL MEMORY OF A PERIPHERAL BY A MASTER, AN ASSOCIATED CIRCUITRY, AN ASSOCIATED DEVICE AND AN ASSOCIATED COMPUTER PROGRAM PRODUCT - A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described. | 03-10-2016 |
| 20160070619 | METHOD AND APPARATUS FOR CONFIGURING I/O CELLS OF A SIGNAL PROCESSING IC DEVICE INTO A SAFE STATE - A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal. | 03-10-2016 |
| 20160069986 | RADAR DEVICE AND METHOD OF OPERATING A RADAR DEVICE - A radar device includes a RF signal source, two or more antenna interface units, a feed network, and a control unit. The RF signal source is arranged to provide a RF signal; each of the antenna interface units includes an antenna port and one of the following an amplifier and a mixer; the feed network includes two or more buffers, each buffer has an active and an inactive state; the control unit is arranged to generate or receive a selection signal which specifies none, one, or more of the antenna interface units as active antenna interface units and the remaining antenna interface units as inactive antenna interface units; the control unit is arranged to activate and deactivate the buffers in dependence on the selection signal so as to feed the RF signal to the none, one, or more active antenna interface units and not to the inactive antenna interface units. | 03-10-2016 |
| 20160069763 | SEMICONDUCTOR SENSOR DEVICE FORMED WITH GEL SHEET - A method for assembling a pressure sensor device uses a pressure-sensitive gel material that is applied to an active region of a pressure-sensing integrated circuit (IC) die. A molding compound is dispensed over the pressure-sensitive gel material to encapsulate the gel material. A portion of the molding compound is then removed to expose the gel material to an ambient environment outside of the packaged semiconductor device. | 03-10-2016 |
| 20160066052 | TELEVISION RECEIVER, TELEVISION SET, AND METHOD FOR UPDATING PROGRAM SCHEDULE INFORMATION IN A TELEVISION RECEIVER - A television receiver, comprising a television signal input, a tuner, a frame buffer, a control input, a pattern recognition unit, and an electronic program guide unit. In operation, the television signal input receives a television signal. The tuner generates consecutive frames of a selected television channel on the basis of the television signal and is connected to a screen so as to drive the screen to display the frames consecutively. The frame buffer buffers the frames. The control input receives a scheduling request triggered by a user. The pattern recognition unit determines one or more program schedule values in response to the scheduling request, by performing an automatic pattern recognition analysis of one or more frames residing in the frame buffer. The electronic program guide unit provides program schedule information and updates the program schedule | 03-03-2016 |
| 20160065295 | ANTENNA-DIVERSITY RECEIVER AND METHOD OF OPERATING AN ANTENNA-DIVERSITY RECEIVER AND A TRANSMITTER IN A FREQUENCY-HOPPING COMMUNICATION SYSTEM - An antenna-diversity receiver receives data units from a transmitter in a frequency-hopping communication system. The frequency-hopping system has a channel set comprising of multiple channels, each having its own frequency range. The channel set comprises a set of multiple advertising channels and a set of multiple data channels. The receiver comprises an antenna set of multiple antennas. | 03-03-2016 |
| 20160065250 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUITS AND METHOD FOR LINEARIZING A TRANSMITTER SIGNAL - A wireless communication unit comprising a transmitter comprises: a linearization circuit arranged to receive and digitally distort an input signal; a radio frequency power amplifier operably coupled to the linearization circuit and arranged to amplify a radio frequency representation of the digitally distorted input signal; a feedback path arranged to feed back a portion of the amplified digitally distorted output of the received input signal to the linearization circuit; a bypass circuit comprising a plurality of energy storage elements operably coupled between an output of the radio frequency power amplifier and ground; and a first connector arranged to provide a representation of at least one electrical memory effect of at least one of the plurality of energy storage elements to the linearization circuit, wherein the linearization circuit is arranged to use the representation of the at least one electrical memory effect when digitally distorting the input signal. | 03-03-2016 |
| 20160065225 | METHOD FOR RE-CENTERING A VCO, INTEGRATED CIRCUIT AND WIRELESS DEVICE - A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop. | 03-03-2016 |
| 20160065131 | INTEGRATED CIRCUIT COMPRISING A FREQUENCY DEPENDENT CIRCUIT, WIRELESS DEVICE AND METHOD OF ADJUSTING A FREQUENCY - An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit. | 03-03-2016 |
| 20160065114 | DEVICE FOR CONTROLLING A MULTI-PHASE MOTOR - An electronic device is for controlling motor drive circuits for driving a multi-phase motor in a force assisted system. Each motor drive circuit selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. A motor control circuit generates the control signals. A fault processor detects at least one fault condition causing a fault current in a first motor drive circuit. In the event of the fault condition being detected, at least one alternative control signal is generated for at least one motor drive circuit for permitting at least one compensation current to flow for reducing a faulty force due to the fault current. | 03-03-2016 |
| 20160064792 | RADIO FREQUENCY COUPLING STRUCTURE AND A METHOD OF MANUFACTURING THEREOF - A radio frequency transmission structure couples a RF signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The RF coupling structure comprises: a hole arranged through the first dielectric substrate, a first electrically conductive layer arranged on a first wall of the hole to electrically connect a first and a second signal terminals, a second electrically conductive layer arranged on a second wall of the hole opposite to the first wall to electrically connect a first and a second reference terminals. The first electrically conductive layer is separated from the second electrically conductive layer. The hole extends beyond the first wall away from the second wall. | 03-03-2016 |
| 20160064356 | SEMICONDUCTOR DEVICE PACKAGE WITH ORGANIC INTERPOSER - A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer. | 03-03-2016 |
| 20160064324 | SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME - A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor. | 03-03-2016 |
| 20160063149 | DESIGN TOOL APPARATUS, METHOD AND COMPUTER PROGRAM FOR DESIGNING AN INTEGRATED CIRCUIT - An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimiser and a circuit sensitivity calculator. The circuit sensitivity optimiser is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. The circuit simulator is configured to communicate to the circuit sensitivity calculator, a performance metrics of the circuit in response thereto. The circuit sensitivity calculator is configured to determine one sensitivity coefficient for each device of the first dynamic list in response thereto. The circuit sensitivity calculator is further configured to determine and communicate to the circuit sensitivity optimiser a variance of the performance metrics and also adapted to gradually determine whether or not to further communicate with the circuit simulator. | 03-03-2016 |
| 20160062862 | DATA PROCESSING SYSTEM WITH DEBUG CONTROL - A data processing system includes a processor configured to execute processor instructions and a memory. The memory has a data array and a checkbit array wherein each entry of the checkbit array includes a plurality of checkbits and corresponds to a storage location of the data array. The system includes error detection/correction logic configured to, during normal operation, detect an error in data access from a storage location of the data array using the plurality of checkbits in the entry corresponding to the storage location. The system further includes debug logic configured to, during debug mode, use a portion of the plurality of the checkbits in the entry corresponding to the storage location to generate a breakpoint/watchpoint request for the processor. | 03-03-2016 |
| 20160062810 | METHODS AND APPARATUS FOR DETECTING SOFTWARE INTEFERENCE - The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal. | 03-03-2016 |
| 20160062806 | METHOD AND DEVICE FOR DETECTING A RACE CONDITION AND A COMPUTER PROGRAM PRODUCT - A method is provided for detecting a race condition of a parallel task when accessing a shared resource in a multi-core processing system. The method requires that a core requires only a read access to the data set of another core thereby ensuring better decoupling of the tasks. In an initialisation phase, initial values of global variables are assigned, in an activation phase, each core determines if the other core has written new values to the variables and if so, detects a race condition. Initial values are restored for each variable in a deactivation phase. | 03-03-2016 |
| 20160062797 | SYSTEM AND METHOD FOR DYNAMICALLY MANAGED TASK SWITCH LOOKAHEAD - A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI. | 03-03-2016 |
| 20160062751 | METHOD AND APPARATUS FOR OPTIMISING COMPUTER PROGRAM CODE - A method and apparatus for optimising computer program code. The method comprises identifying at least one set of candidate instructions within the computer program code, each candidate instruction comprising an instruction for writing a constant value to memory and the at least one set comprising a plurality of candidate instructions. The method further comprises computing an aggregate constant value for the at least one set of candidate instructions, and replacing the at least one set of candidate instructions with at least one instruction for writing the aggregate constant value to memory. | 03-03-2016 |
| 20160062656 | Command Set Extension for Non-Volatile Memory - A method and apparatus are provided for generating an adjusted internal electrical parameter for accessing a NAND Flash memory array based on an adjustment control parameter conveyed by a memory access instruction, where the memory access instruction is compliant with an Open NAND Flash Interface (ONFI) protocol to include a two command cycle sequence to specify a command for accessing the NAND Flash memory with the adjusted internal electrical parameter. | 03-03-2016 |
| 20160062331 | APPARATUS AND METHOD FOR VALIDATING THE INTEGRITY OF CONTROL SIGNALS IN TIMING DOMAIN - The present application relates to a signal integrity module for validating one or more control signals in time domain and a method thereof. The one or more control signals are received via a signal input from at least one control signal generating unit. A new signature is generated by a signature generating unit on the basis of a current signature and the state of the one or more control signals at a watch point. The current signature is latched into a signature register upon receiving a trigger signal. The latched signature is representative of the time course of the one or more control signals at the watch point over a monitoring period defined by the trigger signal. The latched signature is compared by a signature comparator with a pre-calculated signature to validate the integrity of the one or more control signals with respect to the time domain. | 03-03-2016 |
| 20160061898 | WETTING CURRENT DIAGNOSTICS - A method of providing wetting current diagnostics for a load control switch includes changing test switch settings of a detection circuit from an operational configuration to a testing configuration. The test switch settings specify respective states of first and second test switches of the detection circuit. The first and second test switches are connected to a node of the detection circuit through which, in the operational configuration, a wetting current for the load control switch flows. The method includes determining whether a voltage at the node becomes no longer indicative of the operational configuration as a result of the changed test switch settings, returning the test switch settings to the operational configuration, and providing a wetting current fault indication if the voltage at the node fails to return to a level indicative of the operational configuration after returning the test switch settings to the operational configuration. | 03-03-2016 |
| 20160061891 | MIXED MODE INTEGRATED CIRCUIT, METHOD OF PROVIDING A CONTROLLABLE TEST CLOCK SIGNAL TO A SUB-CIRCUITRY OF THE MIXED-MODE INTEGRATED CIRCUIT AND METHOD OF DETECTING CURRENT PATHS CAUSING VIOLATIONS OF ELECTROMAGNETIC COMPATIBILITY STANDARDS IN THE MIXED MODE INTEGRATED CIRCUIT - A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit | 03-03-2016 |
| 20160061890 | INTEGRATED CIRCUIT DEVICE AND METHOD OF PERFORMING SELF-TESTING WITHIN AN INTEGRATED CIRCUIT DEVICE - IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration. | 03-03-2016 |
| 20160061870 | ELECTRIC POWER METER - An electric power meter for measuring electric power is provided. The power meter has a frequency domain converter arranged to convert a sequence of digital voltage samples from the time domain to a frequency domain obtaining digital voltage frequency components, and to convert a sequence of digital current samples from the time domain to the frequency domain obtaining digital current frequency components. The electric power meter also has a frequency domain correction unit arranged to correct the voltage frequency components and the current frequency components by multiplying at least one frequency component of the current frequency components and the voltage frequency components with a complex correction factor using a complex multiplication unit. Electric power is computed by an energy calculation unit. | 03-03-2016 |
| 20160061867 | METHOD AND APPARATUS FOR METERING A VOLTAGE SIGNAL - A voltage metering module for metering a voltage signal at least one analogue to digital converter (ADC) component arranged to receive at an input thereof a voltage signal and to generate a digital signal representative of the received voltage signal. The at least one ADC component includes at least one sampling network controllable to sample the received voltage signal for conversion to a digital signal representative of the received voltage signal and at least one compensation network operably coupled in parallel with the sampling network and controllable to sample the received voltage signal such that an input current of the compensation network at least partially compensates for a component of an input current of the sampling network. | 03-03-2016 |
| 20160056811 | TESTABLE POWER-ON-RESET CIRCUIT - An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage. | 02-25-2016 |
| 20160056765 | FREQUENCY SELECTIVE ISOLATION CIRCUIT AND METHOD FOR SUPPRESSING PARAMETRIC OSCILLATION - In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (RLC) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. Direct current (DC) and other non-harmonically-related frequencies do not pass through the isolation circuit. Since the resistor is used to dissipate specifically the energy of the harmonic frequencies causing the odd-mode oscillation, the current density through the resistor is much lower than the current density of a typical odd-mode resistor without a harmonically tuned filter. | 02-25-2016 |
| 20160056741 | DEVICE FOR DETERMINING A POSITION OF A ROTOR OF AN ELECTRIC MOTOR - A device for determining a rotor position in a polyphase electric motor has a power control unit for applying drive voltages according to a pulse width modulation scheme so as to synchronously drive the motor. A measurement unit is arranged for measuring a voltage value on a respective phase by determining a zero-crossing interval where the phase current is around zero, disconnecting the phase from the respective drive voltage during the zero-crossing interval, and measuring the voltage value when the drive voltage of a first other phase is the supply voltage and the drive voltage of a second other phase is the zero voltage. A position unit is arranged for determining the rotor position based on the voltage value. | 02-25-2016 |
| 20160056234 | DEEP TRENCH ISOLATION STRUCTURES AND SYSTEMS AND METHODS INCLUDING THE SAME - Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures. | 02-25-2016 |
| 20160056114 | TRENCHED FARADAY SHIELDING - A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench. | 02-25-2016 |
| 20160056099 | INTEGRATED CIRCUIT WITH ON-DIE DECOUPLING CAPACITORS - A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device. | 02-25-2016 |
| 20160056094 | BALL GRID ARRAY PACKAGE WITH MORE SIGNAL ROUTING STRUCTURES - A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls. | 02-25-2016 |
| 20160054995 | SINGLE-INSTRUCTION MULTIPLE DATA PROCESSOR - In accordance with at least one embodiment, a processor system is disclosed having a SIMD processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the SIMD processor is a vector processor (VPU) having a plurality of vector Arithmetic Units (AUs) as subsidiary processing elements, and the VPU executes an instruction to transfer table information from a global memory of the VPU to a plurality of local memories accessible by each AU. The VPU also executes an instruction that results in each processing element performing a table lookup from a table stored at its local memory. In response to the instruction, this table lookup uses a portion of a lookup value to access information from the table, and uses another portion of the lookup information to calculate an interpolated resultant based upon the accessed information. | 02-25-2016 |
| 20160054746 | VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT - An integrated circuit (IC) includes a power grid having first, through fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively, a voltage regulator, a reference voltage calibration circuit, a dual-rail sense circuit, and a voltage monitor circuit. The reference voltage calibration circuit receives the first supply, first ground, second supply, and second ground voltage signals and generates a reference voltage signal based on differences between voltage levels of the first supply and ground voltage signals, and the second supply and ground voltage signals. The voltage regulator regulates the first supply voltage signal based on the reference voltage signal and the second supply voltage signal. The dual-rail sense circuit generates a sense signal based on the second supply and ground voltage signals. The voltage monitor generates a voltage monitor signal based on the sense signal that indicates a state of the IC. | 02-25-2016 |
| 20160049905 | OSCILLATOR CIRCUIT AND METHOD OF PROVIDING TEMPERATURE COMPENSATION THEREFOR - An oscillator circuit comprising at least a first component arranged to be statically calibrated to calibrate the oscillator circuit to achieve a symmetrical frequency/temperature profile for the oscillator circuit. The oscillator circuit further comprises at least one further component arranged to be dynamically calibrated to enable an oscillating frequency of the oscillator circuit to be dynamically adjusted, and at least one temperature compensation component arranged to receive at least one temperature indication for the oscillator circuit and to dynamically adjust the at least one further component based at least partly on the at least one received temperature indication. In some examples, the at least one temperature compensation component is arranged to dynamically adjust the at least one further component based on a standardized temperature compensation scheme. | 02-18-2016 |
| 20160049508 | BIDIRECTIONAL TRENCH FET WITH GATE-BASED RESURF - A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage. | 02-18-2016 |
| 20160049303 | METHOD FOR FORMING A MEMORY STRUCTURE HAVING NANOCRYSTALS - A method of forming a semiconductor structure uses a substrate. A first insulating layer is formed over the substrate. An amorphous silicon layer is formed over the first insulating layer. Heat is applied to the amorphous silicon layer to form a plurality of seed nanocrystals over the first insulating layer. Silicon is epitaxially grown on the plurality of seed nanocrystals to leave resulting nanocrystals. | 02-18-2016 |
| 20160048629 | AUTOMATIC GENERATION OF TEST LAYOUTS FOR TESTING A DESIGN RULE CHECKING TOOL - A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises N design constraints numbered 1 to N, wherein N is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. The set of test layouts includes: one or more zero-error layouts; one or more one-error layouts; and one or more two-error layouts. A zero-error layout is a layout that satisfies all of the design constraints. A one-error layout is a layout that violates exactly one of the design constraints. A two-error layout is a layout that violates exactly two of the design constraints. | 02-18-2016 |
| 20160048390 | METHOD FOR AUTOMATED MANAGING OF THE USAGE OF ALTERNATIVE CODE AND A PROCESSING SYSTEM OF OPERATING THEREOF - The present application relates to a method and a processing system for automated managing of the usage of alternative code. Code sections including original code and alternative code are retrieved from a code basis and the retrieved code is analyzed to detect an alternative code section. A condition definition associated with the identified alternative code section is further retrieved and the condition of the retrieved condition definition is evaluated. The identified alternative code section is activated in accordance with the evaluation result. | 02-18-2016 |
| 20160048155 | RESET CIRCUITRY FOR INTEGRATED CIRCUIT - An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset. | 02-18-2016 |
| 20160048147 | VOLTAGE REGULATION SUBSYSTEM - A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions. | 02-18-2016 |
| 20160043039 | SEMICONDUCTOR DEVICE WITH AN ISOLATION STRUCTURE COUPLED TO A COVER OF THE SEMICONDUCTOR DEVICE - A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically. | 02-11-2016 |
| 20160042246 | A HAAR CALCULATION SYSTEM, AN IMAGE CLASSIFICATION SYSTEM, ASSOCIATED METHODS AND ASSOCIATED COMPUTER PROGRAM PRODUCTS - A compute engine is arranged to retrieve a block of image data corresponding to a rectangular image region; calculate integral image values for all pixels of the block of image data to obtain an integral image of the block of image data; and store the integral image of the block in the one or more memories. The main processor determines which blocks of image data comprise pixels of the predefined rectangular region of the image, and defines a respective rectangular region part as the pixels of the block that belong to the predefined rectangular region of the image; calculate a HAAR feature of the rectangular region part for each block of image data that comprise pixels of the predefined rectangular region of the image; and add the HAAR features of the rectangular region parts to obtain the HAAR feature of the predefined rectangular region of the image. | 02-11-2016 |
| 20160041579 | TIMING SYNCHRONIZATION CIRCUIT FOR WIRELESS COMMUNICATION APPARATUS - A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock. | 02-11-2016 |
| 20160041571 | CURRENT GENERATOR CIRCUIT AND METHOD OF CALIBRATION THEREOF - A current generator circuit includes at least one current generation component arranged to generate an output current of the current generator circuit, at least one absolute current calibration component arranged to enable calibration of an absolute current value of the output current, and at least one temperature coefficient calibration component arranged to enable calibration of a temperature coefficient characteristic of the output current. The at least one temperature coefficient calibration component is further arranged to be in a passive state at a reference temperature. | 02-11-2016 |
| 20160037186 | METHOD AND VIDEO SYSTEM FOR FREEZE-FRAME DETECTION - A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames. | 02-04-2016 |
| 20160036463 | DATA STORAGE DEVICE AND METHOD FOR PROTECTING A DATA ITEM AGAINST UNAUTHORIZED ACCESS - A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. Upon a read access the memory control unit reads the data item and the first error-detection code; forms a second data word comprising the data item and a second key; computes a second error-detection code to the second data word; and determines a syndrome on the basis of the first error-detection code and the second error-detection code, wherein the syndrome is indicative of whether or not the first and second data words are identical. | 02-04-2016 |
| 20160035822 | High Voltage Semiconductor Devices and Methods for their Fabrication - Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described. | 02-04-2016 |
| 20160035415 | NON-VOLATILE MEMORY USING BI-DIRECTIONAL RESISTIVE ELEMENTS - A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail. | 02-04-2016 |
| 20160034398 | CACHE-COHERENT MULTIPROCESSOR SYSTEM AND A METHOD FOR DETECTING FAILURES IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM - A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system. | 02-04-2016 |
| 20160034291 | SYSTEM ON A CHIP AND METHOD FOR A CONTROLLER SUPPORTED VIRTUAL MACHINE MONITOR - A system on a chip comprising: a first communication controller; at least one second communication controller operably coupled to the first communication controller; at least one processing core operably coupled to the first communication controller and arranged to support software running on a first partition and a second partition; and a virtual machine monitor located between the first and second partitions, and the at least one processing core and arranged to support communications there between. The first communication controller is arranged to: generate or receive at least one data frame; and communicate the at least one data frame to the at least one second communication controller; such that the at least one second communication controller is capable of routing the at least one data frame to the second partition bypassing the virtual machine monitor. | 02-04-2016 |
| 20160033567 | CRYSTAL OSCILLATOR MONITORING CIRCUIT - In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated. | 02-04-2016 |
| 20160033560 | MODE-CONTROLLED VOLTAGE EXCURSION DETECTOR APPARATUS AND A METHOD OF OPERATING THEREOF - The present application relates to a mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting. | 02-04-2016 |
| 20160032852 | METHOD OF CALIBRATING A CRANK ANGLE OF A COMBUSTION ENGINE - The present application provides a calibration device for calibrating a crank angle of a calibrateable combustion engine, the calibrateable combustion engine and a method for calibrating. The calibration device is provided to determine a trigger wheel angle offset from a combustionless driving of the combustion engine in that an in-cylinder pressure profile is recorded, on the basis of which a trigger wheel angle offset is determined and stored at an offset memory of the combustion engine. The combustion engine is configured to determine a crank angle on the basis of a measured trigger wheel angle and the stored trigger wheel angle offset. | 02-04-2016 |
| 20160027992 | PACKAGE-IN-PACKAGE SEMICONDUCTOR SENSOR DEVICE - A semiconductor sensor device includes a device substrate, a micro-controller unit (MCU) die attached to the substrate, and a packaged pressure sensor having a sensor substrate and a pressure sensor die. The sensor substrate has a front side with the pressure sensor die attached to it, a back side, and an opening from the front side to the back side. A molding compound encapsulates the MCU die, the device substrate, and the packaged pressure sensor. A back side of the sensor substrate and the opening in the sensor substrate are exposed on an outer surface of the molding compound. | 01-28-2016 |
| 20160027529 | Address Fault Detection Circuit - A semiconductor memory device and method of operation are provided for a multi-bank memory array ( | 01-28-2016 |
| 20160026203 | CURRENT SOURCE, AN INTEGRATED CIRCUIT AND A METHOD - The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. Furthermore, the present invention provides an integrated circuit and a method. | 01-28-2016 |
| 20160025808 | METHOD AND SYSTEM FOR LOGIC BUILT-IN SELF-TEST - A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted. | 01-28-2016 |
| 20160021734 | SEMICONDUCTOR DEVICE WITH ACTIVE SHIELDING OF LEADS - A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad. | 01-21-2016 |
| 20160020189 | FLEXIBLE PACKAGED INTEGRATED CIRCUIT - A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device. | 01-21-2016 |
| 20160020182 | Wire Bond Mold Lock Method and Structure - A method and apparatus are described for fabricating a microchip structure ( | 01-21-2016 |
| 20160006399 | DOHERTY AMPLIFIER - A two-way Doherty amplifier for amplifying a modulated or non-modulated carrier signal, said carrier signal having a carrier frequency; wherein the Doherty amplifier comprises a first amplifier having a first amplifier output node, a second amplifier having a second amplifier output node, a combining node connected or connectable to a load, a first amplifier output line connecting the first amplifier output node to the combining node, and a second amplifier output line connecting the second amplifier output node to the combining node, and wherein the first amplifier output line has an electrical length of substantially one quarter wavelength of the carrier signal and the second amplifier output line has an electrical length of substantially one half wavelength of the carrier signal. | 01-07-2016 |
| 20160005730 | ESD Protection with Asymmetrical Bipolar-Based Device - An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device. | 01-07-2016 |
| 20160005682 | Matrix Lid Heatspreader for Flip Chip Package - A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array ( | 01-07-2016 |
| 20160004661 | USB TRANSCEIVER - A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal. | 01-07-2016 |
| 20160004654 | SYSTEM FOR MIGRATING STASH TRANSACTIONS - A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core. | 01-07-2016 |
| 20160004536 | Systems And Methods For Processing Inline Constants - Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register. | 01-07-2016 |
| 20160004292 | MICROCONTROLLER WITH MULTIPLE POWER MODES - A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode. | 01-07-2016 |
| 20160004274 | APPARATUS, A METHOD AND MACHINE READABLE INSTRUCTIONS FOR QUERYING TIMERS - An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window. | 01-07-2016 |
| 20150382316 | SEARCH METHOD AND APPARATUS FOR A COMMUNICATION SYSTEM - A method of searching of base stations in a mobile communication system has a first stage of detecting at least one slot boundary, a second stage of detecting at least one frame boundary and a scrambling code group, and a third stage of detecting a scrambling code. Multiple possible base stations are identified by determining a first threshold based on correlation values of correlating the input signal with a primary synchronization channel code. For each hit, the input signal is aligned to the corresponding slot boundary, an average correlation value is based on all correlations with secondary sequences, and a second threshold based on the average correlation value is set. Any delay and codewords that have a correlation value above the second threshold are correlated with the codes in the detected group so as to determine multiple base stations. | 12-31-2015 |
| 20150381216 | Adaptive High-Order Nonlinear Function Approximation Using Time-Domain Volterra Series to Provide Flexible High Performance Digital Pre-Distortion - A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks ( | 12-31-2015 |
| 20150381198 | APPARATUS AND METHOD FOR MONITORING ELECTRICAL CURRENT - An apparatus for sensing current of a vehicle battery employs an extended counting analogue-to-digital conversion process to a chopped and amplified voltage appearing across a low ohmic shunt resistor placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier by matching the gain to the dynamic range of the ADC permits a high dynamic signal sensing. | 12-31-2015 |
| 20150381167 | GATE DRIVE CIRCUIT AND A METHOD FOR CONTROLLING A POWER TRANSISTOR - A gate drive circuit drives a control terminal of a power transistor and comprises: a drive terminal for electrically coupling the control terminal, a first reference source, a first switch arranged between the first reference source and the control terminal, a switch control circuit and a measurement circuit. The first switch is switched-on to turn-off the power transistor. The switch control circuit switches-off the first switch during a transition period to a fully off-state. The measurement circuit outputs a control signal to the switch control circuit in response to a value of a voltage at the control terminal measured when a discharge current flowing to the drive terminal has been reduced to a predetermined threshold, for switching-on the first switch if the measured value is smaller than a threshold voltage. | 12-31-2015 |
| 20150381140 | METHOD AND APPARATUS FOR A MULTI-HARMONIC MATCHING NETWORK - A matching network and method for matching a source impedance to a load impedance is provided. A bias feed microstrip structure is coupled to a direct current (DC) voltage source and has a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of an input signal. A harmonic impedance transformation network can be configured to compensate for parasitic reactances of a precursor element. A tuned impedance element presents a short circuit impedance at the second harmonic impedance transformation network terminal for harmonic frequency components and presents a higher impedance for the fundamental frequency component. A fundamental impedance transformation network is configured to match a fundamental impedance transformation network input impedance for the fundamental frequency component to a load impedance of a load. Multiple instances of the harmonic impedance transformation network and the tuned impedance element can be provided. | 12-31-2015 |
| 20150381117 | RADIO FREQUENCY DEVICES WITH SURFACE-MOUNTABLE CAPACITORS FOR DECOUPLING AND METHODS THEREOF - An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply. | 12-31-2015 |
| 20150380513 | BIPOLAR TRANSISTOR DEVICE FABRICATION METHODS - A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions. | 12-31-2015 |
| 20150380353 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE, AND AN INTEGRATED CIRCUIT DEVICE THEREFROM - A method of fabricating an integrated circuit (IC) device includes mounting, via a first surface thereof, at least one semiconductor die on to a surface of an IC device package, mounting, via an interconnect surface thereof, at least one fuse component on to a second surface of the at least one semiconductor die, the second surface of the at least one semiconductor die having at least one terminal of the at least one active component. The at least one fuse component is mounted such that the interconnect surface of the at least one fuse component is thermally coupled to the second surface of the at least one semiconductor die and electrically coupled to the at least one terminal of the at least one active component. The at least one fuse component is electrically coupled to at least one external connection surface of the IC device package such that the at least one fuse component is electrically coupled in series between the at least one terminal of the at least one active component of the at least one semiconductor die and the at least one external connection surface of the IC device package. | 12-31-2015 |
| 20150380067 | MEMORY CONTROLLER - A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system. | 12-31-2015 |
| 20150379971 | DISPLAY PROCESSOR AND METHOD FOR DISPLAY PROCESSING - A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied. | 12-31-2015 |
| 20150379276 | SYSTEM ON A CHIP, CONTROLLER AND METHOD FOR SECURING DATA - A system on a chip for securing data is described. The system on a chip comprises: a controller arranged to: partition a data block into a plurality of segments; and determine and extract a subset of the plurality of segments to be compressed. A compressor logic circuit is arranged to receive and compress the subset of the plurality of segments. The controller is arranged to retrieve the compressed subset of the plurality of segments from the compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission. | 12-31-2015 |
| 20150379181 | Routing Standard Cell-Based Integrated Circuits - This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan. | 12-31-2015 |
| 20150379175 | IC DESIGN SYNTHESIS USING SLACK DIAGRAMS - An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design. | 12-31-2015 |
| 20150378944 | A METHOD OF AND CIRCUITRY FOR CONTROLLING ACCESS BY A MASTER TO A PERIPHERAL, A METHOD OF CONFIGURING SUCH CIRCUITRY, AND ASSOCIATED COMPUTER PROGRAM PRODUCTS - A method of controlling access by a master to a peripheral includes receiving one or more interrupt priority levels from one or more interrupt controllers associated with the peripheral, comparing the one or more interrupt priority level with respective one or more pre-established interrupt access levels to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on at least the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including one or more masters, one or more peripherals, and an access control circuitry including one or more interrupt controllers associated with the one or more peripherals. The access control circuitry is arranged to perform a method of controlling access by a master of the one or more masters to a peripheral of the one or more peripherals. | 12-31-2015 |
| 20150378730 | SYSTEM ON A CHIP WITH MANAGING PROCESSOR AND METHOD THEREFOR - A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state. | 12-31-2015 |
| 20150378385 | INTEGRATED CIRCUIT WITH INTERNAL AND EXTERNAL VOLTAGE REGULATORS - An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode. | 12-31-2015 |
| 20150377933 | INTEGRATED CIRCUIT, CURRENT SENSE CIRCUIT FOR A PULSE WIDTH MODULATION DRIVER AND METHOD THEREFOR - A current sense circuit for a PWM driver comprises: a PWM control circuit comprising: a first switching device arranged to receive a PWM signal from the PWM driver whose current is to be sensed; and a second switching device whose supply current is arranged to track the sensed current of the PWM driver. An ADC is operably coupled to the first and second switching device. The ADC comprises: a DAC arranged to provide a current sense to the second switching device that tracks the current passing through the PWM driver; a first comparator arranged to receive and compare an output current from the DAC and an output current from the first switching device; and a first successive approximation register arranged to receive an output from the comparator and provide: a first output to the ADC; and a second output that provides a representation of the sensed current. | 12-31-2015 |
| 20150375995 | MEMS Fabrication Process with Two Cavities Operating at Different Pressures - A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements ( | 12-31-2015 |
| 20150375989 | MICROELECTROMECHANICAL SYSTEMS DEVICES WITH IMPROVED LATERAL SENSITIVITY - Microelectromechanical system (MEMS) devices and methods for forming MEMS devices are provided. The MEMS devices include a substrate, an anchored structure fixedly coupled to the substrate, and a movable structure resiliently coupled to the substrate. The movable structure has an opening formed therethrough and is positioned such that the anchored structure is at least partially within the opening and is in a capacitor-forming relationship with the movable structure. The movable structure comprises a movable structure finger extending only partially across the opening. | 12-31-2015 |
| 20150373331 | PROCESSING DEVICE AND METHOD OF COMPRESSING IMAGES - The present application relates an encoder and a method of operating thereof. The encoder is configured to partition an image domain into several substructures each having one of at least one size dimension; and to define at least one geometric primitive for each substructure on the basis of geometry data. | 12-24-2015 |
| 20150372930 | APPARATUS, SYSTEM AND METHOD FOR CONTROLLING PACKET DATA FLOW - A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority. | 12-24-2015 |
| 20150372130 | POWER DEVICE TERMINATION STRUCTURES AND METHODS - Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors. | 12-24-2015 |
| 20150371711 | CONTROL GATE DRIVER FOR USE WITH SPLIT GATE MEMORY CELLS - A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate. | 12-24-2015 |
| 20150370580 | CONFIGURATION CONTROLLER FOR AND A METHOD OF CONTROLLING A CONFIGURATION OF A CIRCUITRY - A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output. | 12-24-2015 |
| 20150370568 | INTEGRATED CIRCUIT PROCESSOR AND METHOD OF OPERATING A INTEGRATED CIRCUIT PROCESSOR - A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed. | 12-24-2015 |
| 20150370535 | METHOD AND APPARATUS FOR HANDLING INCOMING DATA FRAMES - A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame. | 12-24-2015 |
| 20150370312 | ELECTRONIC MONITORING DEVICE HAVING WAKE-UP FOR DAISY CHAIN - A monitoring device has an event monitor, an uplink interface to a chain controller device, and a downlink interface to a further monitoring device, and a daisy controller for coupling the uplink to the chain downlink. The event monitor, in response to detecting an event in sleep mode, generates a wake-up signal. The daisy controller sets the electronic monitoring device to a wake-up request mode and disables the bidirectional data communication via the downlink interface, and subsequently transmits a wake-up request to the chain controller device via the uplink interface. In response to receiving a wake-up command, the daisy controller re-enables the bidirectional data communication via the downlink interface and sets the electronic monitoring device to the operational mode. Thereby a wake-up sequence is performed while the wake-up request mode avoids bus conflicts. | 12-24-2015 |
| 20150370280 | VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION - A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current. | 12-24-2015 |
