| Fairchild Semiconductor Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20150365000 | FULL BRIDGE DC/DC CONVERTER CONTROL TECHNIQUES - The present disclosure describes full bridge power supply systems and control methods. In at least one embodiment, the full bridge power supply system may be driven utilizing a two-phase continuous conduction switching mode to control the inductor current. In another embodiment, the full bridge power supply system may be driven utilizing variably-configured three-phase continuous conduction modes to control the inductor current when an input voltage is within a window value to the output voltage. In another embodiment, the full bridge power supply may be driven using a four-phase discontinuous conduction switching mode to control the inductor current when a load current is below a current lower threshold. | 12-17-2015 |
| 20150244164 | OVERCURRENT DETECTION CIRCUIT AND METHOD, LOAD SWITCH, AND PORTABLE DEVICE - The present invention provides an overcurrent detection circuit, an overcurrent detection method, a load circuit, and a portable device. The overcurrent detection circuit comprises: a first overcurrent detection sub-circuit and a second overcurrent detection sub-circuit; wherein: the first overcurrent detection sub-circuit is configured to perform overcurrent detection for a switch circuit when a voltage of an output terminal of the switch circuit is greater than or equal to a preset threshold; and the second overcurrent detection sub-circuit is configured to perform overcurrent detection for the switch circuit when the voltage of the output terminal of the switch circuit is less than the preset threshold. | 08-27-2015 |
| 20150115283 | SIC BIPOLAR JUNCTION TRANSISTOR WITH REDUCED CARRIER LIFETIME IN COLLECTOR AND A DEFECT TERMINATION LAYER - A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT ( | 04-30-2015 |
| 20150084895 | LOAD DRIVING METHOD, LOAD DRIVING CIRCUIT, AND APPLICATION DEVICES THEREOF - The present invention discloses a load driving circuit, comprising a voltage differential generation circuit and a common mode voltage generation circuit; wherein the voltage differential generation circuit is configured to generate a driving voltage for driving a load; and the common mode voltage generation circuit is configured to: when the voltage differential generation circuit generates the driving voltage for driving the load, regulate the voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit to the same voltage value. The present invention also provides a load driving method and application devices thereof. With the technical solutions according to the present invention, a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit is effectively regulated. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. | 03-26-2015 |
| 20150035369 | CHARGING CONTROL CIRCUIT, METHOD AND ELECTRONIC DEVICE THEREOF - The present invention discloses a charging control circuit, comprising an external power source, a switching circuit, and a charging path circuit comprising a first output circuit and a second output circuit, wherein the external power source is configured to charge a secondary battery through the first output circuit and charge a load through the second output circuit, and the switching circuit is configured to decouple the secondary battery from the load when the external power source is available. Meanwhile, the present invention discloses a charging control method and an electronic device; according to the present invention, because the two output circuits are coupled to the secondary battery and the load, respectively, the load will not divide up the charging current, thereby effectively shortening the charging time and prolonging the service life of the secondary battery. | 02-05-2015 |
| 20150015333 | DIFFERENTIAL MEASUREMENTS WITH A LARGE COMMON MODE INPUT VOLTAGE - An apparatus comprises a differential amplifier circuit and a current source. The differential amplifier circuit is configured to receive a voltage at an input, wherein the differential amplifier circuit generates an output voltage having a magnitude proportional to the received voltage over a voltage range to be measured at a specified output common mode voltage. The current source is electrically connected to an input of the differential amplifier circuit and is configured to subtract a midpoint of a voltage range of the battery voltage to be measured at the input of the differential amplifier, wherein a circuit supply voltage provided to the differential amplifier circuit and the current source is less than the voltage at the input. | 01-15-2015 |
| 20140354238 | System for Battery Management and Protection - The present disclosure is directed to a system for battery management and protection. A battery protection circuit may include a power semiconductor switch and a control integrated circuit (IC). The battery protection circuit may be configured to regulate the charging and/or discharging of a battery and further prevent the battery from operating outside of a safe operating area based on a protection trip point (e.g. overcurrent detection point) of the protection IC. The protection IC may be configured to calibrate a protection trip point so as to compensate for process and temperature variations of on resistance (RSSon) of the power semiconductor switch. | 12-04-2014 |
| 20140333267 | HEATED ACCELERATED BATTERY CHARGING - This document discusses, among other things, a temperature measurement component configured to receive temperature information from a battery, a heater configured to provide heat to the battery, and a controller configured to enable and disable the heater using information from the temperature measurement component to optimize charge efficiency and capacity of the battery. | 11-13-2014 |
| 20140323184 | REVERSE CURRENT BLOCKING COMPARATOR - An apparatus comprises at least one transistor configured as analog switch, a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor, and a comparator circuit in electrical communication with the well biasing circuit and the transistor. The comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor. The well biasing circuit is configured to apply a first electrical bias to the bulk region of a transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions. | 10-30-2014 |
| 20140320327 | SCALABLE VOLTAGE RAMP CONTROL FOR POWER SUPPLY SYSTEMS - A system for scalable voltage ramp control for power supply systems. A system may comprise at least power supply circuitry, digital-to-analog (D/A) converter circuitry and a controller. The power supply circuitry may be configured to output a voltage to a load based on an input voltage provided by the D/A converter. The controller may be configured to control the D/A converter (e.g., to cause the D/A converter to provide the input voltage to the power supply circuitry) using a large range voltage ramp-up or a small range voltage ramp-up. Utilization of the large range voltage ramp-up or the small range voltage ramp-up by the controller may be based on, for example, a threshold voltage. | 10-30-2014 |
| 20140320093 | FAST LOAD TRANSIENT RESPONSE POWER SUPPLY SYSTEM USING DYNAMIC REFERENCE GENERATION - The present disclosure is directed to a fast load transient response power supply system using dynamic reference voltage generation. A system may comprise, for example, at least power supply circuitry, voltage reference circuitry and dynamic reference generation circuitry. The power supply circuitry may be configured to generate an output voltage (e.g., for driving a load) based on a power supply input voltage. The voltage reference circuitry may be configured to generate a reference voltage for use in controlling the generation of the output voltage. The dynamic reference generation circuitry may be configured to generate a dynamic reference voltage as the input voltage for the power supply circuitry based on the reference voltage and the output voltage. | 10-30-2014 |
| 20140312458 | METHODS AND APPARATUS RELATED TO AN IMPROVED PACKAGE INCLUDING A SEMICONDUCTOR DIE - In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar. | 10-23-2014 |
| 20140268462 | METHODS AND APPARATUS RELATED TO A PRECISION INPUT POWER PROTECTION DEVICE - In one general aspect, an apparatus can include an input terminal and an overvoltage protection device coupled to the input terminal and configured to receive energy via the input terminal. The overvoltage protection device can have a breakdown voltage at an ambient temperature less than a target maximum operating voltage of a source configured to be received at the input terminal. The apparatus can also include an output terminal coupled to the overvoltage protection device and a load. | 09-18-2014 |
| 20140268443 | INPUT POWER PROTECTION - In one general aspect, an apparatus can include an input terminal, an output terminal and a ground terminal. The apparatus can also include an overcurrent protection device coupled between the input terminal and the output terminal. The apparatus can further include a thermal shunt device coupled between the output terminal and the ground terminal, the thermal shunt device being configured to, at a threshold temperature, operate in a thermally-induced low-impedance state. | 09-18-2014 |
| 20140266102 | METHODS AND APPARATUS INCLUDING A CURRENT LIMITER - In one general aspect, an apparatus can include a load terminal, and a power source terminal. The apparatus can include a current limiter coupled to the load terminal and coupled to the power terminal. The current limiter can be configured to limit a current from the power source terminal to the load terminal using an electric field activated in response to a difference in voltage between the power source terminal and the load terminal. | 09-18-2014 |
| 20140264573 | METHOD FOR FORMING ACCUMULATION-MODE FIELD EFFECT TRANSISTOR WITH IMPROVED CURRENT CAPABILITY - An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates. | 09-18-2014 |
| 20140264569 | METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE - In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region. | 09-18-2014 |
| 20140264567 | DIRECT-DRAIN TRENCH FET WITH SOURCE AND DRAIN ISOLATION - In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region. | 09-18-2014 |
| 20140264434 | MONOLITHIC IGNITION INSULATED-GATE BIPOLAR TRANSISTOR - In a general aspect, an apparatus can include an insulated-gate bipolar transistor (IGBT) device disposed in a semiconductor region. The apparatus can further include a plurality of clamping diodes. The plurality of clamping diodes can be coupled in series between a collector terminal of the IGBT device and a gate terminal of the IGBT device. The apparatus can also include a gate pad disposed over at least a portion of the plurality of clamping diodes. The at least a portion of the plurality of clamping diodes can be configured, during operation of the apparatus, to have a voltage of at least 120 V applied across them. | 09-18-2014 |
| 20140244225 | BATTERY STATE OF CHARGE TRACKING, EQUIVALENT CIRCUIT SELECTION AND BENCHMARKING - A method includes calculating a first estimated state of charge (SOC) of a battery at a first time, receiving a voltage value representing a measured voltage across the battery at a second time, calculating a filter gain at the second time, and calculating a second estimated SOC of the battery at the second time based on the first estimated SOC, the voltage value, and the filter gain. Another method includes storing, in a memory, a library of equivalent circuit models representing a battery, determining an operational mode of a battery based on a load associated with the battery, selecting one of the equivalent circuit models based on the determined operational mode, and calculating a state of charge of charge (SOC) of the battery using the selected equivalent circuit model. | 08-28-2014 |
| 20140244193 | BATTERY STATE OF CHARGE TRACKING, EQUIVALENT CIRCUIT SELECTION AND BENCHMARKING - A method includes calculating a first estimated state of charge (SOC) of a battery at a first time, receiving a voltage value representing a measured voltage across the battery at a second time, calculating a filter gain at the second time, and calculating a second estimated SOC of the battery at the second time based on the first estimated SOC, the voltage value, and the filter gain. Another method includes storing, in a memory, a library of equivalent circuit models representing a battery, determining an operational mode of a battery based on a load associated with the battery, selecting one of the equivalent circuit models based on the determined operational mode, and calculating a state of charge of charge (SOC) of the battery using the selected equivalent circuit model. | 08-28-2014 |
| 20140241398 | DIFFERENTIAL THERMISTOR CIRCUIT - This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages. | 08-28-2014 |
| 20140239447 | METHODS AND APPARATUS RELATED TO CAPACITANCE REDUCTION OF A SIGNAL PORT - In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage. | 08-28-2014 |
| 20140237308 | TEST CONTROL USING EXISTING IC CHIP PINS - An apparatus and method are provided for testing normal circuitry in an integrated circuit, the method including writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode, storing a logic high signal in one of the plurality of test registers once the writing is completed, switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal, and testing the normal circuitry using the enable pin and the switch pin in the second mode. | 08-21-2014 |
| 20140233614 | ISOLATION COMMUNICATION TECHNOLOGY USING COUPLED OSCILLATORS/ANTENNAS - The present subject matter discusses, among other things, electrical isolation, and more particularly wireless electrical isolation methods and apparatus. IN an example, an electrical isolator can include a transmit circuit including a transmit antenna, and a receive circuit including a receive antenna. The transmit circuit can be configured to receive digital data and to modulate a transmit signal with the digital data, and to transmit the transit signal using the transmit antenna. The receive antenna can be configured to receive the transmit signal and to demodulate and provide the digital data from the transmit signal using a demodulation clock signal. | 08-21-2014 |
| 20140233139 | CLAMPING CIRCUIT AND DEVICE FOR EOS/SURGE/IEC - This application discusses, among other things, protection methods and apparatus for integrated circuits. In an example, an apparatus to protect a circuit from transient electrical events can include a protection transistor configured to couple a terminal of the circuit to a reference potential during the transient events, and one or more diodes coupled in series between the terminal and a control node of the protection transistor, the one or more diodes configured to trigger the protection transistor at a predetermined voltage of the terminal. In some examples, the apparatus does not include a clamp diode coupled between the control node of the protection transistor and the reference potential. | 08-21-2014 |
| 20140232454 | POWER SUPPLY PROTECTION SYSTEM - Devices and methods provide a protection device for maintaining a steady output on a gate driver terminal despite fluctuations in a power supply, the protection device including low voltage detection circuitry configured to monitor the power supply and detect fluctuations in the power supply; and gate isolation circuitry configured to isolate the gate driver terminal from the power supply if the low voltage detection circuitry detects a fluctuation in the power supply, wherein a voltage of the gate driver terminal is maintained within a preselected range when the gate is isolated. | 08-21-2014 |
| 20140231952 | PRODUCTION OF HIGH-PERFORMANCE PASSIVE DEVICES USING EXISTING OPERATIONS OF A SEMICONDUCTOR PROCESS - In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer. | 08-21-2014 |
| 20140231911 | LDMOS DEVICE WITH DOUBLE-SLOPED FIELD PLATE - In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate. | 08-21-2014 |
| 20140223557 | PERMANENT LOCKOUT ATTACK DETECTION - This document discusses, among other things, an attack detection module configured to permanently shut down a slave device after a number of consecutive attacks. | 08-07-2014 |
| 20140219442 | SECURE CRYPTO KEY GENERATION AND DISTRIBUTION - This document discusses, among other things, a method of distributing authentication keys that can prevent certain forms of circuit fabrication piracy. In an example, a method can include selecting a number of authentication keys for generation at a key generation computer, generating a random number using a random number generator of the key generation computer, generating the number of authentication keys using the random number and a key generation algorithm stored in the memory of the key generation computer, scrambling each of the number of authentication keys using a scrambling routine executing on the key generation computer, and distributing the scrambled authentication keys to an authorized manufacturers. | 08-07-2014 |
| 20140213024 | PRODUCTION OF MULTIPLE SEMICONDUCTOR DEVICES USING A SEMICONDUCTOR PROCESS - In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device. | 07-31-2014 |
| 20140203790 | Hybrid Continuous and Discontinuous Mode Operation - This disclosure is directed to hybrid continuous and discontinuous mode operation. In general, a system comprising a control module and voltage converter module may be configured to operate in a continuous conduction mode (CCM) until a current through an inductor in the voltage converter module is determined to be at or below zero (e.g., negative). The controller may then transition to operating the voltage converter module in a discontinuous control mode (DCM). Some or all of the DCM may be implemented digitally within the controller. In this manner, benefits may be realized from operating in either CCM or DCM while minimizing the disadvantages associated with these control schemes. Moreover, digitizing DCM control may allow for easier implementation and better performance than traditional DCM operation. | 07-24-2014 |
| 20140203355 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 07-24-2014 |
| 20140198543 | POWER SUPPLY WITH DC BREAKER SWITCH AND REDUCED REGULATED DC LINK VOLTAGE - Generally, this disclosure provides circuits and methods to reduce and regulate DC link voltage in a power supply through the use of a DC breaker circuit. The breaker circuit may include a breaker switch configured to couple an input stage circuit of a power supply to an output stage circuit of the power supply and to provide a regulated | 07-17-2014 |
| 20140193003 | PARASITIC ISOLATION COMMUNICATION SWITCH - This document discusses, among other things, a switch multiplexer having a common connector, the switch multiplexer including a first switch configured to receive a first signal at or above a ground (GND) reference and a second switch configured to receive a second signal that swings positive and negative about ground. The switch multiplexer includes a negative charge pump configured to bias the first switch with a negative charge pump voltage lower than the most negative voltage swing of the second signal when the second switch is enabled, and to bias the first switch with GND when the first switch is enabled. | 07-10-2014 |
| 20140184285 | Start-Up Circuitry - One embodiment provides a start-up circuit that includes start-up switch circuitry comprising a switch coupled an input voltage rail and configured to generate a start-up voltage; wherein the start-up switch circuitry is configured to generate the start-up voltage to have a predefined voltage level within a predetermined time period. The start-up circuit also includes first controller circuitry configured to control the switch to turn ON and OFF based on, at least in part, the start-up voltage; and wherein when the switch is turned ON the start-up switch circuitry generates the start-up voltage and when the switch is turned OFF the start-up circuitry discontinues the start-up voltage. | 07-03-2014 |
| 20140177876 | AUDIO AMPLIFIER PERFORMANCE WHILE MAINTAINING USB COMPLIANCE AND POWER DOWN PROTECTION - An apparatus comprises a first audio amplifier circuit configured to provide an analog audio signal and an analog switch circuit including a first input configured to receive the analog audio signal, a second input configured to receive a first digital data signal, and a first output configured to provide one of the digital data signal or the analog audio signal. The apparatus also includes a first feedback circuit coupled to the first audio amplifier circuit and the analog switch circuit output, the feedback circuit configured to bias the first audio amplifier circuit. | 06-26-2014 |
| 20140167710 | DC/DC Converter with Shunt Circuitry - The present disclosure provides, in one embodiment, a method of shunting a power supply to reduce output ripple. The method includes determining at least one performance parameter of a DC/DC converter circuit; generating a first reference signal, wherein the first reference signal is based on the performance parameter; comparing the first reference signal to the performance parameter; and generating a shunt current from an input power source to an output node of the DC/DC converter circuit based on, at least in part, the comparison of the performance parameter and the first reference signal. | 06-19-2014 |
| 20140167238 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 06-19-2014 |
| 20140143887 | SECURITY MEASURES FOR DATA PROTECTION - This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation. | 05-22-2014 |
| 20140143448 | COMBO ID DETECTION - This document discusses, among other things, an identification (ID) detection module configured to identify a first ID code in a first detect period within a first attach period and to identify a second ID code in a second detect period within the first attach period. | 05-22-2014 |
| 20140139281 | WINDOW REFERENCE TRIMMING FOR ACCESSORY DETECTION - This document discusses, among other things, a detection circuit configured to receive an output of a window comparator over a range of input values and to measure a difference between first and second thresholds of the window comparator, and a trim circuit configured to adjust at least one of the first or second thresholds using the measured difference between the first and second thresholds. | 05-22-2014 |
| 20140132312 | EFFICIENCY OPTIMIZED DRIVER CIRCUIT - Driver circuitry and methods are provided for driving a semiconductor device. The driver circuitry includes a buck converter configured to generate a baseline current, and a capacitor coupled between an output of the buck converter and ground, the capacitor configured to store charge during an off-state of the buck converter and to discharge the stored charge as a peak current during an on-state of the buck converter, wherein the baseline current reaches a current limit prior to the capacitor being fully discharged, and an output current at an output of the buck converter is based, at least in part, on the baseline current and the peak current. | 05-15-2014 |
| 20140132311 | HIGH-VOLTAGE BULK DRIVER - This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state. | 05-15-2014 |
| 20140126730 | METHODS AND APPARATUS RELATED TO PROTECTION OF A SPEAKER - In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature. | 05-08-2014 |
| 20140120694 | USE OF PLATE OXIDE LAYERS TO INCREASE BULK OXIDE THICKNESS IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described. | 05-01-2014 |
| 20140117968 | SUPPLY VOLTAGE INDEPENDENT BANDGAP CIRCUIT - This application discusses apparatus and methods for reducing supply voltage induced band gap voltage variation. In an example, a method of compensating a reference voltage current source for supply voltage variation can include providing at least a portion if a reference current for establishing the reference voltage using a first output transistor coupled to the supply voltage, maintaining a constant voltage across the first output transistor using a second output transistor coupled between the first output transistor and an output node, modulating a compensation impedance between a first node and ground as the supply voltage varies, the first node located where the first output transistor is coupled to the second output transistor, and wherein the modulating includes modulating the compensation impedance to substantially equal an output impedance, the output impedance measured between an output node and an input for the supply voltage. | 05-01-2014 |
| 20140117751 | Power Switching System with Control Signal Driven Supply Voltage - Generally, this disclosure provides systems and methods for a power switching system with a switching control circuit powered by a supply voltage derived from an input control signal. The system may include a power switch configured to electrically couple a device between a battery voltage and a ground, the device to be powered by the battery when the power switch is closed; a control circuit coupled to a gate port of the power switch, the control circuit configured to open and close the power switch by adjusting a gate driving signal provided to the gate port in response to a switching control signal provided to the control circuit; and a voltage conditioning circuit configured to generate a supply voltage based on the switching control signal, such that the supply voltage powers the control circuit. | 05-01-2014 |
| 20140115344 | APPARATUS AND METHOD FOR OPERATING AND SWITCHING A SINGLE CONDUCTOR INTERFACE - This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication scheme. In an example, a method for communicating between a master device and a slave device using a first single conductor can include transmitting a first ping on the first single conductor using a master device, the first single conductor configured to couple the master device to a slave device, receiving a slave ping on the first single conductor at the master device during a ping interval, toggling a logic level of the first single conductor prior to sending a first data packet using pulses having a duration of less than one half of a unit interval, such as a unit interval associated with a bit interval. | 04-24-2014 |
| 20140114444 | ADAPTIVE RESPONSE TIME ACCELERATION - This document discusses among other things, methods and apparatus to conserve energy when providing proximity information. An example apparatus can include an energy emitter configured to emit a first pulse of energy, an energy sensor configured to receive reflected energy from the first pulse of energy, a control circuit including a processor, the processor configured to provide first proximity information of the apparatus with respect to an object using the reflected energy. The control circuit can be configured to control the energy emitter, to compare the first proximity information with second proximity information, and to modulate a delay between the first pulse of energy and a subsequent pulse of energy using the comparison. | 04-24-2014 |
| 20140105312 | DATA DURING ANALOG AUDIO - This application discusses among other things, apparatus and method for transmitting data with an analog signal without significantly distorting the analog signal. In an example, an apparatus can include an audio channel, a capacitor coupled to a first conductor of the audio channel, the capacitor configured to couple an analog representation of a digital data signal with an analog audio signal on the audio channel, and a frequency modulator configured to receive the digital data signal and to modulate a frequency of an output signal of the frequency modulator based on a logic level of the digital data signal, wherein the analog representation of the digital data signal includes the frequency of the output signal of the frequency modulator. | 04-17-2014 |
| 20140104003 | OPERATIONAL AMPLIFIER CIRCUIT AND METHOD IMPLEMENTING THE SAME - The disclosure provides an operational amplifier circuit, in which a power supply of an amplifying circuit is coupled to a first voltage clamping circuit, and the first voltage clamping circuit clamps a supply voltage of the amplifying circuit when the supply voltage exceeds a normal-operation allowable voltage of the amplifying circuit. The disclosure also provides a method for implementing the operational amplifier circuit. According to the disclosure, the operational circuit may be avoided from subject to an excessive supply voltage, which may damage devices in the amplifying circuit of the operational amplifier. | 04-17-2014 |
| 20140103428 | TRENCH SUPERJUNCTION MOSFET WITH THIN EPI PROCESS - Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench. | 04-17-2014 |
| 20140098297 | NO POP SWITCH - A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold. | 04-10-2014 |
| 20140071650 | WIRELESS MODULE WITH ACTIVE DEVICES - A wireless multichip module has a leadframe structure | 03-13-2014 |
| 20140070392 | COMMON DRAIN POWER CLIP FOR BATTERY PACK PROTECTION MOSFET - A first embodiment is a common drain+clip | 03-13-2014 |
| 20140070339 | THROUGH SILICON VIA INCLUDING MULTI-MATERIAL FILL - An apparatus includes a substrate having at least one via disposed in the substrate, wherein the substrate includes a trench having a substantially trapezoidal cross-section, the trench extending through the substrate between a lower surface of the substrate and an upper surface of the substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening. The apparatus can include a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench, wherein the via includes a dielectric layer disposed on an inside surface of a trench. The apparatus includes and a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the substrate. | 03-13-2014 |
| 20140070329 | WIRELESS MODULE WITH ACTIVE AND PASSIVE COMPONENTS - A wireless multichip module has a leadframe structure | 03-13-2014 |
| 20140062440 | Sensorless Current Sense for Regulating Inductor Current in a Buck Converter - A device and method for sensing an inductor current in an inductor is provided that generates a voltage signal proportionate to the inductor current if the inductor is connected to a positive supply and simulates the inductor current if the inductor is not connected to the positive supply. The voltage signal may be generated by sampling an input voltage from the inductor onto a capacitor if the inductor is connected to the positive supply. The inductor current may be simulated by generating a simulation current and pushing the simulation current onto the capacitor. | 03-06-2014 |
| 20140062427 | ULTRA LOW RIPPLE BOOST CONVERTER - This document discusses, among other things, systems and methods including a boost converter configured to receive an input voltage (e.g., a battery voltage) and to provide a boosted output voltage higher than the input voltage, and a shunt regulator coupled to the output of the boost converter through a resistive element and configured to regulate an output ripple of the boosted output voltage. In an example, using the systems and methods described herein, a battery voltage of less than 5 volts can be boosted and regulated to an output voltage between 16 and 20 volts with an output ripple of less than 500 microvolts. | 03-06-2014 |
| 20140062386 | SENSOR SHARING FUEL GAUGE - A fuel gauge can include a resistor configured to generate predetermined temperature information and a switch configured to couple a temperature sensor to a temperature output of the fuel gauge in a first state and to couple the resistor to the temperature output of the fuel gauge in a second state. | 03-06-2014 |
| 20140055164 | BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT - A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal. | 02-27-2014 |
| 20140054691 | FIELD EFFECT TRANSISTOR WITH GATED AND NON-GATED TRENCHES - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 02-27-2014 |
| 20140054612 | BIPOLAR JUNCTION TRANSISTOR IN SILICON CARBIDE WITH IMPROVED BREAKDOWN VOLTAGE - A silicon carbide (SiC) bipolar junction transistor (BJT) including a collector region and a base region having an extrinsic part. The SiC BJT including an emitter region and a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT also including a surface gate at the surface passivation layer. | 02-27-2014 |
| 20140049861 | PROTECTIVE MULTIPLEXER - Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage. | 02-20-2014 |
| 20140048869 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-20-2014 |
| 20140043865 | SYNCHRONOUS RECTIFIER CONTROL TECHNIQUES FOR A RESONANT CONVERTER - A resonant converter system includes a first stage having inverter circuitry and resonant tank circuitry configured to generate an AC signal from a DC input signal, a transformer configured to transform the AC signal, and a second stage. The second stage features synchronous rectifier (SR) circuitry including a plurality of SR switches each having a body diode and SR control circuitry. SR control circuitry is configured to generate gate control signals to control the conduction state of the SR switches so that the body diode conduction time is minimized and a negative current across the SR switches is reduced or eliminated. The method includes controlling the conduction state of SR switches to conduct as the body diode associated with the switch begins to conduct and controlling the SR switch to turn off as the current through the switch approaches a zero crossing. | 02-13-2014 |
| 20140043076 | Pulsed Gate Driver - A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation. | 02-13-2014 |
| 20140042994 | Soft-Start Control Techniques for a Switched-Mode Power Supply - A power supply system including switched-mode power supply circuitry configured to generate a DC output voltage from a DC input voltage and soft-start feedback circuitry configured to control the switched-mode power supply circuitry to generate a predefined output voltage during a soft-start period of operation. The soft-start feedback circuitry includes a controllable current source configured to generate a reference current and a reference voltage, wherein the reference current is based on a difference between the reference voltage and a feedback voltage proportional to the output voltage, and amplifier circuitry configured to compare the feedback voltage with the reference voltage and generate a control signal to control the operation of the switched-mode power supply during a soft-start period of operation. | 02-13-2014 |
| 20140042536 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-13-2014 |
| 20140042532 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-13-2014 |
| 20140035627 | SiC Proportional Bias Switch Driver Circuit with Current Transformer - A switch bias system is provided that includes a silicon on carbide (SiC) bipolar junction transistor (BJT) switch comprising a base, emitter, and collector; an energy storage circuit coupled to the collector of the SiC BJT switch, the energy storage circuit supplying current flow to the collector of the SiC BJT switch; a current transformer circuit coupled to the emitter, the current transformer circuit configured to sense current flow through the emitter of the SiC BJT switch; and a proportional bias circuit configured to generate a bias current to the base of the SiC BJT switch, the bias current set to a proportion of the sensed current flow through the emitter of the SiC BJT switch. | 02-06-2014 |
| 20140035546 | Simulating Power Supply Inductor Current - One embodiment described herein provides a circuit to approximate the inductor current of a power supply that includes a capacitor; charge/discharge circuitry configured to charge the capacitor with a voltage that is proportional to an input voltage rail of the power supply, and discharge the capacitor with a voltage that is proportional to the output voltage of the power supply; and error correction circuitry is configured to adjust the voltage that is proportional to the input voltage rail and the voltage that is proportional to the output voltage based on an instantaneous current of the inductor; and wherein the voltage on the capacitor is proportional to a current associated with the inductor. | 02-06-2014 |
| 20140034968 | BIPOLAR JUNCTION TRANSISTOR WITH SPACER LAYER - New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack. | 02-06-2014 |
| 20140021933 | SYNCHRONOUS BUCK CONVERTER WITH DYNAMICALLY ADJUSTABLE LOW SIDE GATE DRIVER - One embodiment provides A DC-DC converter system that includes a high side switch and a low side switch coupled to a power supply, each switch is configured to transition from an on state to an off state and from an off state to an on state to deliver current to an inductor and a load. This embodiment also includes low side driver circuitry configured to control the conduction state of the low side switch and configured to drive the low side switch with a first gate driving signal during a first mode of operation and with a second gate driving signal during a second mode of operation. The first gate driving voltage is stronger than the second gate driving signal and the second gate driving signal is configured to cause a slower switch transition of the low side switch compared to the first gate drive control signal. | 01-23-2014 |
| 20140002139 | MAXIMUM VOLTAGE SELECTION CIRCUIT AND METHOD AND SUB-SELECTION CIRCUIT | 01-02-2014 |
| 20130341737 | PACKAGING TO REDUCE STRESS ON MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit. | 12-26-2013 |
| 20130328139 | MICROMACHINED MONOLITHIC 3-AXIS GYROSCOPE WITH SINGLE DRIVE - This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency. | 12-12-2013 |
| 20130321070 | TRANSLATOR INCLUDING OVERSTRESS PROTECTION - This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors. | 12-05-2013 |
| 20130321063 | MOS SWITCH - This document discusses, among other things, a switch circuit including a switch having a low-impedance state configured to couple a first node to a second node and a high-impedance state configured to isolate the first node from the second node. The switch circuit can include an arbiter circuit configured to receive a source voltage and an input signal, to provide, at an output, the higher voltage of the source voltage and the input signal, and to isolate the input signal form ground when the input signal has a lower voltage than the source voltage. | 12-05-2013 |
| 20130321055 | HIGH VOLTAGE CLAMP CIRCUIT - This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages. | 12-05-2013 |
| 20130320954 | SWITCHED-MODE VOLTAGE CONVERTER WITH ENERGY RECOVERY SYSTEM - Devices, systems and methods are provided for a switched-mode voltage converter system with energy recovery. The device may include a first voltage converter circuit including a boost voltage node and an output voltage port coupled to a load. The first voltage converter circuit configured to deliver energy from the boost voltage node to the load in a first mode, and to deliver energy from the load to the boost voltage node in a second mode. The device may also include a second voltage converter circuit coupled to an energy source and to the boost voltage node, the second voltage converter circuit configured to convert a first voltage associated with the energy source to a second voltage associated with the boost voltage node. | 12-05-2013 |
| 20130320881 | CURRENT OVERSHOOT LIMITING CIRCUIT - This document discusses, among other things, an apparatus, system, and method to limit a current overshoot in an electronic component using a switched feedback circuit to precondition a gate of a transistor coupled to the electronic component. | 12-05-2013 |
| 20130313571 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR COMPRISING SHIELDING REGIONS AND METHODS OF MANUFACTURING THE SAME - A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type. | 11-28-2013 |
| 20130307591 | DEPLETION-MODE CIRCUIT - This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison. | 11-21-2013 |
| 20130307517 | LOW-VOLTAGE BAND-GAP VOLTAGE REFERENCE CIRCUIT - The present application discusses low voltage band-gap voltage reference circuit and methods. In an example the circuit can include a current mirror, an operational amplifier adopting an N-Metal-Oxide-Semiconductor (NMOS) input pair structure, a band-gap output circuit, an adaptive adjustment circuit; and two branches of Bipolar Junction Transistor (BJT). The current mirror can be configured to receive an output signal of the operational amplifier and to provide a current to the two branches of BJT. The operational amplifier can be configured to differentially input voltages at the upper ends of the two branches of BJT, to generate the output signal to the current mirror, and to equalize the voltages at the upper ends of the two branches of BJT using a deep negative feedback. | 11-21-2013 |
| 20130307507 | METHOD AND APPARATUS FOR ZERO CURRENT DETECTION - This application discusses, among other things, zero current detection. In an example, a circuit for zero current detection can include a compensating circuit and a detecting circuit. The compensating circuit can be configured to feed back a compensating voltage to the detecting circuit according to an output voltage of a DC-DC converting circuit. The detecting circuit can be configured to dynamically adjust an intentional offset voltage according to the compensating voltage, and to perform zero current detection of the DC-DC converting circuit according to the adjusted Voffset. | 11-21-2013 |
| 20130307342 | Photovoltaic System Power Optimization - An example system may comprise at least one solar panel including a plurality of photovoltaic cells, wherein the photovoltaic cells are grouped into at least a first group of cells and a second group of cells. The first and second groups of cells may be coupled in series to a DC bus to deliver DC voltage and power to the DC bus. The system may further include first power conversion circuitry configured to generate power from the first group of cells and second power conversion circuitry configured to generate power from the second group of cells, and inverter circuitry coupled to the DC bus and configured to generate AC power from the DC bus. The first power conversion circuitry may be configured to automatically adjust at least one of an output voltage or power delivered to the DC bus based on an operating point of the second power conversion circuitry. | 11-21-2013 |
| 20130307134 | CONDUCTIVE CHIP DISPOSED ON LEAD SEMICONDUCTOR PACKAGE AND METHODS OF MAKING THE SAME - In one implementation, a method of forming a conductive device can include depositing a non-conductive epoxy on a first portion of a lower surface of a semiconductor die, and can include depositing a conductive epoxy on a second portion of the lower surface of the semiconductor die. | 11-21-2013 |
| 20130298671 | FLEXURE BEARING TO REDUCE QUADRATURE FOR RESONATING MICROMACHINED DEVICES - An example include microelectromechanical die for sensing motion that includes a fixed portion, an anchor coupled to the fixed portion, a first nonlinear suspension member coupled to anchor on a side of the anchor, a second nonlinear suspension member coupled to the anchor on the same side of the anchor, the second nonlinear suspension member having a shape and location mirroring the first nonlinear suspension member about an anchor bisecting plane and a proof-mass that is planar, the proof mass suspended at least in part by the first nonlinear suspension member and the second nonlinear suspension member such that the proof-mass is rotable about the anchor and is slideable in a plane parallel to the fixed portion. | 11-14-2013 |
| 20130292771 | METHOD AND APPARATUS FOR INTEGRATED CIRCUIT PROTECTION - In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage. | 11-07-2013 |
| 20130286517 | METHOD AND APPARATUS FOR ELECTROSTATIC DISCHARGE PROTECTION - This application discusses, among other things, apparatus and methods for electrostatic discharge (ESD) protection. In an example, an ESD protection circuit can include an ESD control circuit, and a driver-off circuit, wherein the ESD control circuit is configured to send an enable signal to the driver-off circuit and to perform electrostatic discharge to a ground node when detecting occurrence of electrostatic charges, and wherein the driver-off circuit is configured to disable a driving device upon reception of the enable signal. | 10-31-2013 |
| 20130285730 | CLAMP CIRCUIT AND METHOD FOR CLAMPING VOLTAGE - The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to V | 10-31-2013 |
| 20130277773 | THROUGH SILCON VIA WITH REDUCED SHUNT CAPACITANCE - This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon. | 10-24-2013 |
| 20130277772 | MICROELECTROMECHANICAL PRESSURE SENSOR INCLUDING REFERENCE CAPACITOR - This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion. | 10-24-2013 |
| 20130271228 | MICRO-ELECTRO-MECHANICAL-SYSTEM (MEMS) DRIVER - In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state. | 10-17-2013 |
| 20130270660 | SEALED PACKAGING FOR MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit. | 10-17-2013 |
| 20130270657 | MICROMACHINED MONOLITHIC 6-AXIS INERTIAL SENSOR - The device layer of a 6-degrees-of-freedom (6-DOF) inertial measurement system can include a single proof-mass 6-axis inertial sensor formed in an x-y plane, the inertial sensor including a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards the edge of the inertial sensor, a central suspension system configured to suspend the 6-axis inertial sensor from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 6-axis inertial sensor about a z-axis normal to the x-y plane. | 10-17-2013 |
| 20130269413 | MEMS QUADRATURE CANCELLATION AND SIGNAL DEMODULATION - In certain examples, a quadrature cancellation apparatus can include a drive charge amplifier configured to couple to a proof mass of a MEMS device and to provide oscillation motion information, a first sense charge amplifier configured to couple to the proof mass and to provide first sense information of a first movement of the MEMS device, a first programmable amplifier configured to receive the oscillation motion information and provide amplified oscillation motion information, a first summer configured to cancel quadrature error of the first sense information using the first sense information and the amplified oscillation motion information to provide quadrature-corrected first sense information, a phase shifter configured to receive the oscillation motion information and to provide carrier information, and a first multiplier configured to provide demodulated first sense information using the quadrature-corrected first sense information and the carrier information. | 10-17-2013 |
| 20130268228 | MEMS DEVICE QUADRATURE SHIFT CANCELLATION - This document discusses, among other things, apparatus and methods quadrature cancelation of sense information from a micro-electromechanical system (MEMS) device, such as a MEMS gyroscope. In certain examples, a quadrature correction apparatus can include a drive charge-to-voltage (C2V) converter configured to provide drive information of a proof mass of a MEMS gyroscope, a sense C2V converter configured to provide sense information of the proof mass, a phase-shift module configured to provide phase shift information of the drive information, a drive demodulator configured to receive the drive information and the phase shift information and to provide demodulated drive information, a sense demodulator configured to receive the sense information and the phase shift information and to provide demodulated sense information, and wherein the quadrature correction apparatus is configured to provide corrected sense information using the demodulated drive information and the demodulated sense information. | 10-10-2013 |
| 20130268227 | MEMS DEVICE AUTOMATIC-GAIN CONTROL LOOP FOR MECHANICAL AMPLITUDE DRIVE - This document discusses, among other things, apparatus and methods for digital automatic gain control for driving a MEMS device, such as a proof mass. In an example, an apparatus can include a driver configured to oscillate a proof mass of a MEMS device, a charge-to-voltage (C2V) converter configured to provide oscillation information of the proof mass, an analog-to-digital converter (ADC) configured to provide a digital representation of the oscillation information, and a digital, automatic gain control circuit to provide oscillation amplitude error information using a comparison of the oscillation information to target amplitude information, and to provide a digital drive command signal using an amplified representation of the oscillation amplitude error information. | 10-10-2013 |
| 20130265184 | AUDIO DEVICE SWITCHING WITH REDUCED POP AND CLICK - This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds. | 10-10-2013 |
| 20130265183 | NOISE REDUCTION METHOD WITH CHOPPING FOR A MERGED MEMS ACCELEROMETER SENSOR - An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor. | 10-10-2013 |
| 20130265070 | SELF TEST OF MEMS ACCELEROMETER WITH ASICS INTEGRATED CAPACITORS - An apparatus comprises a micro-electromechanical system (MEMS) sensor including a first capacitive element and a second capacitive element and an integrated circuit (IC). The IC includes a switch network circuit and a capacitance measurement circuit. The switch network circuit is configured to electrically decouple the first capacitive element of the MEMS sensor from a first input of the IC and electrically couple the second capacitive element to a second input of the IC. The capacitance measurement circuit can be configured to measure capacitance of the second capacitive element of the MEMS sensor during application of a first electrical signal to the decoupled first capacitive element. | 10-10-2013 |
| 20130263665 | MEMS DEVICE FRONT-END CHARGE AMPLIFIER - This document discusses, among other things, apparatus and methods for a front-end charge amplifier. In certain examples, a front-end charge amplifier for a microelectromechanical system (MEMS) device can include a charge amplifier configured to couple to the MEMS device and to provide sense information of a proof mass of the MEMS device, a feedback circuit configured to receive the sense information and to provide feedback to an input of the charge amplifier, and wherein the charge amplifier includes a transfer function having a first pole at a first frequency, a second pole at a second frequency, and one zero at a third frequency. | 10-10-2013 |
| 20130263641 | SELF TEST OF MEMS GYROSCOPE WITH ASICS INTEGRATED CAPACITORS - An apparatus includes a MEMS gyroscope sensor including a first sensing capacitor and a second sensing capacitor and an IC. The IC includes a switch circuit configured to electrically decouple the first sensing capacitor from a first input of the IC and electrically couple the second sensing capacitor to a second input of the IC, and a capacitance measurement circuit configured to measure capacitance of the second sensing capacitor of the MEMS gyroscope sensor during application of a first electrical signal to the decoupled first capacitive element. | 10-10-2013 |
| 20130259269 | BUTTON-PRESS DETECTION AND FILTERING - The disclosure provides a button-press detection and filtering method, related circuit, and button-press detection chip for a external device. A button-press signal from a wire control apparatus is coupled to the button-press detection chip for the external device. The button-press detection chip for the external device can digitally sample the button-press signal through the filter circuit and outputs a digital logic signal corresponding to a button to an audio codec according to the sampling result. The audio codec can determine a pressed button according to the digital logic signal and performs a corresponding function. With the solutions of the disclosure, a noise interference signal in a button-press signal may be avoided and a pressed button may be accurately detected, without using a dedicated chip or complex software codes in a wire control apparatus and an electronic device. | 10-03-2013 |
| 20130257487 | ACCURATE NINETY-DEGREE PHASE SHIFTER - An apparatus includes a drive signal circuit for MEMS sensor. The drive signal circuit includes an input configured to receive a voltage signal representative of charge generated by the MEMS sensor, a phase-shift circuit electrically coupled to the input and configured to phase shift an input signal by substantially ninety degrees, and a comparator circuit with hysteresis. An input of the comparator is electrically coupled to an output of the phase-shift circuit and an output of the comparator circuit is electrically coupled to an output of the drive signal circuit. A feedback loop extends from the output of the drive signal circuit to the input of the phase-shift circuit and is configured to generate a self-oscillating signal at an output of the drive signal circuit. An output signal generated by the drive signal circuit is applied to a drive input of the MEMS sensor. | 10-03-2013 |
| 20130250532 | MULTI-DIE MEMS PACKAGE - This document refers to multi-die micromechanical system (MEMS) packages. In an example, a multi-die MEMS package can include a controller integrated circuit (IC) configured to couple to a circuit board, a MEMS IC mounted to a first side of the controller IC, a through silicon via extending through the controller IC between the first side and a second side of the controller IC, the second side opposite the first side, and wherein the MEMS IC is coupled to the through silicon via. | 09-26-2013 |
| 20130249524 | ENHANCED ON-TIME GENERATOR - This document discusses, among other things, voltage converters and computed on-time voltage converters. In an example, an on-time generator for a voltage converter can include a timing capacitor configured to provide a timing voltage, a comparator configured to receive the timing voltage and a threshold voltage and to provide the timing signal using a comparison of the timing voltage and the threshold voltage, a current source configured to discharge the timing voltage of the timing capacitor after a start-up delay, and first and second compensation capacitors configured to bias the timing voltage of the timing capacitor to compensate for the start-up delay. | 09-26-2013 |
| 20130249520 | BOOST REGULATOR WITH TIMING CONTROLLED INDUCTOR BYPASS - Apparatus and methods of implementing a voltage converter bypass switch, among other things, are discussed herein. In certain examples, a boost converter can include a bypass switch configured to bypass an inductor and a transistor of the boost converter to more directly couple a supply voltage to an output of the boost converter during a bypass mode, and to isolate a supply voltage input from the output during a boost mode of the boost converter. | 09-26-2013 |
| 20130249519 | Improved Startup of DC-DC Converters - Generally, this disclosure provides methods and systems for improved startup for DC-DC converters that reduce input voltage droop, in-rush current and output voltage jumps. The system may include a power stage circuitry including a plurality of power segments coupled in parallel, the power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to the output stage circuitry. The system may further include PWM and power stage controller circuitry configured to sequentially and progressively activate the plurality of power segments to limit an input in-rush current from the input voltage during a ramp up period and output voltage at the output stage circuitry. | 09-26-2013 |
| 20130249513 | ADAPTIVE STARTUP CONTROL FOR BOOST CONVERTER - This document discusses, among other things, apparatus and methods for a boost converter start-up circuit. In an example, a start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. The linear current generator can include a modified current mirror and a feedback circuit configured to provide a first representative of an output voltage of the output terminal to an input of each of a first and a second adjustable current source of the modified current mirror. | 09-26-2013 |
| 20130249438 | EARLY WARNING STROBE FOR MITIGATION OF LINE AND LOAD TRANSIENTS - This document discusses apparatus and methods associated with an early warning strobe input of a boost converter. In an example, a method of increasing a set point of a boost converter configured to provide power to a mobile device can include receiving an indication that the mobile device will transition from the first low-power mode to a second higher-power mode; and increasing the set point of the boost converter in response to the indication. | 09-26-2013 |
| 20130248991 | STRUCTURE AND METHOD FOR FORMING TRENCH-GATE FIELD EFFECT TRANSISTOR - A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric. | 09-26-2013 |
| 20130247668 | INERTIAL SENSOR MODE TUNING CIRCUIT - This document discusses, among other things, an mode matching circuit for a inertial sensor including an oscillator circuit configured to selectively couple to a sense axis of an inertial sensor and to provide sense frequency information of the sense axis, a frequency comparator configured to receive the sense frequency information of the sense axis and drive frequency information of the inertial sensor, and to provide frequency difference information to a processor, and a programmable bias source configured to apply a bias voltage to the sense axis to set a sense frequency of the sense axis in response to a command from the processor, and to maintain a desired frequency difference between the sense frequency and a drive frequency of the inertial sensor. | 09-26-2013 |
| 20130247666 | MICROMACHINED 3-AXIS ACCELEROMETER WITH A SINGLE PROOF-MASS - This document discusses, among other things, an inertial measurement system including a device layer including a single proof-mass 3-axis accelerometer, a cap wafer bonded to a first surface of the device layer, and a via wafer bonded to a second surface of the device layer, wherein the cap wafer and the via wafer are configured to encapsulate the single proof-mass 3-axis accelerometer. The single proof-mass 3-axis accelerometer can be suspended about a single, central anchor, and can include separate x, y, and z-axis flexure bearings, wherein the x and y-axis flexure bearings are symmetrical about the single, central anchor and the z-axis flexure is not symmetrical about the single, central anchor. | 09-26-2013 |
| 20130241660 | Buck Up Power Converter - Generally, this disclosure provides an apparatus, method and system for DC-DC conversion. The apparatus may include a switch network including a first plurality of switches configured to operate in a Buck mode to generate an output voltage that is less than an input voltage, and a second plurality of switches configured to operate in an Up mode to generate an output voltage that is greater than the input voltage. The apparatus of this example may further include controller circuitry configured to generate control signals to control the conduction state of the first plurality of switches and the second plurality of switches based on a variable reference signal indicative of power demands from a load coupled to the switch network. | 09-19-2013 |
| 20130234774 | LEVEL SWITCHING CIRCUIT AND METHOD FOR CONTROLLING RAIL-TO-RAIL ENABLING SIGNAL - This document discusses, among other things, methods for controlling a Rail-to-Rail enabling signal, including providing a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply coupled to the level switching circuit. The document also discusses a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit configured to output a disabling signal properly to provide an accurate enabling control signal for equipment operated under control of an enabling control in case of the failure of the power supply. | 09-12-2013 |
| 20130224922 | UMOS Semiconductor Devices Formed by Low Temperature Processing - UMOS (U-shaped trench MOSFET) semiconductor devices that have been formed using low temperature processes are described. The source region of the UMOS structure can be formed before the etch processes that are used to create the trench, allowing low-temperature materials to be incorporated into the semiconductor device from the creation of the gate oxide layer oxidation forward. Thus, the source drive-in and activation processing that are typically performed after the trench etch can be eliminated. The resulting UMOS structures contain a trench structure with both a gate insulting layer comprising a low temperature dielectric material and a gate conductor comprising a low temperature conductive material. Forming the source region before the trench etch can reduce the problems resulting from high temperature processes, and can reduce auto doping, improve threshold voltage control, reduce void creation, and enable incorporation of materials such as silicides that cannot survive high temperature processing. Other embodiments are described. | 08-29-2013 |
| 20130222046 | MODIFIED BINARY SEARCH FOR TRANSFER FUNCTION ACTIVE REGION - This document discusses, among other things, a modified binary search configured to identify monotonic transfer function active region boundaries. The modified binary search can avoid false results outside of the active region of the monotonic transfer function. | 08-29-2013 |
| 20130221905 | CURRENT OBSERVER CIRCUITRY FOR BATTERY CHARGERS - According to one aspect of the present disclosure, there is provided a battery charging system. The battery charging system includes battery charging circuitry configured to provide charging current to a battery. The battery charging system further includes feedback circuitry configured to generate a feedback signal indicative of a battery charging condition, wherein the battery charging system is configured to control the battery charging current based on, at least in part, the feedback signal. The battery charging system further includes feed forward circuitry configured to adjust the feedback signal to decrease battery charging current when a decrease in battery current draw exceeds a threshold, and wherein the feed forward circuitry is configured to decrease the battery charging current faster than the feedback circuitry. | 08-29-2013 |
| 20130207186 | STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 08-15-2013 |
| 20130187619 | SHUNT REGULATOR - This document discusses, among other things, a circuit including a diode and a transistor. In certain examples, an integrated circuit can include the diode and the transistor. In some examples, an apparatus can include the diode having a first temperature coefficient, a bias resistor configured to bias the diode, and a bipolar junction transistor having a second temperature coefficient the bipolar junction transistor having a base coupled to the diode and the bias resistor, wherein the first temperature coefficient and the second temperature coefficient are configured to reduce at least a portion of a temperature drift effect of the diode and the bipolar transistor. | 07-25-2013 |
| 20130187173 | CONDUCTIVITY MODULATION IN A SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region. | 07-25-2013 |
| 20130181282 | FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND HEAVY BODY REGIONS - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 07-18-2013 |
| 20130176755 | DIMMER CONTROL WITH SOFT START OVER-CURRENT PROTECTION - This document discloses, among other things, apparatus and methods for dimmer control. In an apparatus example, a circuit can include an input configured to receive a control signal, a controller configured to modulate a pulse width of a pulse train using the control signal when the controller is enabled, an output configured to provide the pulse train to a driver, and first and second current limit detectors configured to receive load current information of the driver and to terminate an active pulse of the controller when a value of the load current information exceeds a threshold. | 07-11-2013 |
| 20130169059 | Dual Input Single Output Power Multiplexer for Near Field Communication Application - Generally, this disclosure provides systems, methods and platforms for power multiplexer switching operations. The system may include a near field communication (NFC) module configured to receive power through a radio frequency (RF) channel; a subscriber identity module (SIM) circuit configured with a supply voltage port; and a power multiplexer circuit configured to controllably couple the SIM circuit supply voltage port to the NFC module, wherein the NFC module provides a supply voltage to the SIM circuit such that the SIM circuit is operable in the absence of primary device power source. | 07-04-2013 |
| 20130154709 | SYSTEMS AND METHODS FOR OUTPUT CONTROL - The present disclosure provides an output control circuit including a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to compare an output voltage with a set output voltage threshold and to output a disable signal to an enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. | 06-20-2013 |
| 20130139592 | MEMS MULTI-AXIS GYROSCOPE Z-AXIS ELECTRODE STRUCTURE - Various examples include microelectromechanical die for sensing motion that includes symmetrical proof-mass electrodes interdigitated with asymmetrical stator electrodes. Some of these examples include electrodes that are curved around an axis orthogonal to the plane in which the electrodes are disposed. An example provides vertical flexures coupling an inner gimbal to a proof-mass in a manner permitting flexure around a horizontal axis. | 06-06-2013 |
| 20130132626 | PIN SELECTABLE I2C SLAVE ADDRESSES - This document discusses, among other things, a multi-address Inter-Integrated Circuit (I | 05-23-2013 |
| 20130126910 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact. | 05-23-2013 |
| 20130119467 | DEVICES, METHODS, AND SYSTEMS WITH MOS-GATED TRENCH-TO-TRENCH LATERAL CURRENT FLOW - A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained. | 05-16-2013 |
| 20130087809 | METHOD OF MANUFACTURING A SiC BIPOLAR JUNCTION TRANSISTOR AND SiC BIPOLAR JUNCTION TRANSISTOR THEREOF - A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided. | 04-11-2013 |
| 20130087808 | SIC BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN EMITTER - New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion. | 04-11-2013 |
| 20130082644 | CHARGER DETECTION WITH PROPRIETARY CHARGER SUPPORT - Method and apparatus, among other things, are provided for detecting a charger type. In an example, a method to classify a potential charger coupled to a port of an electronic device can include detecting the potential charger coupled to a USB-compatible port of the electronic device, applying a pull-down current to first and second data lines of the USB-compatible port to provide a first test voltage on each of the first and second data lines, and executing a primary detection process of a USB Battery Charging 1.2 Compliance Plan if the first test voltage on each of the first and second data lines is not between a first threshold and a second threshold using the pull-down current. | 04-04-2013 |
| 20130076147 | MULTIPLE BATTERY POWER PATH MANAGEMENT SYSTEM - Devices, systems and methods are provided for multiple battery power path management. The device may include a first battery port configured to couple to a first battery; a second battery port configured to couple to a second battery; an output voltage port configured to couple to a device to be powered; a battery selection port configured to couple to the device to be powered; a control circuit configured to select one of the first battery and the second battery as a power source battery, the selection based on a signal received at the battery selection port; and a first switch configured to selectively couple the first battery port or the second battery port to the output voltage port, the selective coupling based on a first switching signal generated by the control circuit in response to the selection of the power source battery. | 03-28-2013 |
| 20130063844 | Load Switch with True Reverse Current Blocking - Devices, systems and methods are provided for switching a load with true reverse current blocking (TRCB). The device may include an input port coupled to a supply voltage; an output port coupled to the load; a TRCB circuit coupled to the input port and the output port; and a switch control port coupled to the TRCB circuit. The TRCB circuit may be configured to couple the input port to the output port in response to a switch close signal applied to the switch control port and to de-couple the input port from the output port in response to a switch open signal applied to the switch control port. The TRCB circuit may further be configured to block current flow from the output port to the input port in response to both the switch open signal and the switch close signal. | 03-14-2013 |
| 20130063116 | TRUE REVERSE CURRENT BLOCKING SYSTEM - Devices, systems and methods are provided for a switch to perform true reverse current blocking (TRCB). The device may include a PMOS switch, including a source port, a drain port, a gate port and an n-well region; an input voltage port coupled to the source port; an output voltage port coupled to the drain port; a switch control port coupled to the gate port; and comparator circuitry configured to compare an input voltage at the input voltage port with an output voltage at the output voltage port and select a maximum of the input voltage and the output voltage. The comparator circuitry may be further configured to couple the selected maximum to the n-well region. | 03-14-2013 |
| 20130034242 | MIC AUDIO NOISE FILTERING - This document discusses, among other things, a MIC audio noise filtering system configured to detect MIC audio noise at a pole of a four-pole audio jack using first and second comparators. The MIC audio noise detection system can include first and second comparators configured to compare a value of the pole to respective first and second thresholds and to provide an output indicative of the comparisons and a detection circuit configured to count changes in the output over a first period of time and to detect MIC audio noise at the pole of the four-pole audio jack using the count. | 02-07-2013 |
| 20130027089 | CIRCUIT AND METHOD FOR DETECTING MULTIPLE SUPPLY VOLTAGES - An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a V | 01-31-2013 |
| 20130026563 | STRUCTURES AND METHODS FOR FORMING HIGH DENSITY TRENCH FIELD EFFECT TRANSISTORS - A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions. | 01-31-2013 |
| 20130022208 | ACTIVE AUDIO TRANSDUCER PROTECTION - This document discusses, among other things, apparatus and methods for providing audio transducer protection. In an example, an audio protection circuit can include a first comparator configured to compare peak power information of a drive signal of an amplifier of an audio system with a first threshold, a limiter circuit configured to limit an input of the amplifier if the peak power information of the drive signal exceeds the first threshold, and a second comparator configured to compare average power information of the drive signal with a second threshold and to provide an output signal configured to modulate a gain of a pre-amplifier of the audio system using the comparison. | 01-24-2013 |
| 20130021046 | AUDIO JACK DETECTION CIRCUIT - This document discusses, among other things, a detection system configured to identify a type of a pole of a four-pole audio jack using first and second comparators. The detection system can include a bias circuit configured to bias a detection input coupled to the pole, and first and second comparators configured to compare the detection input to respective first and second thresholds to provide an indication of the type of the pole. | 01-24-2013 |
| 20130021041 | DETECTION AND GSM NOISE FILTERING - This document discusses, among other things, a GSM noise detection system configured to detect GSM noise at a pole of a four-pole audio jack using first and second comparators. The GSM noise detection system can include first and second comparators configured to compare a value of the pole to respective first and second thresholds and to provide an output indicative of the comparisons and a detection circuit configured to count changes in the output over a first period of time and to detect GSM noise at the pole of the four-pole audio jack using the count. | 01-24-2013 |
| 20130020611 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A STRUCTURE IN A TARGET SUBSTRATE FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer on the target substrate and providing a stair-like profile in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material. | 01-24-2013 |
| 20120326764 | MIPI ANALOG SWITCH FOR AUTOMATIC SELECTION OF MULTIPLE IMAGE SENSORS - An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface. | 12-27-2012 |
| 20120326736 | DETECTING ACCESSORIES ON AN AUDIO OR VIDEO JACK - A detection circuit can be configured to receive a digital value from an identification register and to determine a resistance at a conducting terminal of an audio or video jack plug using the digital value. The detection circuit can include a current source that outputs a current according to the digital value from the identification register and a comparator that compares a reference voltage to a voltage created by the current source across the resistance at the conducting terminal of the audio or video jack plug. A control logic circuit can be configured to store the digital value in the identification register, generate an interrupt signal to cause a processor to read the digital value, and identify a function of an accessory device including the audio or video jack plug, when the detection circuit determines the resistance at the conducting terminal of the audio or video jack plug. | 12-27-2012 |
| 20120320481 | Protection System - Devices, systems and methods are provided for protecting electronic circuitry from voltage transients including undervoltage transients in a supply voltage. The device may include a first low voltage isolated transistor coupled in forward bias with respect to a power supply and a second low voltage isolated transistor coupled in series with the first low voltage isolated transistor and in reverse bias with respect to the power supply voltage. The device may further include a resistor coupled between a gate of the first low voltage isolated transistor and the power supply, the resistor configured to limit current flow to the gate of the first low voltage isolated transistor during an overvoltage event. | 12-20-2012 |
| 20120319776 | DC VOLTAGE ERROR PROTECTION CIRCUIT - This document discusses among other things apparatus and methods for protecting circuit elements from harmful voltages. In an example, an apparatus can include an amplifier configured to receive an input signal and to provide an estimate of a first output signal, a peak detector to receive the estimate and to generate a comparison signal that is active when the amplified input signal exceeds a threshold value, and a timer configured to activate a second output signal if the comparison signal is active for at least a selected time period. The timer can include a first digital input and the selected time period can be set using a state of the first digital input. | 12-20-2012 |
| 20120274369 | POWER-ON-RESET CIRCUIT AND RESET METHOD - Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage. | 11-01-2012 |
| 20120265911 | MOBILE DEVICE AUTO DETECTION APPARATUS AND METHOD - This application discusses, among other things, multiple interface detection circuits configured to connect with a mobile electronic device connector. In an example, a multiple interface detection circuit can include a first comparator to compare a bus voltage of the mobile electronic device connector with a first threshold and to provide a first control signal, a second comparator to compare the bus voltage of the mobile electronic device connector with the first threshold and to provide a second control signal, a third comparator to compare the bus voltage of the mobile electronic device connector with a second threshold and to provide a third control signal, and a switch control configured to switch one or more signals of the connector. | 10-18-2012 |
| 20120262233 | MIXED SIGNAL DYNAMIC RANGE COMPRESSION - This document discusses, among other things, apparatus and methods for providing dynamic range compression. In an example, an amplifier can an first amplifier configured to receive a representation of an input signal and provide an amplified representation of the input signal to an output stage, an automatic gain control comparator configured to provide automatic gain control information to the first amplifier, a plurality of dynamic range compression comparators configured to provide a plurality of signals indicative of an amplitude of an output signal of the output stage, a first voltage divider configured to provide an automatic gain control threshold to the automatic gain control comparator, and a second voltage divider configured to receive the automatic gain control threshold and to provide a plurality of range compression thresholds to the plurality of dynamic range compression comparators. | 10-18-2012 |
| 20120262211 | CLASS D PULSE WIDTH MODULATOR WITH DUAL FEEDBACK - This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage. | 10-18-2012 |
| 20120223728 | METHOD AND SYSTEM THAT DETERMINES THE VALUE OF A RESISTOR IN LINEAR AND NON-LINEAR RESISTOR SETS - The present subject matter refers to apparatus and methods for identifying a resistance level of a resistor. In an example, circuit configured to identify a resistor can include a plurality of current sources, each current source selectively coupled to the resistor to generate a resistor voltage, a comparator configured to compare the resistor voltage and a reference voltage, and to provide an output indicative of the comparison, and a controller configured to selectively couple a first one or more current sources of the plurality of current sources to the resistor, and to selectively couple a second one or more current sources of the plurality of current sources to the resistor in response to the output indicative of the comparison. | 09-06-2012 |
| 20120211834 | MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES - A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure. | 08-23-2012 |
| 20120206184 | DETERMINING AUTOMATIC GAIN CONTROL LEVELS - An apparatus comprises an integrated circuit (IC) and a resistor external to the IC. The IC includes a current output digital-to-analog converter (IDAC) circuit configured to provide an adjustable specified current to a resistor external to the apparatus, a voltage sensing circuit configured to sense the voltage of the external resistor, and an automatic gain control (AGC) circuit configured to receive threshold information using the adjustable specified current. | 08-16-2012 |
| 20120156845 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE - A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches. | 06-21-2012 |
| 20120146204 | SEMICONDUCTOR DEVICES AND ELECTRICAL PARTS MANUFACTURING USING METAL COATED WIRES - The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with other metallic materials, but at lower costs because instead of plating the lead frame the wire is plated. The wire can be either gold or aluminum. When the wire is gold, the coating may be silver or other suitable metallic materials. When the wire is aluminum, the coating may be nickel, palladium, or other suitable metals. | 06-14-2012 |
| 20120146140 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE - A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region. | 06-14-2012 |
| 20120133016 | LATERAL POWER DIODE WITH SELF-BIASING ELECTRODE - A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode. | 05-31-2012 |
| 20120100670 | WAFER LEVEL BUCK CONVERTER - A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die. | 04-26-2012 |
| 20120094458 | HYBRID-MODE LDMOS - An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode. | 04-19-2012 |
| 20120094436 | EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME - A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other. | 04-19-2012 |
| 20120086051 | SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON - A vertical semiconductor device includes a bottom metal layer and a first P-type semiconductor layer overlying the bottom metal layer. The first P-type semiconductor layer is characterized by a surface crystal orientation of (110) and a first conductivity. The first P-type semiconductor layer is heavily doped. The vertical semiconductor device also includes a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The vertical semiconductor device also has a top metal layer overlying the second P-type semiconductor layer. A current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane. | 04-12-2012 |
| 20120001610 | BUCK-BOOST REGULATOR WITH DEAD BAND - This document provides methods and apparatus configured to efficiently regulate an output voltage near a desired voltage level, for example, under varying input or load conditions. An example apparatus can include a regulator having a boost controller configured to provide voltage to an output of the regulator when at least one of the output voltage or the input voltage is below a first threshold voltage and a buck controller configured to provide voltage to the output of the regulator when at least one of the output voltage or the input voltage is above a second threshold voltage. Further, the regulator can be configured to provide the input voltage at the output of the regulator when at least one of the input voltage or the output voltage is between the first and second threshold voltages. In some examples, the first threshold is below the second threshold. | 01-05-2012 |
| 20120001313 | SEMICONDUCTOR PACKAGE WITH AN EMBEDDED PRINTED CIRCUIT BOARD AND STACKED DIE - A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module. | 01-05-2012 |
| 20110318920 | LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE - A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours. | 12-29-2011 |
| 20110316078 | SHIELDED LEVEL SHIFT TRANSISTOR - A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface. | 12-29-2011 |
| 20110293100 | AUDIO AMPLIFIER PERFORMANCE WHILE MAINTAINING USB COMPLIANCE AND POWER DOWN PROTECTION - An apparatus comprises a first audio amplifier circuit configured to provide an analog audio signal and an analog switch circuit including a first input configured to receive the analog audio signal, a second input configured to receive a first digital data signal, and a first output configured to provide one of the digital data signal or the analog audio signal. The apparatus also includes a first feedback circuit coupled to the first audio amplifier circuit and the analog switch circuit output, the feedback circuit configured to bias the first audio amplifier circuit. | 12-01-2011 |
| 20110284955 | FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS - In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region. | 11-24-2011 |
| 20110275208 | SHIELD CONTACTS IN A SHIELDED GATE MOSFET - A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region. | 11-10-2011 |
| 20110255203 | CHARGE PUMP SWITCH POWER DOWN PROTECTION - This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold. | 10-20-2011 |
| 20110204960 | Fully Featured Control Pin Powered Analog Switch - An apparatus comprises at least one input connection, at least one output connection, at least one control connection, a voltage converter circuit having an input coupled to the control connection and an output, wherein the voltage converter circuit is configured to provide a voltage at its output that is greater than a voltage present at its input, and at least one switch circuit coupled to the input connection, the output connection, and the output of the voltage converter circuit. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by the voltage converter output. Power to the voltage converter circuit is provided via the control connection, and power to the switch circuit is provided via the output of the voltage converter circuit. | 08-25-2011 |
| 20110204955 | CONTROL PIN POWERED ANALOG SWITCH - An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection. | 08-25-2011 |
| 20110199123 | MULTIPLE DETECTION CIRCUIT FOR ACCESSORY JACKS - This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator. | 08-18-2011 |
| 20110163391 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 07-07-2011 |
| 20110161532 | TRANSCEIVER FOR WIRED SERIAL COMMUNICATION - This document discusses, among other things, transceiver apparatus and methods for wired serial communication to a remote device. The transceiver can be configured to generate an output signal using received compensation information to maintain a specified signal quality at the remote device. The transceiver can include an input for receiving first information, a compensation input for receiving the compensation information and an output to transmit the output signal including the first information to a component coupled between the transceiver and the remote device. | 06-30-2011 |
| 20110148510 | REDUCED CURRENT CHARGE PUMP - This document discusses, among other things, a charge pump having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current for a capacitor using a comparison of an output voltage to at least one reference voltage. | 06-23-2011 |
| 20110148386 | FAST RECOVERY VOLTAGE REGULATOR - This document discusses, among other things, a voltage regulator having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current using a comparison of a regulated Dc output voltage to at least one reference voltage. | 06-23-2011 |
| 20110148385 | SELECTIVELY ACTIVATED THREE-STATE CHARGE PUMP - This document discusses, among other things, a device for providing a DC output voltage, including a first output voltage and a second output voltage, from an input voltage. The device can include a first voltage regulator configured to provide the first output voltage when the input voltage is below a threshold voltage, and a charge pump configured to provide the second output voltage from the first output voltage in a two-state mode when the input voltage is below the threshold voltage, and to provide the first output voltage and the second output voltage in a three-state mode when the input voltage is above the threshold voltage. | 06-23-2011 |
| 20110147917 | INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED COMPONENTS - This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions. | 06-23-2011 |
| 20110133318 | SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace. | 06-09-2011 |
| 20110127607 | STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 06-02-2011 |
| 20110124197 | METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES - A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. | 05-26-2011 |
| 20110124158 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 05-26-2011 |
| 20110099300 | CAMERA SHUTTER CONTROL THROUGH A USB PORT OR AUDIO/VIDEO PORT - An apparatus comprises a digital image sensor, a communication port, a detection circuit and a processor. The detection circuit is configured to detect a change in electrical resistance at a connector of the communication port. The processor is configured to initiate an operation of the apparatus according to the detected change in resistance. | 04-28-2011 |
| 20110099298 | METHOD OF DETECTING ACCESSORIES ON AN AUDIO JACK - An apparatus comprises an audio or video jack connector configured to receive an audio or video jack plug of a separate device, a detection circuit in electrical communication with the connector, and a processor communicatively coupled to the detection circuit. The connector includes an electrical contact for connection to a conducting terminal of the plug. The detection circuit is configured to determine a resistance at the conducting terminal. The resistance is a resistive load of the separate device at the conducting terminal of the plug. The processor is configured to identify a function of the separate device according to the determined resistance, and configure an operation of the apparatus according to the determined function. | 04-28-2011 |
| 20110095417 | LEADLESS SEMICONDUCTOR DEVICE TERMINAL - This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area. | 04-28-2011 |
| 20110095410 | WAFER LEVEL SEMICONDUCTOR DEVICE CONNECTOR - This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation. | 04-28-2011 |
| 20110089432 | WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer. | 04-21-2011 |
| 20110070699 | 3D SMART POWER MODULE - A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array. | 03-24-2011 |
| 20110068461 | EMBEDDED DIE PACKAGE AND PROCESS FLOW USING A PRE-MOLDED CARRIER - An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings. | 03-24-2011 |
| 20110042717 | INTEGRATED LOW LEAKAGE DIODE - An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on. | 02-24-2011 |
| 20110042013 | METHOD AND APPARATUS FOR BONDED SUBSTRATES - An apparatus for bonding substrates includes a base member having a top surface and a recessed region which is configured for receiving at least a first substrate. The apparatus also has a plurality of support members disposed over the top surface for supporting a second substrate peripherally over the first substrate. Each support member is configured to vary a separation between the first substrate and the second substrate. Moreover, a pressure bar is configured to cause a center portion of the second substrate to contact the first substrate while the support members maintain peripheral separation between the first substrate and the second substrate. In operation, a bonded region between the first and the second substrates is expanded radially from the center portion when the support members are positioned to reduce the separation between the first and the second substrates. | 02-24-2011 |
| 20110031979 | IGNITION SYSTEM OPEN SECONDARY DETECTION - This document discusses, among other things, a system and method for detecting an open secondary condition in a secondary coil of an ignition coil using a control signal received from a control input of a switch configured to control the flow of current to a primary coil of the ignition coil. In an example, the flow of current in the primary coil of the ignition coil can be controlled using an insulated gate bipolar junction transistor (IGBT), and the open secondary condition in the secondary coil of the ignition coil can be detected using a received gate voltage of the IGBT. | 02-10-2011 |
| 20110010750 | NO POP SWITCH - A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold. | 01-13-2011 |
| 20110008935 | SEMICONDUCTOR DIE PACKAGE INCLUDING LEADFRAME WITH DIE ATTACH PAD WITH FOLDED EDGE - A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material. | 01-13-2011 |
| 20110003432 | FLIP CHIP MLP WITH FOLDED HEAT SINK - A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board. | 01-06-2011 |
