Etron Technology Inc. Patent applications |
Patent application number | Title | Published |
20150319425 | IMAGE PROCESS APPARATUS - An image process apparatus includes an image capture device, a filter, a receiver, an input interface, a mixture unit, and an output interface. The image capture device captures an original image and generates a depth map corresponding to the original image, wherein the original image includes at least a first object within a first depth range of the depth map and the other objects not within the first depth range of the depth map. The receiver stores a value of the first depth range and the input interface receives an input image. The filter removes the other objects from the original image and generates a temporary image which includes the first object based on the value of the first depth range. The mixture unit combines the temporary image with the input image, and generates a blending image which is then outputted by the output interface to an external display. | 11-05-2015 |
20140363097 | IMAGE CAPTURE SYSTEM AND OPERATION METHOD THEREOF - An image capture system includes a depth information generation unit, a feature extraction unit, and a merging unit. The depth information generation unit generates a depth information corresponding to at least one object of an original image. The feature extraction unit generates a feature information corresponding to the at least one object of the original image. The merging unit is coupled to the depth information generation unit and the feature extraction unit, and merges the depth information and the feature information into a feature depth map and outputs the feature depth map to an application unit. | 12-11-2014 |
20140355335 | STATIC RANDOM ACCESS MEMORY SYSTEM AND OPERATION METHOD THEREOF - A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to a write command. The output buffer reads read data of addresses of the static random access memory corresponding to a read address signal according to a read command. The multiplexer transmits the write address signal and the read address signal to the static random access memory, and generates the write command and the read command. The shifter shifts the write command to an operation clock behind the read command when the write command and the read command exist simultaneously. | 12-04-2014 |
20140351609 | MEMORY WITH VARIABLE OPERATION VOLTAGE AND THE ADJUSTING METHOD THEREOF - A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage. | 11-27-2014 |
20140218571 | IMAGE PROCESSING METHOD CAPABLE OF REDUCING IMAGE NOISE - An image processing method includes searching a plurality of reference image blocks with pixel patterns identical to a pixel pattern of a main image block in image data; generating a plurality of weight values according to brightness values of pixels of the main image block and brightness values of pixels of the plurality of reference image blocks; summing values of multiplying the plurality of weight values with brightness values of center pixels of the corresponding main image block and the corresponding reference image blocks to generate a sum result; generating a first brightness value according to the sum result and a normalizing factor; and updating the brightness value of the center pixel of the main image block according to the first brightness value. | 08-07-2014 |
20140210438 | MULTI-INPUT LOW DROPOUT REGULATOR - A multi-input low dropout regulator includes an amplifier, a first metal-oxide-semiconductor transistor, and a resistor. The amplifier has a plurality of first input terminals, a second input terminal, and an output terminal. Each first input terminal of the plurality of first input terminals is used for receiving an internal voltage. The first metal-oxide-semiconductor transistor has a first terminal for receiving a first voltage, a second terminal coupled to the output terminal of the amplifier, and a third terminal coupled the second input terminal of the amplifier. The resistor has a first terminal coupled to the third terminal of the first metal-oxide-semiconductor transistor, and a second terminal for receiving a second voltage. The third terminal of the first metal-oxide-semiconductor transistor is further used for coupling to a monitor pad, and the monitor pad is used for outputting the internal voltage. | 07-31-2014 |
20140075251 | CHIP CAPABLE OF IMPROVING TEST COVERAGE OF PADS AND RELATED METHOD THEREOF - A method capable of improving test coverage of chip pads, where the chip includes a control unit, a plurality of pads, and a storage unit, is disclosed. The storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed. | 03-13-2014 |
20140075103 | METHOD CAPABLE OF INCREASING PERFORMANCE OF A MEMORY AND RELATED MEMORY SYSTEM - The present invention discloses a method capable of increasing performance of a memory, where a memory system applied to the method includes a memory and a controller, and a reserved space of the memory is used for storing a logic address/physical block mapping table. The method includes the controller reserving a plurality of physical blocks of the memory as a writing buffer pool; and the controller executing width writing operation or depth writing operation on a plurality of data and the writing buffer pool according to the logic address/physical block mapping table when the plurality of data are written to the memory. The logic address/physical block mapping table includes corresponding relationships between the plurality of physical blocks and a plurality of logic addresses. | 03-13-2014 |
20140050038 | MEMORY DEVICE WITH BI-DIRECTIONAL TRACKING OF TIMING CONSTRAINTS - A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line. | 02-20-2014 |
20140043888 | METHOD OF OPERATING PSRAM AND RELATED MEMORY DEVICE - The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency. | 02-13-2014 |
20130346679 | SYSTEM OF GENERATING SCRAMBLE DATA AND METHOD OF GENERATING SCRAMBLE DATA - A system of generating scramble data includes a linear feedback shift register and a scramble engine. The linear feedback shift register is used for generating a plurality of first scramble values according to an initial value. The scramble engine is coupled to the linear feedback shift register for utilizing at least one bit of a first scramble value of the plurality of first scramble values to execute a first logic operation on other bits of the first scramble value to generate a second scramble value corresponding to the first scramble value. A bit number of the second scramble value is the same as a bit number of the first scramble value. | 12-26-2013 |
20130329947 | IMAGE CAPTURING METHOD FOR IMAGE RECOGNITION AND SYSTEM THEREOF - An image capturing method includes providing at least three image capturing devices arranged along a same direction and an image processor, the at least three image capturing devices capturing at least three first images, determining a target object in the at least three first images, activating a first pair of image capturing devices of the at least three image capturing devices according to shooting angles of the target object in the at least three first images in order to capture a first pair of motion images, and the image processor performing image recognition to the target object of the first pair of motion images. | 12-12-2013 |
20130300474 | DELAY-LOCKED LOOP AND METHOD FOR A DELAY-LOCKED LOOP GENERATING AN APPLICATION CLOCK - A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal. | 11-14-2013 |
20130257495 | LOOP FILTER - A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter. | 10-03-2013 |
20130250711 | MEMORY AND METHOD OF REFRESHING A MEMORY - A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle. | 09-26-2013 |
20130248860 | BUNDLED MEMORY AND MANUFACTURE METHOD FOR A BUNDLED MEMORY WITH AN EXTERNAL INPUT/OUTPUT BUS - A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus. | 09-26-2013 |
20130234766 | INPUT RECEIVER AND OPERATION METHOD THEREOF - An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal. | 09-12-2013 |
20130234694 | INITIAL VOLTAGE GENERATION CIRCUIT AND METHOD OF GENERATING AN INITIAL VOLTAGE - An initial voltage generation circuit includes a reference voltage generator, a reference voltage selector, at least one initial voltage level regulator, and a plurality of stabilization capacitors. The reference voltage generator generates a plurality of reference voltage candidate groups. The reference voltage selector includes a plurality of selection switch groups and a plurality of switch control circuits. Each selection switch group includes a plurality of parallel switches. Each switch control circuit corresponds to a selection switch group for generating a switch signal to control the selection switch group to output a reference voltage candidate of a corresponding reference voltage candidate group. Each initial voltage level regulator generates an inner reference voltage according to a power-up signal, and a stabilization capacitor corresponding to the initial voltage level regulator is used for stabilizing the inner reference voltage. | 09-12-2013 |
20130234684 | IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METHOD OF A LOW DROPOUT REGULATION SYSTEM - An immediate response low dropout regulation system includes a low dropout regulation unit, a tracking voltage generation unit, and a self-driving unit. The low dropout regulation unit is used for generating and outputting an inner output voltage according to a reference voltage. The tracking voltage generation unit is used for generating and outputting a tracking voltage according to the reference voltage. The self-driving unit is coupled to the low dropout regulation unit and the tracking voltage generation unit. When a voltage difference between the tracking voltage and the inner output voltage is greater than a constant times threshold voltage, the self-driving unit provides a compensation current to an output terminal of the low dropout regulation unit. | 09-12-2013 |
20130215112 | Stereoscopic Image Processor, Stereoscopic Image Interaction System, and Stereoscopic Image Displaying Method thereof - A 3D face model is generated by calculating depths on a left image and a right image. An eye-distance of a user is determined according to the 3D face model. A precise stereoscopic digital image of the user is generated by integrating the 3D face model, the eye-distance, and a user digital image processed by human-body rendering and face morphing. The stereoscopic digital image generated by following the user's appearance can be utilized by the user to serve as an avatar, for enhancing entertainments of the user when the user plays an interactive game using the avatar with other players on the Internet. | 08-22-2013 |
20130205148 | USB 3.0 HOST WITH LOW POWER CONSUMPTION AND METHOD FOR REDUCING POWER CONSUMPTION OF A USB 3.0 HOST - A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is coupled to the super speed circuit and the non-super speed circuit for controlling the super speed circuit or the non-super speed circuit to transmit data with a USB peripheral device, and turning-on or turning-off of the super speed circuit and the non-super speed circuit. | 08-08-2013 |
20130173838 | BRIDGE BETWEEN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE AND A UNIVERSAL SERIAL BUS 3.0 DEVICE - A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane. | 07-04-2013 |
20130091315 | HIGH SPEED MEMORY CHIP MODULE AND ELECTRONICS SYSTEM DEVICE WITH A HIGH SPEED MEMORY CHIP MODULE - A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length. | 04-11-2013 |
20130091312 | RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE AND ELECTRONICS SYSTEM DEVICE - A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus. | 04-11-2013 |
20130088907 | TRANSISTOR CIRCUIT LAYOUT STRUCTURE - A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line. | 04-11-2013 |
20130087839 | DYNAMIC MEMORY STRUCTURE - A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal. | 04-11-2013 |
20100327921 | CIRCUIT ARCHITECTURE FOR EFFECTIVE COMPENSATING THE TIME SKEW OF CIRCUIT - A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated. | 12-30-2010 |