Emulex Design & Manufacturing Corporation Patent applications |
Patent application number | Title | Published |
20150089498 | Guest-Based Quality of Service for iSCSI - A system and method for providing access to a Logical Unit mapped to an iSCSI target are described herein. In accordance with this disclosure, an initiator IQN name may be split into a physical IQN name (PIN) and a virtual IQN name (VIN). The VIN may be assigned to a virtual adapter that is created in a guest partition. The PIN may be assigned to a physical adapter (e.g., an iSCSI initiator in a hypervisor). The physical adapter may log into the iSCSI target on behalf of the virtual adapter using the VIN. The physical adapter may receive a list of available logical units associated with the iSCSI target and map the list of available logical units to the virtual adapter. Thereafter, a quality of service between the virtual adapter and the iSCSI target may be monitored. | 03-26-2015 |
20150052280 | METHOD AND SYSTEM FOR COMMUNICATIONS-STACK OFFLOAD TO A HARDWARE CONTROLLER - The current document is directed to offloading communications processing from server computers to hardware controllers, including network interface controllers. In one implementation, the transport channel and zero, one, or more protocol channels immediately overlying the transport channel of a Windows Communication Foundation communications stack are offloaded to a network interface controller. The offloading of communications processing carried out by the methods and systems to which the current document is directed involves minimal supporting development and is configurable, during service-application initialization, by exchange of relatively small amounts of information between an enhanced NIC and the communications stack. | 02-19-2015 |
20140282551 | NETWORK VIRTUALIZATION VIA I/O INTERFACE - Network virtualization can be provided via network I/O interfaces, which may be partially or fully aware of the virtualization. Network virtualization can be reflected in the use of a first header and an additional header(s) for a data frame. A partially-aware transmit example can gather together data frame components, including its additional header(s), via a work queue entry. A fully-aware transmit example can refer to a transmit-side table to gather its additional header(s) and can track the state of its additional header(s) stored in a cache. A partially-aware receive example can handle an additional header(s), e.g., by writing it to host-memory. A fully-aware receive example can determine values from multiple headers (including its additional header(s)) to further determine where to write a data payload to host-memory. The examples can relieve a host's hypervisor from performing all the network virtualization processing. The fully-aware examples can incorporate JOY techniques. | 09-18-2014 |
20140281022 | DATA TRANSMISSION SCHEDULING - A scheduler is disclosed. The scheduler can include a time-wheel structure configured to hold scheduling elements, an enqueuer configured to place a scheduling element on the time-wheel structure, and a delay manager configured to direct the scheduling element through the time-wheel structure and remove the scheduling element from the time-wheel structure. The time-wheel structure can include a plurality of decades that can rotate, and each of the plurality of decades can rotate respectively at one or more different rates of rotation. Multiple scheduling elements can be on the time-wheel structure at least partially during the same time. The scheduling elements can be on different decades or on the same decade. One of the plurality of decades can comprise an entry configured to hold a plurality of scheduling elements. | 09-18-2014 |
20140280716 | DIRECT PUSH OPERATIONS AND GATHER OPERATIONS - When interfacing with a host, a networking device can handle a first data like Bulk Data Send. In response to a first doorbell ring, the networking device can read a first queue entry from a send queue in the host. Based on the first queue entry, the networking device can read the first data from a first memory in the host and then output the read first data. The networking device can also handle a second data like Direct Packet Push. The networking device can store a second data received from the host. In response to a second doorbell ring, the networking device can output the second data. The first data and the second data can be associated with first and second queue entries, both on the same send queue in the host. High-throughput and low-latency can be achieved. Small and large data packets can be accommodated. | 09-18-2014 |
20140280674 | LOW-LATENCY PACKET RECEIVE METHOD FOR NETWORKING DEVICES - When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages. | 09-18-2014 |
20140095741 | Restore PCIe Transaction ID On The Fly - Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again. | 04-03-2014 |
20140089735 | Computer System Input/Output Management - The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers. | 03-27-2014 |
20140082244 | Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes - Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt. | 03-20-2014 |
20130346799 | GENERATION OF SIMULATED ERRORS FOR HIGH-LEVEL SYSTEM VALIDATION - Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test. | 12-26-2013 |
20130340042 | SECURE CONFIGURATION OF AUTHENTICATION SERVERS - Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files. | 12-19-2013 |
20130223281 | LARGE FRAME PATH MTU DISCOVERY AND COMMUNICATION FOR FCOE DEVICES - Embodiments of the invention relate to performing network communications according to an existing protocol by using frames that are larger than those usually allowed by the existing protocol. Thus, embodiments of the present invention provide for an extension of the existing protocol which allows for the use of larger frames. Embodiments provide for use of various negotiation and initialization mechanisms of the existing protocol with additional modifications to allow for the negotiation of the use of larger frames. Some embodiments ensure that the negotiations are performed in such a manner that devices that feature the improvements of the present invention can communicate with devices that do not feature these improvements. | 08-29-2013 |
20130195104 | POWER MANAGEMENT FOR INPUT/OUTPUT DEVICES - A method for managing power consumption by a network device is disclosed. The network device includes first and second ports, each of the first and second ports identified by a unique identifier and adapted to handle separate network traffic. The method includes verifying that the first and the second ports are connected to a common network end node; shutting off a link between the first port and the network end node; obtaining the unique identifier of the first port; creating, on the second port, a virtual port in response to the unique identifier of the first port; discovering the virtual port on the network device; and redirecting traffic formerly routed through the link through the virtual port. | 08-01-2013 |
20130107892 | METHOD FOR PARSING NETWORK PACKETS HAVING FUTURE DEFINED TAGS | 05-02-2013 |
20130101298 | OUT OF BAND DATA TRANSFER OVER OPTICAL CONNECTIONS - Provided herein are various schemes for transmitting out of band (OOB) signals over optical connections that may not support the transmission of such signals. One scheme may involve converting the OOB signals to different types of signals that are supported by the optical connection, while another scheme may utilize a separate parallel connection that supports the transmission of out of band signals in order to extend the optical connection. Yet another scheme modulates the reference clock of the original (in-band) signal to transmit and receive the OOB information. | 04-25-2013 |
20120287944 | RoCE PACKET SEQUENCE ACCELERATION - Disclosed herein are methods and apparatus for accelerating RoCE packet sequence transmission and reducing processing latency in received RoCE packets. Under the disclosed method, the RoCE protocol stack and RDMA verbs are implemented partially in the host software and partially in the adapter hardware, thereby providing a better balance between simplifying the adapter configuration and maximizing the host processing efficiency. Particularly, the adapter implemented with partial RoCE offload is able to perform a few major functionalities under the RoCE protocol, such as offloading a complete RoCE packet sequence for transmission, building individual packets out of the RoCE packet sequence and performing Invariant CRC calculation, insertion, validation and removal thereof. | 11-15-2012 |
20110293282 | OUT OF BAND DATA TRANSFER OVER OPTICAL CONNECTIONS - Provided herein are various schemes for transmitting out of band (OOB) signals over optical connections that may not support the transmission of such signals. One scheme may involve converting the OOB signals to different types of signals that are supported by the optical connection, while another scheme may utilize a separate parallel connection that supports the transmission of out of band signals in order to extend the optical connection. Yet another scheme modulates the reference clock of the original (in-band) signal to transmit and receive the OOB information. | 12-01-2011 |
20110258352 | Inline PCI-IOV Adapter - A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device. | 10-20-2011 |
20110239014 | POWER MANAGEMENT FOR INPUT/OUTPUT DEVICES - A method for managing power consumption by a network device is disclosed. The network device includes first and second ports, each of the first and second ports identified by a unique identifier and adapted to handle separate network traffic. The method includes verifying that the first and the second ports are connected to a common network end node; shutting off a link between the first port and the network end node; obtaining the unique identifier of the first port; creating, on the second port, a virtual port in response to the unique identifier of the first port; discovering the virtual port on the network device; and redirecting traffic formerly routed through the link through the virtual port. | 09-29-2011 |
20110202623 | ACCELERATED SOCKETS - Disclosed herein is an improved method of using sockets in connection with TCP over certain local networks, such as the enhanced Ethernet. In particular, an accelerated socket protocol is provided to enhance data communications between different host computer systems connected to an enhanced Ethernet network. Under the accelerated socket protocol, a host computer, while sending a number of data packets, is able to indicate a particular data packet is a last ready data packet out of all packets ready to be sent by setting a PUSH bit in that particular data packet, which triggers an automatic acknowledgement message that confirms receipt of data from the receiver. In addition, while receiving data packets, the host computer can advertise an effective window that corresponds to the actually available receiving space in the host computer. | 08-18-2011 |
20110107002 | SAS Expander-Based SAS/SATA Bridging - Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process. | 05-05-2011 |
20110087814 | Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes - Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt. | 04-14-2011 |
20100306635 | Method for Verifying Correct Encryption Key Utilization - A method for sending encrypted data in response to a request for an I/O operation. The method includes the steps of requesting a data encryption key, the request including one or more identifiers unique to the I/O operation; receiving a data encryption key attached with a first key use fingerprint, independently generating a second key use fingerprint in response to the one or more identifiers; comparing the first and the second key use fingerprints; and if the first key use fingerprint matches the second key use fingerprint, using the data encryption key to encrypt the data to be sent. In one embodiment, the one or more identifiers include at least one of a target identifier, a LUN identifier, and a LBA range identifier. | 12-02-2010 |
20100235678 | System and Method for Data Protection Against Power Failure During Sector Remapping - Disclosed herein is a technique to protect sector remapped boundary data from corruption due to catastrophic errors such as loss of power in storage disks including SATA (Serial ATA) drives. Specially, one method is provided for protecting the boundary sector data from power failure through a data recovery mechanism, namely, a boundary sector table in which the boundary sectors are pre-stored in case any power failure or loss occurs during the sector remapped write operations. In connection with the boundary sector table stored in a reserved region of the storage disk, a boundary sector information index is provided in a bridge coupled to the disk, which serves as a key to identify and retrieve the needed boundary sector data from the table for corrupted data recovery. | 09-16-2010 |
20100232049 | System and Method for Sector Remapping - Disclosed herein is an improved sector remapping method that maps logical sectors into physical sectors in storage disks such as SATA (Serial ATA) drives without reducing either storage capacity or I/O performance efficiency. Under this sector remapping method, logical sectors of data can be written into the physical sectors of a storage device through control frames having padded data or information associated with the padded data, as well as data frames having real data to be stored. With the padded data to be added to the real data, the frames provide multiple physical sectors to be transmitted into the storage device in a single write operation. The sector remapping method can be implemented in a storage bridge coupled to a storage device such as SATA drives. | 09-16-2010 |
20100115132 | ADDRESS IDENTIFIER SCALING IN CONVERGED NETWORKS - Embodiments of the present invention allow for address scaling of existing addresses in a FC, FCoE, CEE or other type of network. More specifically, subaddresses can be used in conjunction with existing addresses, so that a combination of a subaddress and existing address can identify an addressable entity. Thus, multiple entities can be share a single existing address and be distinguished among each other by way of their respective subaddresses. Some embodiments of the invention allow for use of the inventive subaddressing scheme in conjunction with devices or network elements (e.g., gateways, switches, etc.) that may not be subaddressing aware. Further embodiments allow for the multiple distinct devices to communicate with a single Fibre Channel switching element through a single port by using N_Port_ID Virtualization. | 05-06-2010 |
20100064072 | Dynamically Adjustable Arbitration Scheme - A network arbitration scheme is disclosed that manages device access fairness by selectively and dynamically increasing a requestor queue's likelihood of being serviced. A requestor queue increases its service priority by duplicating a request entry onto a set of priority rings maintained by arbitration hardware in a host bus adapter. Duplication occurs when (1) a requestor's queue fill count (the number of descriptors stored in the queue) exceeds a watermark level or (2) a requestor's queue timer times out. In the case of time-out, the requester in the lower priority ring will duplicate itself in the higher priority ring. Because the arbitration hardware services requesters using a round robin selection scheme, the likelihood of a requestor queue being serviced increases as the number of its duplicate request entries on a priority ring increases. Upon being serviced, the requester is able to perform the requested action. | 03-11-2010 |
20100061383 | Combined FCOE Network Device - Embodiments of the present invention are related to a device and a method for more efficiently processing Ethernet communications that include FCOE communications. In some embodiments the device is a single device including a combination of an aggregator, a filter and a gateway. Such a combination can be more practical, affordable and efficient than the usual arrangement of a several separate devices. In other embodiments, the device of the present invention can be a combination of a switch and a gateway. In yet other embodiments other types of devices can be used. More generally, embodiments of the present invention can apply to a device or method for processing communications involving a set of two network protocols (first and second protocols) as well as a third protocol, the third protocol being compatible with the first protocol and used to define how to tunnel the second protocol over the first protocol. | 03-11-2010 |
20100023748 | SELF CHECKING ENCRYPTION AND DECRYPTION BASED ON STATISTICAL SAMPLING - The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data. | 01-28-2010 |
20100014526 | Hardware Switch for Hypervisors and Blade Servers - A hardware switch for use with hypervisors and blade servers is disclosed. The hardware switch enables switching to occur between different guest OSs running in the same server, or between different servers in a multi-root IOV system, or between different guest OSs running in the same server in single-root IOV systems. Whether embedded in a host bus adapter (HBA), converged network adapter (CNA), network interface card (NIC) or other similar device, the hardware switch can provide fast switching with access to and sharing of at least one external network port such as a Fibre Channel (FC) port, 10 Gigabit Ethernet (10 GbE) port, FC over Ethernet (FCOE) port, or other similar port. The hardware switch can be utilized when no hypervisor is present or when one or more servers have hypervisors, because it allows for switching (e.g. Ethernet switching) between the OSs on a single hypervisor. | 01-21-2010 |
20090307473 | METHOD FOR ADOPTING SEQUENTIAL PROCESSING FROM A PARALLEL PROCESSING ARCHITECTURE - Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order. | 12-10-2009 |
20090287732 | SECURE CONFIGURATION OF AUTHENTICATION SERVERS - Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files. | 11-19-2009 |
20090259749 | COMPUTER SYSTEM INPUT/OUTPUT MANAGEMENT - The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers. | 10-15-2009 |
20090240986 | GENERATION OF SIMULATED ERRORS FOR HIGH-LEVEL SYSTEM VALIDATION - Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test. | 09-24-2009 |
20090172706 | SAS EXPANDER BASED PERSISTENT CONNECTIONS - Embodiments of the present invention provide for creating and using persistent connections in SAS networks. A persistent connection may be a connection that persists for longer than the usual SAS connection. More specifically, it is a connection that is not subject to periodic tear downs by SAS devices according to existing SAS protocols (such as, by using CLOSE or BREAK primitives). Instead, persistent connections may be removable by a link reset. Persistent connections may be used in situations in which the overhead associated with the usual tear down and re-establishment of connections in a SAS network may be considered too high in comparison with its intended benefits. Persistent connections may also be used to provide virtual direct attachment between two different SAS connected devices or between a SAS connected device and an expander. | 07-02-2009 |
20090172206 | DETECTION AND CONFIGURATION OF SAS/SATA CONNECTION - Given the different configurations for SAS and SATA Host and Target Ports, embodiments of the present invention automatically detect the configuration of SATA and SAS Phys when any device is inserted into a port enclosure and properly configure the connection regardless of the Phy configuration of the connected device. When a device is connected to the system, the port listens for either a SATA or SAS OOB signal to determine if the receive pin of the port is properly connected to the transmit signal of the attached device. By switching the configuration periodically and listening for the OOB signal, the port can determine which configuration is proper. Once a signal is detected, the port can properly configure the connection and continue with the SATA or SAS insertion algorithm. A user may alternatively choose which configuration to use and bypass the automatic detection and configuration. | 07-02-2009 |
20090168654 | SNOOPING IN SAS EXPANDER NETWORKS - Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer. | 07-02-2009 |
20090164630 | NETWORK ADAPTER BASED ZONING ENFORCEMENT - Embodiments of the present invention are directed to enforcing zoning at a network adapter of an end point device. Thus, a network adapter can monitor the communications that are sent and/or received by the adapter and discard communications that are prohibited based on the zoning rules applicable to the adapter. In some embodiments, zoning configuration information can be defined and stored at a central entity and sent to the various network adapters. Alternatively, or in addition, each network adapter can also check outgoing communications to ensure that they include a proper source address. More specifically, outgoing communications may be checked to ensure that their source address is the address (or one of the addresses) that are associated with the network adapter. This can be used to detect and/or prevent malfunctions and/or intentional tampering or hacking. | 06-25-2009 |
20090161692 | HIGH PERFORMANCE ETHERNET NETWORKING UTILIZING EXISTING FIBRE CHANNEL FABRIC HBA TECHNOLOGY - This is directed to providing Fibre Channel over Ethernet communication. For example a Fibre Channel over Ethernet (FCoE) enabled device (such as a computer) may include a Fibre Channel over Ethernet Adapter (FCoEA). The FCoEA may include an HBA module. The HBA module may be configured to communicate over the Fibre Channel protocol. The FCoE enabled device may process and encapsulate the HBA module's communication in order to send them over an Ethernet network instead. The FCoE enabled device may process communications directed to various Fibre Channel fabric services by utilizing existing Ethernet services, such as an iSNS server. Thus, the FCoE enabled device can emulate a Fibre Channel network for the HBA module using the Ethernet network and one or more Existing Ethernet services/servers. | 06-25-2009 |
20090157918 | EFFICIENT PROCESSING OF GROUPS OF HOST ACCESS REQUESTS THAT MAY INCLUDE ZERO LENGTH REQUESTS - This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests. | 06-18-2009 |
20090150643 | SAS reference Phys for virtualization and traffic isolation - Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is created within the expander. Next, a route table is generated that includes an entry for each of the SAS addresses being virtualized, each entry associated with one or more of the physical or virtual Phy through which the SAS address is being virtualized. With the route table so established, requests for a virtualized SAS address are routed to a particular one of the one or more physical or virtual Phy associated with the virtualized SAS address in the route table. | 06-11-2009 |
20090125655 | ENABLING SAS EXPANDER LOOPS FOR INCREASED FAIRNESS AND PERFORMANCE - The use of loops in SAS networks is enabled by designating ports connected to loop connections as table loop ports (TLPs). Under normal operating conditions, each TLP is blocked from receiving BCNs, appears to the expander to have nothing connected to it, and is made invisible to initiators. The loop connection and TLPs may be enabled and used to access devices when a problem is detected. In particular, the TLP will now appear in a list of destination ports within the expander to which a BCN should be propagated. In addition, during a subsequent self-configuration, the TLP is allowed to populate its route table with devices accessible through it, and the existence of the TLP is also reported back to initiators. After re-discovery is complete, communications between the initiator and a target can resume, with traffic re-routed through the TLPs as needed, bypassing the failure point. | 05-14-2009 |
20090041046 | High performance ethernet netrworking utilizing existing fibre channel arbitrated loop HBA technology - Embodiments of the present invention are directed to a device which may be used for communication through an Ethernet network. The device may comprise two modules. A first module may be based on an existing Fibre Channel arbitrated loop HBA technology. The second module may be configured to provide a virtual Fibre Channel arbitrated loop network for the first module utilizing the Ethernet network. In other words the second module may process communications generated by the first module as well as incoming communications from the Ethernet network in order to make it appear to the first module that it is communicating with an actual Fibre Channel Arbitrated Loop network (whereas it is actually communicating through an Ethernet network). Thus, existing Fibre Channel technology can be used for the first module and the overall design cost of the device can be reduced. | 02-12-2009 |
20090007155 | Expander-based solution to the dynamic STP address problem - The persistent binding of STP SAS addresses to SATA devices is disclosed so that SATA devices can be moved to different insertion points (ports) within a SAS expander and still properly receive I/O requests. When a SATA device is inserted into the SAS expander, it is interrogated to obtain information about the attached device. This information may be combined using a hashing function to obtain a unique ID for the SATA device. A table can be used to assign a STP SAS address to the Phy connected to the device based in the unique ID. In this manner, the same STP SAS address will be assigned to the Phy connected to a particular SATA device, regardless of where the device is connected to the SAS expander. | 01-01-2009 |
20090007154 | SAS expander-side optimization for the re-discovery process - A simplification of the re-discovery process for initiators due to changes in the network is disclosed. If an initiator subscribes to change reports from a SAS expander, when that SAS expander detects a change in the network, it sends an SMP command back to the initiator, indicating the specific change in the network. Initiator BCN management and re-discovery of the entire network is therefore avoided. | 01-01-2009 |
20090006761 | Cache pollution avoidance - Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache. | 01-01-2009 |
20090006697 | Label switched routing in SAS expanders - The attaching of labels to an OPEN frame and applying label switched routing to SAS expanders is disclosed to eliminate the need for large routing tables in SAS networks. A label stack is inserted into the OPEN frame by the initiator, prior to the OPEN frame being transmitted. Each label contains the egress port for a SAS expander in the transmit path. Each SAS expander to be participating in the connection reads the labels to determine the egress port to connect to and through which data is to be sent. The SAS expander marks its label invalid or discards it and forwards the OPEN frame to the egress port where the next SAS expander will look for the first valid label. The process repeats until the OPEN frame reaches the edge device, at which time all labels are discarded and the OPEN frame is forwarded to the end device. | 01-01-2009 |
20090003361 | Multi-protocol controller that supports PCle, SAS and enhanced ethernet - SAS over Enhanced Ethernet (SOE) controllers that integrate SAS and Enhanced Ethernet to perform a conversion between SAS and Enhanced Ethernet are disclosed. A central intelligence block can be employed to perform the mapping between SAS and Enhanced Ethernet. The SOE controller can include one or more Enhanced Ethernet Interfaces, one or more SAS interfaces, and a PCIe interface. The SOE controller can direct the I/O requests presented on one interface to another interface after performing some basic operations on the I/O requests, including protocol conversion. The SOE controller can include an intelligence mechanism for identifying the appropriate output ports for routing the I/O requests and redirecting them accordingly. In the case of routing I/O requests over Enhanced Ethernet, the SOE controller can perform SAS protocol conversion to map outgoing I/O requests into Enhanced Ethernet frames suitable for transmission over the Enhanced Ethernet network. | 01-01-2009 |
20090003197 | Isolation of unverified devices in a SAS expander - When a new device is attached to a SAS expander, malfunctioning devices can cause many BCNs to be generated, which in turn can cause excessive re-discovery processes to be performed by initiators in a storage network. Therefore, the isolation of devices from the storage network until they can be validated as healthy is disclosed. Any device malfunctions during this time of isolation do not cause BCNs to be generated and do not cause re-discovery processes to be performed. Once the device is validated (via a port-test-before-insertion approach) and found to be healthy, the fabric is notified via a BCN, and the device can be made visible to the network. | 01-01-2009 |
20090001960 | Systems and methods for ASIC power consumption reduction - Embodiments of the present invention are directed to dynamically measuring the speed of a circuit and modifying the operating voltage of the circuit based on the measured speed, in order to minimize the power being used while still ensuring proper operation of the circuit. Consequently, circuits of higher inherent speeds may have their voltages decreased (thus decreasing their actual speeds), while circuits of lower speeds may have their voltages increased, or kept the same. Thus, the resulting speeds of all circuits may be kept within a limited range to ensure proper operation. In addition, the power dissipated of circuits of higher speeds may be decreased. | 01-01-2009 |
20080307122 | Autonomous mapping of protected data streams to Fibre channel frames - A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network. | 12-11-2008 |
20080294296 | Chip overheat protection - Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log. | 11-27-2008 |