| Elpida Memory, Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20150228710 | Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 08-13-2015 |
| 20150149717 | PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY - Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2 | 05-28-2015 |
| 20150087130 | DRAM MIM Capacitor Using Non-Noble Electrodes - A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material. | 03-26-2015 |
| 20140246780 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PATTERN - A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern. | 09-04-2014 |
| 20140241059 | METHOD AND DEVICE FOR STORING AND READING RELIABLE INFORMATION IN A NAND ARRAY - A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets. | 08-28-2014 |
| 20140233335 | SEMICONDUCTOR DEVICES - A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of the plurality of memory chips, output terminal 101 being connected to one end of the first transmission line, and a first termination resistor being connected to another end of the first transmission line. | 08-21-2014 |
| 20140233334 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge. | 08-21-2014 |
| 20140232438 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal. | 08-21-2014 |
| 20140231959 | SEMICONDUCTOR DEVICE HAVING STORAGE ELECTRODE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first storage electrode, a second storage electrode that is arranged above the first storage electrode, a first landing pad that is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode, the first landing pad connecting the first storage electrode and the second storage electrode, the first landing pad having a first landing surface, the first landing surface being larger than the bottom surface of the second storage electrode, and the second storage electrode being placed on the first landing surface, a capacitive insulating film that is laminated on the first and second storage electrodes and on an outer circumferential surface of the first landing pad, and a plate electrode that contacts the capacitive insulating film. | 08-21-2014 |
| 20140217560 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion. | 08-07-2014 |
| 20140211545 | SEMICONDUCTOR DEVICE - A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations. | 07-31-2014 |
| 20140204692 | SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY - A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines. | 07-24-2014 |
| 20140197495 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant. | 07-17-2014 |
| 20140191416 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. | 07-10-2014 |
| 20140187018 | Methods for Reproducible Flash Layer Deposition - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands. | 07-03-2014 |
| 20140187015 | Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer. | 07-03-2014 |
| 20140185350 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal. | 07-03-2014 |
| 20140184284 | SEMICONDUCTOR DEVICE - A method for synchronizing an output clock signal with an input clock signal in a delay locked loop. A first count values decreasing the number of bypassed elements in a differential delay line until an edge of the output clock signal is delayed relative to an edge of the input clock signal or the first count value reaches a first count final value if the first count value reaches the first count final value, a second count value is adjusting to decrease the number of bypassed elements in a single-ended delay line until the edge of the output clock signal is delayed relative to the edge of the input clock signal. A third count value is adjusted to decrease the delay of an interpolator until the edge of the output clock signal is no longer delayed with respect to the edge of the input clock signal. | 07-03-2014 |
| 20140183705 | SEMICONDUCTOR DEVICE WITH THROUGH SILICON VIA AND ALIGNMENT MARK - A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor. | 07-03-2014 |
| 20140183704 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a semiconductor substrate having first and second surfaces and a peripheral edge, the first and second surfaces being opposite to each other, includes forming an inter-layer insulator having a guard ring on the first surface, adjacent to the peripheral edge, forming a first groove on the second surface and adjacent to the peripheral edge, and forming a through electrode that penetrates the second surface to the inter-layer insulator near the first groove and on an opposite side of the groove with respect to the peripheral edge. | 07-03-2014 |
| 20140183695 | Methods for Reproducible Flash Layer Deposition - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands. | 07-03-2014 |
| 20140177339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number. | 06-26-2014 |
| 20140173173 | METHOD, DEVICE, AND SYSTEM INCLUDING CONFIGURABLE BIT-PER-CELL CAPABILITY - A method includes providing a partition command to a device that includes a memory array including a plurality of memory cells. In response to the providing of the partition command, the memory cells of the memory array are partitioned to select a portion of the memory array. In response to the providing of the partition command, one of bit numbers that are to be stored in one memory cell is selected, so that each of the memory cells included in the selected portion stores data with the selected one of the bit numbers. | 06-19-2014 |
| 20140170833 | Methods to Improve Leakage of High K Materials - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor dopant incorporated within the dielectric layer. The oxygen donor dopants may be incorporated within the dielectric layer during the formation of the dielectric layer. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current. | 06-19-2014 |
| 20140169111 | DEVICE INCLUDING A PLURALITY OF MEMORY BANKS AND A PIPELINE CONTROL CIRCUIT CONFIGURED TO EXECUTE A COMMAND ON THE PLURALITY OF MEMORY BANKS - A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot. | 06-19-2014 |
| 20140169057 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM HAVING THE SAME - A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address. | 06-19-2014 |
| 20140167221 | METHODS TO IMPROVE LEAKAGE OF HIGH K MATERIALS - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current. | 06-19-2014 |
| 20140167125 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 06-19-2014 |
| 20140152380 | SEMICONDUCTOR DEVICE THAT CAN CANCEL NOISE IN BIAS LINE TO WHICH BIAS CURRENT FLOWS - Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line. | 06-05-2014 |
| 20140151791 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film. | 06-05-2014 |
| 20140140125 | SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof. | 05-22-2014 |
| 20140132316 | SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes. | 05-15-2014 |
| 20140117969 | CONSTANT CURRENT SOURCE CIRCUIT - A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor. | 05-01-2014 |
| 20140117440 | SEMICONDUCTOR DEVICE WITH IMPURITY REGION WITH INCREASED CONTACT AREA - A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region. | 05-01-2014 |
| 20140112047 | SEMICONDUCTOR DEVICE HAVING DATA BUS - A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers. | 04-24-2014 |
| 20140111271 | SEMICONDUCTOR DEVICE HAVING BOOSTING CIRCUIT - A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit. | 04-24-2014 |
| 20140103542 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 04-17-2014 |
| 20140103483 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug. | 04-17-2014 |
| 20140103442 | SEMICONDUCTOR DEVICE, METHOD OF FORMING SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region. | 04-17-2014 |
| 20140094000 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array. | 04-03-2014 |
| 20140092691 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line. | 04-03-2014 |
| 20140092679 | MEMORY DEVICE AND WRITING METHOD THEREOF - A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability. | 04-03-2014 |
| 20140091479 | SEMICONDUCTOR DEVICE WITH STACKED SEMICONDUCTOR CHIPS - A semiconductor chip | 04-03-2014 |
| 20140089723 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 03-27-2014 |
| 20140087518 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied. | 03-27-2014 |
| 20140085997 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line. | 03-27-2014 |
| 20140085964 | SEMICONDUCTOR STORAGE DEVICE - A control circuit controls memory operations such that, in a first rewriting operation in which a resistance state of a variable resistance element is changed from a first state to a second state, a first voltage pulse is applied to both terminals of a memory cell while limiting the amount of current flowing through the variable resistance element to a value smaller than or equal to a certain small amount of current, in a second rewriting operation in which the resistance state of the variable resistance element is changed from the second state to the first state, a second voltage pulse is applied to both terminals of the memory cell, and, in a reading operation in which the resistance state stored in the variable resistance element is read, a third voltage pulse is applied to both terminals of the memory cell. | 03-27-2014 |
| 20140080284 | High Temperature ALD Process of Metal Oxide for DRAM Applications - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers. | 03-20-2014 |
| 20140080282 | Leakage reduction in DRAM MIM capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 03-20-2014 |
| 20140078852 | SEMICONDUCTOR DEVICE INCLUDING LATENCY COUNTER - For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density. | 03-20-2014 |
| 20140078843 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. | 03-20-2014 |
| 20140078805 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTORS - A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element. | 03-20-2014 |
| 20140073127 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure. | 03-13-2014 |
| 20140071760 | SYSTEMS AND METHODS FOR ERASING CHARGE-TRAP FLASH MEMORY - FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors. | 03-13-2014 |
| 20140063992 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells, a second bit line, a first voltage line, a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors. | 03-06-2014 |
| 20140056086 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF ADJUSTING THE SAME AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells. | 02-27-2014 |
| 20140056063 | SEMICONDUCTOR DEVICE HAVING CURRENT CHANGE MEMORY CELL - A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line, the performing including providing a gate of the first transistor with a first voltage, providing the sensing line with a second voltage, and providing the bit line with a third voltage, the third voltage being independent from the second voltage. | 02-27-2014 |
| 20140050004 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES - Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell. | 02-20-2014 |
| 20140048860 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars. | 02-20-2014 |
| 20140043885 | SEMICONDUCTOR DEVICE - In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. | 02-13-2014 |
| 20140042617 | SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE - Disclosed herein is a semiconductor device that includes: a semiconductor substrate including first and second surfaces opposed to each other, a plurality of penetration electrodes each penetrating between the first and second surfaces and a plurality of first metal films each surrounding an associated one of the penetration electrodes with an intervention of an insulating film; and a wiring structure formed on a side of the first surface of the semiconductor substrate, the wiring structure including a plurality of wirings each electrically connected to an associated one of the penetration electrodes. | 02-13-2014 |
| 20140042589 | SEMICONDUCTOR DEVICE - The semiconductor device | 02-13-2014 |
| 20140042555 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar. | 02-13-2014 |
| 20140038424 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface. | 02-06-2014 |
| 20140038411 | MANUFACTURING METHOD OF DEVICE - A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films. | 02-06-2014 |
| 20140038387 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions. | 02-06-2014 |
| 20140038375 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a vertical MOS transistor, includes forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench, forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation, etching the semiconductor substrate in the region subjected to the shallow trench isolation with the insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor, implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation, and forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor. | 02-06-2014 |
| 20140036607 | SEMICONDUCTOR MEMORY DEVICE AND READ WAIT TIME ADJUSTMENT METHOD THEREOF, MEMORY SYSTEM, AND SEMICONDUCTOR DEVICE - A system including a controller and a memory device interconnected to the controller; the controller includes a set of first terminals that is connected to the memory device through a set of first signal lines, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the memory device to cause the memory device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state. The control circuit is further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the memory device. | 02-06-2014 |
| 20140036606 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines. | 02-06-2014 |
| 20140036573 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells. | 02-06-2014 |
| 20140036244 | METHOD OF EXPOSING A SEMICONDUCTOR WAFER AND EXPOSURE APPARATUS - An exposure apparatus includes an autofocus scan processor configured to generate a detection signal indicating a defocused portion of a resist film over a semiconductor substrate, an exposure scan processor configured to perform an exposure process for the resist film, and a controller configured to feed back the detection signal from the autofocus scan processor to the exposure scan processor. | 02-06-2014 |
| 20140035639 | SEMICONDUCTOR DEVICE GENERATING INTERNAL CLOCK SIGNAL HAVING HIGHER FREQUENCY THAN THAT OF INPUT CLOCK SIGNAL - Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line. | 02-06-2014 |
| 20140035166 | SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
| 20140035161 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
| 20140030865 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER CAPACITOR ELECTRODE - To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode. | 01-30-2014 |
| 20140029370 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION METHOD - A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, | 01-30-2014 |
| 20140028280 | SEMICONDUCTOR DEVICE - A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at first node; third and fourth transistors of second conductivity type coupled in series between first and second lines and coupled to each other at second node; power supply node coupled in common to first and second nodes; fifth transistor of first conductivity type coupled between first and second signal lines; and sixth transistor of second conductivity type coupled between first and second signal lines, wherein each of first, second and fifth transistors is configured to receive first control signal at gate electrode thereof, each of the third and fourth transistors is configured to receive second control signal at gate electrode thereof, and sixth transistor is configured to receive third control signal at gate electrode thereof. | 01-30-2014 |
| 20140022857 | SEMICONDUCTOR DEVICE - A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. | 01-23-2014 |
| 20140021994 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 01-23-2014 |
| 20140016427 | SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS - A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command. | 01-16-2014 |
| 20140016388 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. | 01-16-2014 |
| 20140015022 | SEMICONDUCTOR DEVICE HAVING RING-SHAPED GATE ELECTRODE, DESIGN APPARATUS, AND PROGRAM - A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode. | 01-16-2014 |
| 20140010034 | SEMICONDUCTOR DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING SAME, AND CONTROLLER FOR CONTROLLING SEMICONDUCTOR DEVICE - A system includes a control chip and a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals. | 01-09-2014 |
| 20140008535 | METHOD AND SYSTEM OF EVALUATING DISTRIBUTION OF LATTICE STRAIN ON CRYSTAL MATERIAL - A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample. | 01-09-2014 |
| 20140003116 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL STRUCTURED BIT LINES | 01-02-2014 |
| 20140002144 | SEMICONDUCTOR DEVICE WITH BUFFER AND REPLICA CIRCUITS | 01-02-2014 |
| 20140001639 | SEMICONDUCTOR DEVICE HAVING SILICON INTERPOSER ON WHICH SEMICONDUCTOR CHIP IS MOUNTED | 01-02-2014 |
| 20140001030 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20130344674 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A LAMINATED STRUCTURE COMPRISING A BORON-DOPED SILICON GERMANIUM FILM AND A METAL FILM - A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film. | 12-26-2013 |
| 20130344665 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds. | 12-26-2013 |
| 20130342238 | SEMICONDUCTOR DEVICE INCLUDING TRI-STATE CIRCUIT - Disclosed herein is a device that includes first and second logic circuits driving first and second output nodes, respectively. The first logic circuit includes first and second transistors that are coupled in series between the first output node and a power line, in which the first transistor is controlled to change between a conductive state and a non-conductive state and the second transistor is controlled to keep a conductive state. The second gate circuit includes third and fourth transistors that are coupled in series between the second output node and the power line, in which each of the third and fourth transistors is controlled to change between a conductive state and a non-conductive state. | 12-26-2013 |
| 20130336077 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME - A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array | 12-19-2013 |
| 20130330903 | MANUFACTURABLE HIGH-K DRAM MIM CAPACITOR STRUCTURE - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material. | 12-12-2013 |
| 20130330902 | ENHANCED NON-NOBLE ELECTRODE LAYERS FOR DRAM CAPACITOR CELL - A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode materials are conductive molybdenum oxide. | 12-12-2013 |
| 20130329481 | SEMICONDUCTOR SYSTEM - A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-12-2013 |
| 20130328590 | SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR - A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level. | 12-12-2013 |
| 20130328589 | SEMICONDUCTOR DEVICE BASED ON POWER GATING IN MULTILEVEL WIRING STRUCTURE - A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively. | 12-12-2013 |
| 20130328188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate including first and second surfaces, a first insulating film including third and fourth surfaces, the fourth surface being in contact with the first surface, and an electrode elongated to penetrate the substrate and the first insulating film, the electrode including a first portion and a second portion. The first portion includes first and second end parts and a center part sandwiched between the first and second end part. The first and second end parts of the first portion are smaller in diameter than at least a portion of the center part of the first portion. The second portion is located between the first portion and the third surface, and includes a third end part exposed from the third surface and a fourth end part connected to the first end part of the first portion. | 12-12-2013 |
| 20130328160 | SEMICONDUCTOR DEVICE - Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant. | 12-12-2013 |
| 20130328046 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement. | 12-12-2013 |
| 20130320507 | SEMICONDUCTOR DEVICE HAVING PLURAL PATTERNS EXTENDING IN THE SAME DIRECTION - A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace. | 12-05-2013 |
| 20130315018 | SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 11-28-2013 |
| 20130313690 | SEMICONDUCTOR DEVICE - Disclosed herein is a device that includes a semiconductor substrate, a plurality of first electrodes formed over the semiconductor substrate and arranged in line in a first direction, a plurality of second electrodes formed over the semiconductor substrate and arranged in line in the first direction on a left side of an associated one of the first electrodes, and a plurality of third electrodes formed over the semiconductor substrate and arranged in line in the first direction on a right side of an associated one of the first electrodes. Each of the first electrodes is configured to be supplied with a corresponding electrical potential, whereas each of the second and third electrodes is in an electrical floating state serving as a dummy electrode. | 11-28-2013 |
| 20130313689 | SEMICONDUCTOR DEVICE - In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material. | 11-28-2013 |
| 20130308403 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT - Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. | 11-21-2013 |
| 20130307622 | DIFFERENTIAL AMPLIFIER CIRCUIT HAVING PLURAL CURRENT MIRROR CIRCUITS - Disclosed herein is a differential amplifier circuit that includes: first and second transistors coupled to form a differential circuit; a first current mirror circuit generating first and second currents in response to a third current flowing through the first transistor; and a second current mirror circuit generating a fourth current in response to a fifth input current. A sum of the second and fourth currents flowing through the second transistor. | 11-21-2013 |
| 20130307056 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a semiconductor substrate including first, second and third surfaces, the second surface being placed above the first surface, the third surface having first and second edges connecting to the first and second surfaces, respectively; an isolation region including an insulator and formed on the first and third surfaces; an active region including the second surface and fenced with the insulator of the isolation region; and first and second semiconductor pillars each protruding upwardly from the second surface in the active region, wherein the first semiconductor pillar is thinner than the second semiconductor pillar. | 11-21-2013 |
| 20130301361 | ROW DRIVER ARCHITECTURE - Devices and circuits for row driver in a memory device. The proposed row driver circuit architectures may reduce size of the row driver circuitry and enhance the row driver circuit's reliability. Specifically, the proposed embodiments of the row driver may reduce the required sizing of the boosting capacitor or alternatively eliminate the boosting capacitor entirely. Further, the embodiments of the row driver may reduce the risk of charge-leakage on K-nodes, enhancing the row driver's reliability in driving the x-path of the memory array. | 11-14-2013 |
| 20130301330 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. | 11-14-2013 |
| 20130294176 | CONTROL DEVICE - A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other. | 11-07-2013 |
| 20130294170 | SWITCH AND SEMICONDUCTOR DEVICE INCLUDING THE SWITCH - A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor. | 11-07-2013 |
| 20130294137 | SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED - Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state. | 11-07-2013 |
| 20130286715 | SEMICONDUCTOR DEVICE WITH MEMORY DEVICE - A memory mat ( | 10-31-2013 |
| 20130285258 | SEMICONDUCTOR DEVICE HAVING MESH-PATTERN WIRINGS - Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position. | 10-31-2013 |
| 20130285202 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including a capacitor which includes a cylindrical or columnar lower electrode, a support film in contact with the upper portion of the lower electrode for supporting the lower electrode, a dielectric film covering the lower electrode and the support film, and an upper electrode facing the lower electrode with the dielectric film interposed therebetween, wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode, and thereby the mechanical strength of the support film is increased. | 10-31-2013 |
| 20130283001 | SEMICONDUCTOR DEVICE THAT BURST-OUTPUTS READ DATA - Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length. | 10-24-2013 |
| 20130278286 | SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT THAT ADJUSTS IMPEDANCE OF OUTPUT BUFFER - Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel. | 10-24-2013 |
| 20130270677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width. | 10-17-2013 |
| 20130270629 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - Disclosed herein is a device that includes: a semiconductor substrate; a first semiconductor pillar having a side surface that is substantially perpendicular to a main surface of the semiconductor substrate; an insulator pillar having a side surface that is substantially perpendicular to the main surface of the semiconductor substrate and a top surface that is substantially parallel to the main surface of the semiconductor substrate; a first gate electrode covering the side surface of the first semiconductor pillar with intervention of a first gate insulation film; an extended gate electrode covering the side surface of the insulator pillar, the extended gate electrode being configured integrally with the first gate electrode; and a conductive film formed on the top surface of the insulator pillar, the conductive film being in contact with the extended gate electrode in a position above the top surface of the insulator pillar. | 10-17-2013 |
| 20130265840 | SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING - Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring. | 10-10-2013 |
| 20130265831 | SEMICONDUCTOR DEVICE HAVING PLURAL DATA INPUT/OUTPUT TERMINALS - Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines. | 10-10-2013 |
| 20130264655 | SEMICONDUCTOR DEVICE, DESIGNING METHOD THEREFOR, AND MANUFACTURING METHOD THEREFOR - In a semiconductor device including active regions which are adjacent to each other with an element isolation region interposed therebetween and which are different in height from the element isolation region, when a contact is formed in a gate wiring on the element isolation region, a contact failure is caused. Provided is a semiconductor device including an element isolation region, two active regions adjacent to each other with the element isolation region interposed therebetween and having surfaces which are higher than that of the element isolation region, a gate wiring commonly led from the respective active regions and extending through the element isolation region, and a contact for connecting the gate wiring to a conductor layer above the gate wiring. The contact is provided in a region other than the element isolation region, or is provided in an expanded element isolation region. | 10-10-2013 |
| 20130264621 | SEMICONDUCTOR DEVICE HAVING FIN-SHAPED FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film. | 10-10-2013 |
| 20130258793 | SEMICONDUCTOR DEVICE - A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained. | 10-03-2013 |
| 20130258792 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER SUPPLY VOLTAGE - Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area. | 10-03-2013 |
| 20130258780 | METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY - Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition. | 10-03-2013 |
| 20130257175 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER-SUPPLY VOLTAGE - The semiconductor device includes a capacitance element connected to a first power-supply line via a first switch element, and to a second power-supply line via a second switch element; and a control circuit that controls the first and second switch elements. The control circuit turns the first switch element ON during a first period (voltage is supplied only to the first power-supply line), while turning the second switch element ON during a second period (voltage is supplied to both the first and second power-supply lines). | 10-03-2013 |
| 20130256918 | DEVICE - A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste. | 10-03-2013 |
| 20130256788 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an isolation region formed by filling a trench with an insulator, an active region surrounded with the sidewall of the trench, a combined pillar including a semiconductor pillar in the active region and an insulator pillar in the isolation region, a gate electrode covering a side surface surrounding the combined pillar; and a transistor including the combined pillar and the gate electrode. The trench has a sidewall in a semiconductor substrate. The insulator pillar contacts the semiconductor pillar with the sidewall of the trench interposed therebetween. | 10-03-2013 |
| 20130250704 | SEMICONDUCTOR DEVICE HAVING LEVEL SHIFTER - Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode. | 09-26-2013 |
| 20130249613 | SEMICONDUCTOR DEVICE AND INPUT SIGNAL RECEPTION CIRCUIT - A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level. | 09-26-2013 |
| 20130249578 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SUBSTRATE - Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line. | 09-26-2013 |
| 20130249085 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SEMICONDUCTOR CHIP - Disclosed herein is a device that includes: a semiconductor substrate; plurality of first through-substrate vias each penetrating through the semiconductor substrate, a plurality of second through-substrate vias each penetrating through the semiconductor substrate, an insulating film formed over the semiconductor substrate, the insulating film including a first opening and a plurality of second openings, the first opening being located over the first through-substrate vias, and each of the second openings being located over a corresponding one of the second through-substrate vias. | 09-26-2013 |
| 20130248809 | VARIABLE RESISTIVE ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - As for a variable resistive element including first and second electrodes, and a variable resistor containing a metal oxide between the first and second electrodes, in a case where a current path having a locally high current density of a current flowing between the both electrodes is formed in the metal oxide, and resistivity of at least one specific electrode having higher resistivity of the both electrodes is 100 μΩcm or more, a dimension of a contact region of the specific electrode with the variable resistor in a short side or short axis direction is set to be more than 1.4 times as long as a film thickness of the specific electrode, which reduces variation in parasitic resistance generated in an electrode part due to process variation of the electrode, and prevents variation in resistance change characteristics of the variable resistive element generated due to the variation in parasitic resistance. | 09-26-2013 |
| 20130242683 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITORS FOR STABILIZING OPERATION VOLTAGE - Disclosed herein is a device that includes first and second memory cell arrays each including a plurality of memory cells, a first power supply line supplying a first voltage to the first memory cell array, a second power supply line supplying the first voltage to the second memory cell array, and a first capacitive element. The first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated. The first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated. | 09-19-2013 |
| 20130242674 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized. | 09-19-2013 |
| 20130242671 | VOLTAGE REGULATOR FOR BIASING A NAND MEMORY DEVICE - Disclosed herein is a device that includes an amplifier, a first transistor coupled between the first power supply line and the internal node and including a gate terminal supplied with a bias voltage, a second transistor coupled between the internal node and the second power supply line and including a gate terminal coupled to the output terminal of the amplifier, a third transistor coupled between the first power supply line and the output node and including a gate terminal coupled to the internal node, a divider configured to produce a first discharge path from the output node to the second power supply line to establish the feedback voltage to the amplifier, and a first switch circuit supplied with a first signal and coupled between the output node and the internal node. | 09-19-2013 |
| 20130242641 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of variable resistance memory cells; a plurality of bit lines each of which is connected to one end of each of the plurality of variable resistance memory cells; a common source line that is connected to the other ends of the plurality of variable resistance memory cells in common; a source line driver that supplies a potential to the common source line; and a controller that variably controls a current supplied to the common source line by the source line driver. | 09-19-2013 |
| 20130241009 | SEMICONDUCTOR DEVICE - A memory cell region comprises a first interlayer insulating film having a bit contact hole, a contact plug formed of a first conductor film embedded in the bit contact hole, and a second conductor film which is stacked on the first interlayer insulating film to constitute a bit line connected to the contact plug. A peripheral transistor region comprises a peripheral transistor having a gate insulating film and a gate electrode stack formed on the gate insulating film. The gate electrode stack is provided with a metal gate film formed on the gate insulating film, an upper gate film stacked on the metal gate film, and a third conductor film stacked on the upper gate film. A height from a semiconductor substrate to a top face of the upper gate film is equal to or lower than a height of a top face of the first interlayer insulating film. | 09-19-2013 |
| 20130240966 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body including a first upper surface with a first side surface extending downwardly therefrom, a second upper surface with a second side surface extending downwardly therefrom, and a bottom surface interfacing first and second side surfaces. The first and second side surfaces and the bottom surface together define a groove. A conductive film partially fills the groove with an intervention of an insulating film therebetween so the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface. A distance between the first intermediate portion of the first side surface and the first upper surface exceeds a distance between the second intermediate portion of the second side surface and the second upper surface. | 09-19-2013 |
| 20130235669 | HIGH VOLTAGE SWITCH CIRCUIT - Disclosed herein is a device that includes a first transistor coupled between an input terminal and an output terminal and including a control gate, a voltage-generating circuit configured to produce a voltage at the control gate of the first transistor, and a discharge circuit coupled between the input terminal of the first transistor and the control gate of the first transistor, the discharge circuit responding to a discharge signal to perform a discharge operation such that an electrical charge is discharged from the output terminal to the input terminal of the first transistor. | 09-12-2013 |
| 20130235641 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring. | 09-12-2013 |
| 20130234342 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias. | 09-12-2013 |
| 20130234323 | SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising stacked substrates through a bump, the bump comprising a solder bump formed on a copper bump wherein the solder bump includes Zn. | 09-12-2013 |
| 20130229870 | NONVOLATILE RAM - A semiconductor random access memory device includes a memory cell including a resistor whose resistance varies by formation and disappearance of a filament due to an oxidation-reduction reaction of metal ions, a memory area configured to include a first memory area operable in a nonvolatile mode in which a stored content thereof is not lost by a power-off event, and a second memory area operable in a volatile mode in which the stored content thereof is lost by the power-off event, each of the first memory area and the second memory area including the plurality of the memory cells, a register circuit that stores information including a first address information indicating the first memory area, and a second address information indicating the second memory area, and a control circuit that controls the nonvolatile mode, and the volatile mode, with reference to the information stored in the register circuit. | 09-05-2013 |
| 20130229857 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced. | 09-05-2013 |
| 20130229214 | SEMICONDUCTOR DEVICE GENERATING PHASE-CONTROLLED CLOCK SIGNAL - The semiconductor device includes a frequency detection circuit that outputs a frequency detection signal based on a frequency of a first clock signal; a phase comparison circuit that compares a phase of the first clock signal with a phase of a reference clock signal and outputs a phase comparison signal according to a result of the comparison; and a phase adjustment circuit that outputs a second clock signal by shifting the phase of the first clock signal according to the phase comparison signal. An amount of the phase of the first clock signal according to the phase comparison signal is variable according to the frequency detection signal. | 09-05-2013 |
| 20130228935 | SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER - Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. | 09-05-2013 |
| 20130228898 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SUBSTRATE - Disclosed herein is a device that includes: a first semiconductor chip having a first internal circuit formed in a first substrate; and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode. | 09-05-2013 |
| 20130228877 | SEMICONDUCTOR DEVICE HAVING PLURAL STANDARD CELLS - Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the first standard cells in a second direction. The field-effect transistor including a gate electrode formed on a gate wiring layer. The first power supply wiring being formed on the gate wiring layer. | 09-05-2013 |
| 20130228837 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to −700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film. | 09-05-2013 |
| 20130227229 | SEMICONDUCTOR DEVICE THAT BURST-OUTPUTS READ DATA - A semiconductor device includes a command terminal, a plurality of memory banks, a control circuit and an output circuit. The control circuit is configured to respond to each of issuance of a read command, that is supplied to the command terminal, to perform a read operation on any one of the memory banks so that the any one of the memory banks output a plurality of read data sets. The output circuit receives the read data sets and outputs the read data sets to outside in response to a clock signal so that a first interval substantially the same as a period of the clock signal or longer than the period of the clock signal is interposed between the read data sets. | 08-29-2013 |
| 20130223170 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: plurality of global bit lines; plurality of sense amplifier circuits each connected to corresponding one of the plurality of global bit lines; plurality of column selection lines each of which is connected to or disconnected from corresponding one of the plurality of sense amplifier circuits according to column address information; and plurality of local bit lines including first local bit line and second local bit line. The first local bit line is connected to or disconnected from corresponding one of the plurality of global bit lines according to first row address information different from column address information. The second local bit line replaces first local bit line when defect is present in first local bit line and is connected to or disconnected from corresponding global bit line according to second row address information different from column address information. | 08-29-2013 |
| 20130223167 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, | 08-29-2013 |
| 20130223152 | CLOCK GENERATOR - A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power supply. The clock generator or oscillating circuit may also adjust the clock period (T) of the clock signal, either or both upwards and downwards, around its central value to compensate fabrication process variations. | 08-29-2013 |
| 20130217202 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 08-22-2013 |
| 20130215698 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON. | 08-22-2013 |
| 20130215691 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information. | 08-22-2013 |
| 20130215676 | SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal. | 08-22-2013 |
| 20130215659 | LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. | 08-22-2013 |
| 20130214427 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED WITH EACH OTHER - A first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor chip is stacked over the second surface of the first semiconductor chip. The second semiconductor chip is larger in size than the first semiconductor chip. A first sealing resin covers the first and second semiconductor chips so that the first surface exposes from the first sealing resin. A first width of the first sealing resin that is around the first semiconductor chip is larger than a second width of the first sealing resin that is around the second semiconductor chip. | 08-22-2013 |
| 20130214420 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar. | 08-22-2013 |
| 20130214338 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a convex portion, a concave portion provided so as to cover upper and side surfaces of the convex portion, a gate electrode provided so as to be opposed to the convex portion with a gate insulating film interposed between the gate electrode and the convex portion, a pair of diffusion layers provided within the convex portion so as to sandwich the gate electrode, and a contact plug provided on the concave portion, so as to be electrically connected to at least one of the diffusion layers. | 08-22-2013 |
| 20130207171 | SEMICONDUCTOR DEVICE HAVING CAPACITOR INCLUDING HIGH-K DIELECTRIC - A first semiconductor device comprises a metal-oxide film over a substrate. The metal-oxide film is formed by an atomic layer deposition method including a treatment in a reducing gas atmosphere after forming oxidized metal. A second semiconductor device comprises a lower electrode having a cup shape over a substrate, a metal-oxide film covering the lower electrode, and an upper electrode covering the metal-oxide film. The metal-oxide film is formed by an atomic layer deposition method including a treatment in a reducing gas atmosphere after forming oxidized metal. | 08-15-2013 |
| 20130205157 | DATA TRANSFER OPERATION COMPLETION DETECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE PROVIDED THEREWITH - A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress. | 08-08-2013 |
| 20130201774 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data. | 08-08-2013 |
| 20130201744 | DMA ARCHITECTURE FOR NAND-TYPE FLASH MEMORY - A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits. | 08-08-2013 |
| 20130200941 | CASCADED HIGH VOLTAGE SWITCH ARCHITECTURE - Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line. | 08-08-2013 |
| 20130194857 | SEMICONDUCTOR DEVICE HAVING BIT LINES HIERARCHICALLY STRUCTURED - Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals. | 08-01-2013 |
| 20130194035 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 08-01-2013 |
| 20130193590 | SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad. | 08-01-2013 |
| 20130193586 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. | 08-01-2013 |
| 20130193507 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate. | 08-01-2013 |
| 20130193396 | VARIABLE RESISTIVE ELEMENT, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A variable resistive element that performs a forming action at small current and a stable switching operation at low voltage and small current, and a low-power consumption large-capacity non-volatile semiconductor memory device including the element are realized. The element includes a variable resistor between first and second electrodes. The variable resistor includes at least two layers, which are a resistance change layer and high-oxygen layer, made of metal oxide or metal oxynitride. The high-oxygen layer is inserted between the first electrode having a work function smaller than the second electrode and the resistance change layer. The oxygen concentration of the metal oxide of the high-oxygen layer is adjusted such that the ratio of the oxygen composition ratio to the metal element to stoichiometric composition becomes larger than the ratio of the oxygen composition ratio to the metal element of the metal oxide forming the resistance change layer to stoichiometric composition. | 08-01-2013 |
| 20130187294 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 07-25-2013 |
| 20130183799 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device, which includes: preparing a semiconductor wafer; and peeling off an adhesive layer from the semiconductor wafer. The prepared semiconductor wafer includes at least one semiconductor chip having a bump electrode group formed by arraying bump electrodes in a matrix, and the adhesive layer formed on one surface having the bump electrodes. The bump electrode group is formed by arraying the bump electrodes so that the number of bump electrodes in a second direction can be smaller than that in a first direction. To peel off the adhesive layer from the semiconductor wafer, the adhesive layer is peeled off from the semiconductor wafer along the first direction from one end side of the semiconductor wafer. | 07-18-2013 |
| 20130182516 | SEMICONDUCTOR DEVICE HAVING COUNTER CIRCUIT - A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal. | 07-18-2013 |
| 20130181345 | SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE PENETRATING THROUGH SEMICONDUCTOR SUBSTRATE - Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer. | 07-18-2013 |
| 20130181271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 07-18-2013 |
| 20130175682 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film. | 07-11-2013 |
| 20130173973 | DEVICE - A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data. | 07-04-2013 |
| 20130173864 | SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER - Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address. | 07-04-2013 |
| 20130164909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask. | 06-27-2013 |
| 20130163361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input. | 06-27-2013 |
| 20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 06-27-2013 |
| 20130163303 | SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE - Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. | 06-27-2013 |
| 20130162308 | SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL - Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. | 06-27-2013 |
| 20130162302 | SEMICONDUCTOR DEVICE HAVING DATA OUTPUT CIRCUIT IN WHICH SLEW RATE THEREOF IS ADJUSTABLE - Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals. | 06-27-2013 |
| 20130162282 | SEMICONDUCTOR DEVICE HAVING POTENTIAL MONITORING TERMINAL TO MONITOR POTENTIAL OF POWER-SUPPLY LINE - Disclosed herein is a device that includes an internal circuit, a first terminal supplied with a first voltage, a first power-supply line coupled between the first terminal and the internal circuit, a potential monitoring terminal, and a first switch coupled between the internal power-supply line and the potential monitoring terminal. | 06-27-2013 |
| 20130162275 | SEMICONDUCTOR DEVICE HAVING COMMAND MONITOR CIRCUIT - A semiconductor device includes a plurality of channels, a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively, and a plurality of signal lines coupled in common to the plurality of command monitor circuits. Each of the plurality of command monitor circuits includes a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information, and an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information. One of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information. | 06-27-2013 |
| 20130161827 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATION ELECTRODE PENETRATING THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode. | 06-27-2013 |
| 20130161738 | SEMICONDUCTOR DEVICE - A semiconductor device | 06-27-2013 |
| 20130161733 | SEMICONDUCTOR DEVICE - Disclosed herein a semiconductor device, which comprises: a vertical MOS transistor that has an upper diffusion layer, and a first lower diffusion layer disposed at a lower position than the upper diffusion layer; and a first diode that has a first well isolated from the first lower diffusion layer, and a second lower diffusion layer disposed at a lower position than the upper diffusion layer and formed in the first well. A surge voltage is discharged across the second lower diffusion layer and the first well when the surge voltage is applied. | 06-27-2013 |
| 20130155798 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. | 06-20-2013 |
| 20130155792 | SEMICONDUCTOR DEVICE HAVING DATA TERMINAL SUPPLIED WITH PLURAL WRITE DATA IN SERIAL - Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals. | 06-20-2013 |
| 20130155752 | WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP - Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip. | 06-20-2013 |
| 20130154096 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film. | 06-20-2013 |
| 20130154057 | Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO | 06-20-2013 |
| 20130154056 | SEMICONDUCTOR DEVICE - In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium. | 06-20-2013 |
| 20130154025 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR STABILIZING VARIATION OF POWER SUPPLY VOLTAGE - Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor. | 06-20-2013 |
