CYPRESS SEMICONDUCTOR CORPORATION Patent applications |
Patent application number | Title | Published |
20160118980 | LOW POWER CAPACITIVE SENSOR BUTTON - Disclosed herein are system, methods, and apparatus for low power capacitive sensors. Apparatus may include a timing block configured to generate a repetitive trigger signal having a first frequency, and further configured to generate a clock signal having a second frequency. Apparatus may also include a sensing block coupled with the timing block and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a capacitive sensor button by applying an excitation signal to the capacitive sensor button during a measurement period. Apparatus further include a wake logic block coupled with the sensing block and configured to transition a processing unit from a first power consumption state to a second power consumption state in response to the sensing block detecting the change in capacitance associated with the object proximate to the capacitive sensor button. | 04-28-2016 |
20160111292 | CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different. | 04-21-2016 |
20160085355 | FORCE SENSOR BASELINE CALIBRATION - Systems, methods, and apparatus for force sensor baseline calibration are disclosed herein. 1. Apparatus may include a force sensor configured to receive a plurality of force signals from a plurality of force sensitive elements, where the plurality of force signals is associated with a first touch at a first location of a sensing surface. The apparatus may include a touch sensor configured to receive a touch signal associated with the first touch. The apparatus may include processing logic coupled to the force sensor and the touch sensor, the processing logic being configured to determine a magnitude of a first component force associated with the first touch based, at least in part, on the plurality of force signals and the touch signal. The first component force may characterize a force applied by the first touch at the first location of the sensing surface. | 03-24-2016 |
20160062379 | SYSTEMS, METHODS, AND DEVICES FOR BOOTSTRAPPED POWER CIRCUITS - Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled between a first and second position. Devices may include a power source configured to store a second voltage having a second amplitude. Devices may include a bootstrap circuit configured to receive a third voltage from the power source when the switch is in the first position, and configured to receive at least some of the amount of energy from the power converter when the switch is in the second position. | 03-03-2016 |
20160004343 | Single Layer Sensor Pattern - An embodiment of a capacitive sensor array may comprise a first set of sensor electrodes each comprising one or more large subelements and a second set of sensor electrodes each comprising one or more small subelements. In one embodiment, each of the small subelements may be smaller than any of the large subelements, and the first set of sensor electrodes and the second set of sensor electrodes are formed from a single layer of conductive material. In one embodiment, the surface area of the capacitive sensor array may be divisible into a grid of N×M unit cells, wherein each of the N×M unit cells contains one of the large subelements and k of the small subelements, where k is greater than or equal to 2. | 01-07-2016 |
20160003881 | CAPACITANCE SENSING CIRCUITS AND METHODS - A capacitance sense system can include a capacitance sense input configured to receive an input signal that varies according to a sensed capacitance; an integrator/discharge circuit configured to integrate the input signal and discharge the integrated input signal toward the reference level in conversion operations; and a remainder retainer section configured to quantize the discharging of the integrated input signal, and retain any remainder of the integrated input signal that follows a quantization point for a next conversion by the integrator/discharge circuit. | 01-07-2016 |
20150248177 | BARRIER ELECTRODE DRIVEN BY AN EXCITATION SIGNAL - Apparatuses and methods of driving barrier electrodes of a capacitive-sense array with an excitation signal are described. One apparatus includes a capacitance-sensing circuit coupled to a capacitive-sense array including multiple electrodes. The capacitance-sensing circuit includes multiple sensing channels. The capacitance-sensing circuit is operative to measure signals on a first subset of the multiple electrodes using the multiple sensing channels. Each of the sensing channels is selectively coupled to one of the first subset of electrodes. The capacitance-sensing circuit is further operative to drive a barrier electrode of the multiple electrodes with an excitation signal while measuring the signals on the first subset. The excitation signal is greater in magnitude than the measured signals. The barrier electrode is adjacent to an edge electrode of the first subset that is coupled to one of the sensing channels. A second subset of electrodes can be driven by a shield signal and the excitation signal is greater in magnitude than the shield signal. | 09-03-2015 |
20150160744 | Stylus Tip Shape - Stylus tip configurations may reduce shadow effect of the stylus tip on capacitance measurements by reducing capacitive coupling between undesired portions of the stylus tip and the capacitive sensing surface. Additionally signal-to-noise ratio (SNR) of a stylus on a plurality of capacitance sensing electrodes may be improved by reducing the self capacitance between the stylus tip and the receive electrodes of a mutual capacitance touch screen. | 06-11-2015 |
20150117091 | MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT - An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal. | 04-30-2015 |
20150072441 | METHOD OF FABRICATING A FERROELECTRIC CAPACITOR - Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top electrode formed by etching through the top electrode layer and at least partially through the ferroelectric layer. A non-conductive barrier is formed on sidewalls formed by etching through the top electrode layer and at least partially through the ferroelectric layer, and then a bottom electrode is formed by etching the bottom electrode layer so that conductive residues generated by the etching are electrically isolated from the top electrode by the non-conductive barrier. | 03-12-2015 |
20150062094 | Active Stylus to Host Data Transmitting Method - Apparatus and methods of active stylus to host device data transmitting are described. One method receives, at a stylus, an indication that a host device is performing a first coordinate measurement operation to determine a coordinate of the stylus proximate to a capacitive sense array of the host device. The set of coordinate measurement operations includes a first measurement operation of a first set of electrodes of the capacitive sense array and a second measurement operation of a second set of electrodes of the capacitive sense array. While the host device is performing the set of coordinate measurement operations, the stylus transmits a data packet of stylus data to the host device. In particular, the stylus transmits a first bit of the data packet during the first measurement operation and transmits a second bit of the data packet during the second measurement operation. | 03-05-2015 |
20140374813 | SONOS Stack With Split Nitride Memory Layer - A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described. | 12-25-2014 |
20140369136 | SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES - Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device. | 12-18-2014 |
20140368960 | OVER-VOLTAGE TOLERANT CIRCUIT AND METHOD - Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit. | 12-18-2014 |
20140340978 | ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS - A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations. | 11-20-2014 |
20140327553 | ZERO POWER METERING CIRCUITS, SYSTEMS AND METHODS - A system can include a passive wireless interface circuit that generates data from a wireless signal and further includes an energy harvesting circuit that generates first operating power from the wireless signal; a meter interface circuit configured to receive at least one input signal and second operating power from a metering device; logic circuits configured to arbitrate accesses to nonvolatile storage circuits from the passive wireless interface and meter interface circuits using the first or second operating power. | 11-06-2014 |
20140316729 | HARDWARE DE-CONVOLUTION BLOCK FOR MULTI-PHASE SCANNING - Apparatuses and methods of hardware de-convolution for multi-phase scanning of a touch arrays are described. One apparatus includes a memory device configured to store a capacitance map including convolved capacitance data. The convolved data are results of multi-phase transmit (TX) scanning of a sense array with multiple TX patterns. The apparatus further comprises a de-convolution circuit block coupled to the memory device. The de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the multiple TX patterns to obtain capacitance data for a de-convolved capacitance map. | 10-23-2014 |
20140313159 | UNIFORM SIGNALS FROM NON-UNIFORM PATTERNS OF ELECTRODES - Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern including a first region being located at the intersection of the respective unit cell and a distal region being at a location within the respective unit cell that is farther away from the intersection than the first region. The first region includes a first conductive surface area and the distal region includes a second conductive surface area that is greater than the first conductive surface area. | 10-23-2014 |
20140301139 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 10-09-2014 |
20140293717 | MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE - A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal. | 10-02-2014 |
20140285469 | Predictive Touch Surface Scanning - A method for locating a conductive object at a touch-sensing surface may include detecting a first resolved location for the conductive object at the touch-sensing surface based on a first scan of the touch-sensing surface, predicting a location for the conductive object, and determining a second resolved location for the conductive object by performing a second scan of a subset of sensor electrodes of the touch-sensing surface, wherein the subset of sensor electrodes is selected based on the predicted location of the conductive object. | 09-25-2014 |
20140285467 | Method and Apparatus for Identification of Touch Panels - A method for configuring a touchscreen controller may include identifying a model of a touchscreen by measuring a capacitance or resistance of at least one element integrated in the touchscreen, identifying the model of the touchscreen based on the measured capacitance or resistance, and configuring the touchscreen controller based on the identified model of the touchscreen. | 09-25-2014 |
20140284696 | OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS - A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described. | 09-25-2014 |
20140281200 | MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-SPEED ACCESS OF MEMORY MODULES - A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed. | 09-18-2014 |
20140267216 | DIGITAL DRIVING CIRCUITS, METHODS AND SYSTEMS FOR LIQUID CRYSTAL DISPLAY DEVICES - A method may include generating display driver signals that vary between only two levels and applying the display driver signals to opposing electrodes of a display segment within a display device. An intrinsic capacitance of the display device filters the display driver signals to generate different analog signal levels at the display segment of the display device. The method varies the pulse density of the display driver signals to select or de-select the display segment based on an average voltage magnitude across the display segment over a time period. The display segment is activated when the average voltage magnitude exceeds a threshold value. | 09-18-2014 |
20140267151 | ATTENUATOR CIRCUIT OF A CAPACITANCE-SENSING CIRCUIT - Apparatuses and methods of input attenuator circuits are described. One sensing circuit includes an attenuator circuit to receive a signal from an electrode of a sense array. The attenuator circuit is configured to attenuate input current of the signal. The attenuator circuit includes an attenuation matrix including an input terminal to receive the signal and multiple resistors. The attenuation matrix is configured to split the input current into an output current of the attenuation signal on a first output terminal and a second output current on a second output terminal. The attenuation matrix is to output the attenuated signal on the first output terminal to an integrator of the sensing circuit. The attenuator circuit also includes a buffer coupled between the attenuation matrix and the integrator. The buffer is configured to maintain a substantially same voltage at the first output terminal and the second output terminal. | 09-18-2014 |
20140266257 | METHODS AND CIRCUITS FOR MEASURING MUTUAL AND SELF CAPACITANCE - In an example embodiment, an apparatus includes a sensing device. The sensing device includes circuitry configured to sense self-capacitance and circuitry configured to sense mutual-capacitance, each configured to detect capacitance values corresponding to whether an object is proximate to a touch screen. The sensing device is configured to measure a first capacitance value using the self-capacitance circuitry during self-capacitance sensing operations and to measure a second capacitance value using the mutual-capacitance circuitry during mutual-capacitance sensing operations. | 09-18-2014 |
20140264552 | NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS - A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed. | 09-18-2014 |
20140264551 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described. | 09-18-2014 |
20140264550 | Nonvolatile Charge Trap Memory Device Having a Deuterated Layer in a Multi-Layer Charge-Trapping Region - A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer. | 09-18-2014 |
20140245263 | DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT - A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code. | 08-28-2014 |
20140239374 | EMBEDDED SONOS BASED MEMORY CELLS - Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor. | 08-28-2014 |
20140235046 | METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW - A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described. | 08-21-2014 |
20140211547 | MEMORY CELL ARRAY LATCHUP PREVENTION - A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices are configured to limit current through each of the columns so that current through a memory cell in a row of the column due to a soft error rate event does not result in a lateral spread of soft errors to memory cells in the row in an adjacent column. Other embodiments are also provided. | 07-31-2014 |
20140210784 | TOUCH SENSOR DEVICE - Described herein are capacitance sensing devices and methods for forming such devices. A capacitance sensing device includes a substrate and a plurality of electrodes disposed on an area of the substrate to form an active portion of the device. Each of the plurality of electrodes comprises at least one irregular edge formed along a non-linear path. The touch sensor also includes a first plurality of conductors disposed on the substrate. Each of the first plurality of conductors has an end electrically connected to one of the plurality of electrodes. The touch sensor can also include a second plurality of conductors that form a routing channel. Each of the second plurality of conductors has an end electrically connected to a second end of one of the first plurality of conductors. Each of the second plurality of conductors has an end electrically connected to a second end of one of the first plurality of conductors. At least one of the first plurality of conductors or at least one of the second plurality of conductors comprise at least one irregular edge formed along a non-linear path. | 07-31-2014 |
20140192030 | STYLUS AND RELATED HUMAN INTERFACE DEVICES WITH DYNAMIC POWER CONTROL CIRCUITS - A device comprising a body comprising an elongated housing with at least a first conductive tip formed at a distal end and at least one sense electrode on the body; a capacitance sense circuit disposed within the housing and configured to sense a capacitance of the sense electrode to generate a proximity result in response to contact with a human body; and a signal generator circuit disposed within the housing and configured to activate a position signal in response to the proximity result, the position signal being driven at the tip of the device | 07-10-2014 |
20140192027 | Tail Effect Correction for SLIM Pattern Touch Panels - Techniques for correcting tail effect are described herein. In an example embodiment, a device comprises a sensor coupled with a processing logic. The sensor is configured to measure a plurality of measurements from a sensor array, where the measurements are representative of a conductive object that is in contact with or proximate to the sensor array. The sensor array comprises RX electrodes and TX electrodes that are interleaved without intersecting each other in a single layer on a substrate of the sensor array. The processing logic is configured to determine a set of adjustment values that correspond to a tail effect associated with the measurements, and to generate adjusted measurements based on the set of adjustment values, where the adjusted measurements correct a parasitic signal change of the tail effect. | 07-10-2014 |
20140191995 | Touch Identification for Multi-Touch Technology - A first plurality of contact locations may be determined in view of a first scan of a touch-sensing surface and a second plurality of contact locations may be determined in view of a second scan of the touch-sensing surface. A number of total contact locations may be identified in view of the first plurality of contact locations and the second plurality of contact locations. Furthermore, a first correlation process may be performed when the number of total contact locations satisfies a threshold number and a second correlation process may be performed when the number of total contact locations does not satisfy the threshold number. | 07-10-2014 |
20140191675 | SYSTEM AND METHOD FOR CONTROLLING A LIGHT EMITTING DIODE FIXTURE - One embodiment in accordance with the invention can include a circuit for controlling a light emitting diode (LED) lighting fixture via a power line. The circuit can include a power switch coupled to the power line and is for outputting a firing angle. Additionally, the circuit can include a control circuit coupled to the power switch and is for implementing firing angle control of the power switch. Furthermore, the circuit can include a translator coupled to receive the firing angle and for mapping the firing angle to a function of the LED lighting fixture. | 07-10-2014 |
20140184280 | LOAD DRIVER - A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage. | 07-03-2014 |
20140160030 | SENSOR SYSTEM AND METHOD FOR MAPPING AND CREATING GESTURES - A computing system includes a sensor configured to detect user inputs. The system further includes a processor configured to receive a detected first user input from the sensor. The processor further receives a detected second user input from the sensor. In response, the processor assigns a command to the first user input based on the second user input. | 06-12-2014 |
20140103418 | SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias. | 04-17-2014 |
20140098598 | MEMORY CELL ARRAY LATCHUP PREVENTION - A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus. | 04-10-2014 |
20140095757 | MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 04-03-2014 |
20140095120 | DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT - A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from both the internal domain and the external domain in a single view of the design interface. | 04-03-2014 |
20140093983 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE - A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer. | 04-03-2014 |
20140087484 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS - A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer. | 03-27-2014 |
20140085257 | CAPACITIVE STYLUS FOR A TOUCH SCREEN - A stylus having a transmit drive circuit configured to transmit a signal to a capacitance sensor via capacitive coupling between the stylus and a capacitive sense array which is coupled to the capacitance sensor, which is configured to synchronize to the stylus, the stylus being configured to act as a timing master. | 03-27-2014 |
20140077827 | METHOD FOR IMPROVING SCAN TIME AND SENSITIVITY IN TOUCH SENSITIVE USER INTERFACE DEVICE - System and method for optimizing the consumption of power while maintaining performance in capacitive sensor arrays. A limited sensing area is used to improve the update rate and sensitivity of a row/column array of capacitive sensors. According to one embodiment, a method is provided for scanning a plurality of capacitive sensors by: detecting a stimulus in the field of capacitive sensors, scanning the field of capacitive sensors to determine the position of the stimulus. Once the position of the stimulus is determined, a subsection of the field comprising window corresponding to the position of the stimulus remains activated while the remaining sensors in the field are deactivated. | 03-20-2014 |
20140056093 | ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS - A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed. | 02-27-2014 |
20140043251 | Dual Scanning with Automatic Gain Control - A method and apparatus perform a first scan of an input device and determine that a first signal profile received through the first scan is outside a range of a reference signal profile. The method and apparatus perform a second scan of the input device responsive to the first signal profile being outside the range of the reference signal profile and use a second signal profile received through the second scan to detect a presence of an input object at least proximate to the input device. | 02-13-2014 |
20140035871 | Capacitance Scanning Proximity Detection - A method and apparatus for scanning a first set of electrodes of a capacitive sense array using a first sensing mode to identify a presence of an object in proximity to the capacitive sense array, where scanning using the first sensing mode identifies objects not in physical contact with the capacitive sense array. The first set of electrodes is scanned using a second sensing mode to determine a location of the object in relation to the capacitive sense array, where rescanning using the second sensing mode determines locations of objects in physical contact with the capacitive sense array. | 02-06-2014 |
20140022211 | TOUCHSCREEN DATA PROCESSING - Capacitive touch sensors and touchscreen data processing methods are provided. In one embodiment, the method includes sequentially integrating and converting charge from each of a plurality of sensing capacitors in an array to digital data, the digital data including sample values corresponding to a measured capacitance for each of the plurality of sensing capacitors. Noise is then separated from useful information by filtering the sample values on a sample-by-sample basis. Finally, the filtered sample values are summed and a position of at least one contact on the array determined using the filtered capacitance values. Other embodiments are also provided. | 01-23-2014 |
20140022206 | HARDWARE ACCELERATOR FOR TOUCHSCREEN DATA PROCESSING - A contact's interaction with a sensing array is subject to several external and internal stimuli which may impact a processing unit's confidence in the characteristics of that interaction or the presence of the interaction itself. Fidelity of user action is greatly improved with a step-wise and holistic analysis of a contact on an array of capacitance sensors, which allows for repetition of certain steps of processing or the entire operation if threshold confidence levels are not achieved. | 01-23-2014 |
20140022202 | Sensor Array with Edge Pattern - A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells. | 01-23-2014 |
20140022201 | Gain Correction for Fast Panel Scanning - Settling time for high-impedance conductive materials in capacitance touchscreen may be overcome by employed a series of mathematical or hardware implemented correction factors. Correction factors may allow for faster mutual capacitance measurement and enable greater noise performance for mutual capacitance panels. | 01-23-2014 |
20140015768 | EDGE-BY-EDGE INTEGRATION AND CONVERSION - An apparatus includes a transmission system configured to transmit a drive signal to a touch screen device. The apparatus also includes a reception system configured to integrate an output signal received from a touch screen device in response to the drive signals and to filter the integrated output signal to suppress noise in the output signal, wherein the reception system is configured to integrate the output signal for a period of time that is less than or equal to a signal period corresponding to the drive signal. | 01-16-2014 |
20140006730 | MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY MEMORY DEVICES | 01-02-2014 |
20140002409 | METHODS AND APPARATUS TO DETERMINE POSITION OF AN INPUT OBJECT | 01-02-2014 |
20140002112 | DEVICES AND METHODS HAVING CAPACITANCE SENSE STRUCTURE FORMED OVER HOUSING SURFACE | 01-02-2014 |
20130309826 | RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE - A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation. | 11-21-2013 |
20130307823 | DYNAMIC MODE SWITCHING FOR FAST TOUCH RESPONSE - A method of operating a touch-sensing surface may include performing a first scan of a first set of electrodes of a touch-sensing surface, determining a presence of at least one conductive object proximate to the touch-sensing surface, in response to determining the presence of the at least one conductive object, performing a second scan of a second set of electrodes of the touch-sensing surface, and repeating the performing the second scan until the at least one conductive object is no longer proximate to the touch-sensing surface. | 11-21-2013 |
20130307053 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed. | 11-21-2013 |
20130307052 | SONOS ONO STACK SCALING - A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer. | 11-21-2013 |
20130306975 | Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-Layer Charge-Trapping Region - Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed | 11-21-2013 |
20130298100 | Graphical User Interface for Display of System Resistance - Techniques for determining resistances of analog routes in electronic designs are described herein. In an example embodiment, a computer system receives first user input that indicates, in a user interface, a first component in an electronic design. The electronic design has been placed and routed for a programmable target device. The computer system receives second user input that selects, in the user interface, a particular component from one or more second components of the electronic design, where the one or more second components have analog connectivity to the first component. The computer system determines a resistance value of an analog route between the first component and the particular component, and displays the resistance value in association with the analog route in the user interface. | 11-07-2013 |
20130278334 | SLEW RATE AND BANDWIDTH ENHANCEMENT IN RESET - Embodiments of a capacitance sensing system including an integrating amplifier and methods for operating the same to provide a higher slew rate and bandwidth are described. In one embodiment, the integrating amplifier comprises an input stage including an inverting input coupled to an electrode of a capacitor to sense a capacitance and a non-inverting input coupled to a reference potential, and an output stage including a compensating capacitor coupled to an output. The compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor. | 10-24-2013 |
20130265089 | SYSTEMS AND METHODS FOR STARTING UP ANALOG CIRCUITS - Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled based on the comparison of VOUT and VREF. One system includes an analog device coupled to the above circuit. A method includes enabling the startup portion to start up the driver portion when VOUT is outside a predetermined voltage of VREF, disabling the startup portion when VOUT is within the predetermined voltage, and enabling the driver portion to drive the analog device subsequent to disabling the startup portion. | 10-10-2013 |
20130249314 | SYSTEMS AND METHODS FOR SWITCHING BETWEEN VOLTAGES - Systems and methods for switching between voltages are provided. One system includes an output, first and second switches coupled to the output. The system also includes a first transmission gate coupled to the first switch and a second transmission gate coupled to the second switch. One method includes receiving, at the first transmission gate, a first pair of complementary voltages and receiving, at the second transmission gate, a second pair of complementary voltages. The method further includes selecting the smallest voltage amongst both pairs of complementary voltages and outputting a third pair of complementary voltages. In one method, the first pair of complementary voltages includes a first negative voltage and a positive voltage, the second pair of complementary voltages includes a second negative voltage and the positive voltage, and the third pair of complementary voltages includes the smaller of the first and second negative voltages and the positive voltage. | 09-26-2013 |
20130241630 | Touch Sensor Driver With Selectable Charge Source - An apparatus may include an internal charge pump within an integrated circuit package, an external pin positioned at an exterior of the integrated circuit package, and a select circuit configured to operate independently from the internal charge pump and located within the integrated circuit package, wherein the select circuit is configurable to selectively couple at least one of the internal charge pump and the external pin to a transmit (TX) sensor electrode. | 09-19-2013 |
20130234978 | FALSE TOUCH FILTERING FOR CAPACITANCE SENSING SYSTEMS - Apparatuses and methods of false touch filtering are described. One device includes a controller and a capacitance sensing array including multiple sense elements (e.g., intersections of TX and RX electrodes). The controller includes a capacitance sensing circuit coupled to the capacitance sensing array, and a filter circuit coupled to the output of the capacitance sensing circuit. The controller is configured to receive, from the capacitance sensing circuit, data representing capacitances of the sense elements, process the data to identify activated sense elements, and filter the data to remove false touch events based on a spatial relationship of activated sense elements. | 09-12-2013 |
20130225072 | METHOD AND APPARATUS FOR DATA TRANSMISSION VIA CAPACITANCE SENSING DEVICE - Embodiments described herein provide methods, devices, and systems for a touch sensor, or capacitive sensing device, interact with external objects. One method utilizes a capacitive profile on the external object. Another method involves the use of a capacitive sensor array for wireless communication. | 08-29-2013 |
20130223165 | MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE - A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal. | 08-29-2013 |
20130222332 | CIRCUITS, SYSTEMS, AND METHODS FOR PROCESSING THE PROXIMITY OF LARGE OBJECTS, INCLUDING LARGE OBJECTS ON TOUCH SCREENS - A method of sensing at least one object in proximity to an array of sensors can include making a determination that an object greater than a predetermined size has been detected; defining an ignore zone that includes sensor locations of the object and sensor locations surrounding those of the object; and removing the ignore zone after a predetermined duration; wherein the proximity of objects outside of the ignore zone are processed differently than the proximity of objects inside of the ignore zones. | 08-29-2013 |
20130222331 | Close Touch Detection and Tracking - A method of tracking touches at a touch-sensing surface may include, detecting an initial location of a first contact and an initial location of a second contact at the touch-sensing surface based on a first scan of a touch-sensing surface, detecting a plurality of signal levels caused by the first contact and the second contact during a second scan of the touch-sensing surface, identifying a first signal level of the plurality of signal levels as a local maximum, and locating a lost touch based on one or more signal levels associated with one or more unit cells within a fixed distance from a first unit cell associated with the local maximum. | 08-29-2013 |
20130211776 | BALL GRID STRUCTURE - An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the contact grid array based, at least in part, on the area available for the contact grid array on the substrate. | 08-15-2013 |
20130210209 | METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW - Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed. | 08-15-2013 |
20130178031 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate. | 07-11-2013 |
20130178030 | METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW - An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer. | 07-11-2013 |
20130175604 | NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION - An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer. | 07-11-2013 |
20130175600 | SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER - Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed. | 07-11-2013 |
20130175599 | INLINE METHOD TO MONITOR ONO STACK QUALITY - Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages. | 07-11-2013 |
20130175504 | OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS - An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer. | 07-11-2013 |
20130170312 | CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST - A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”). | 07-04-2013 |
20130170292 | HIGH VOLTAGE TOLERANT ROW DRIVER - A circuit is configured to supply a first gate voltage (PG | 07-04-2013 |
20130169582 | CONTACT IDENTIFICATION AND TRACKING ON A CAPACITANCE SENSING ARRAY - Active stylus operation when there is no physical connection between the stylus and the touch array requires communication and synchronization. It is possible to use the touchscreen stack-up itself to communicate synchronization signals or other information optically by outfitting the active stylus with an optical receiver and transmitting signals either with additional diodes or by modulating the display clock itself. | 07-04-2013 |
20130169519 | METHODS AND APPARATUS TO PERFORM A DETECTION OPERATION - A method and apparatus determine a difference value, the determined difference value reflecting a difference between a plurality of presence values. In an embodiment, the method and apparatus perform an operation associated with the plurality of presence values, based on the determined difference value. | 07-04-2013 |
20130169294 | DEVICES AND METHODS HAVING CAPACITANCE SENSE STRUCTURE FORMED OVER HOUSING SURFACE - A capacitance sensing system can include at least a first conductive pattern formed on a first surface of a housing of an electronic device; and a capacitance sensing circuit electrically connected to the first conductive pattern. | 07-04-2013 |
20130147732 | TOUCH SENSING - A method and apparatus varying, by interval, a frequency of a drive signal applied to one electrode of each of a plurality of electrode pairs, select a frequency corresponding to the frequency of the drive signal, monitor changes in capacitance of each of the electrode pairs through receive signals at the selected frequency, from the other electrode of each of the plurality of electrode pairs; and determine a position of at least two objects, which are simultaneously on a touch device, according to the monitored capacitance changes. | 06-13-2013 |
20130145056 | UTILIZING USB RESOURCES - At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port. | 06-06-2013 |
20130141984 | INTERNAL DATA COMPARE FOR MEMORY VERIFICATION - A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row. | 06-06-2013 |
20130141978 | FLASH MEMORY DEVICES AND SYSTEMS - Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations. | 06-06-2013 |
20130135954 | MEMORY CELL ARRAY LATCHUP PREVENTION - A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level. | 05-30-2013 |
20130132614 | RE-ENUMERATION OF USB 3.0 COMPATIBLE DEVICES - A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device. | 05-23-2013 |
20130100071 | Predictive Touch Surface Scanning - A method for locating a conductive object at a touch-sensing surface may include detecting a first resolved location for the conductive object at the touch-sensing surface based on a first scan of the touch-sensing surface, predicting a location for the conductive object, and determining a second resolved location for the conductive object by performing a second scan of a subset of sensor electrodes of the touch-sensing surface, wherein the subset of sensor electrodes is selected based on the predicted location of the conductive object. | 04-25-2013 |
20130086282 | METHODS AND PHYSICAL COMPUTER-READABLE STORAGE MEDIA FOR INTIATING RE-ENUMERATION OF USB 3.0 COMPATIBLE DEVICES - Methods, physical computer-readable media, and devices are provided that allow re-enumeration to be initiated on a USB 3.0-compatible device. The method includes establishing a connection with a host, transmitting an indicator from the device to the host to cause a Link Training and Status State Machine (LTSSM) of the host to move from active state (U0) to one of SS.Inactive and RX.Detect, synchronizing the device with the host, and presenting a new configuration of the device to the host. | 04-04-2013 |
20130083608 | 1T SMART WRITE - The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value. | 04-04-2013 |
20130082719 | Sensor Patterns With Reduced Noise Coupling - A capacitive sense array configured to improve noise immunity in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements disposed in straight parallel lines along a first axis of the capacitive sense array. A second set of sense elements is disposed in crooked paths about a second axis of the capacitive sense array. The first and second sets form a capacitive sense array that includes crooked sense paths in at least one of the axes of the sense array. | 04-04-2013 |
20130076643 | Methods and Apparatus to Associate a Detected Presence of a Conductive Object - A method and apparatus determine a plurality of attribute values of a first detected presence, determine another plurality of attribute values of a second detected presence, and associate the first detected presence with the second detected presence based on the plurality of attribute values and the other plurality of attribute values. | 03-28-2013 |
20130076375 | CAPACITANCE SENSING CIRCUITS, METHODS AND SYSTEMS HAVING CONDUCTIVE TOUCH SURFACE - A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes. | 03-28-2013 |
20130038339 | METHODS AND APPARATUS TO DETECT A PRESENCE OF A CONDUCTIVE OBJECT - A method and apparatus determine a plurality of regions, each of the plurality of regions having a detected change in capacitance value that meets or exceeds a threshold value. In an embodiment, the method and apparatus fit a shape to the plurality of regions and determine another region, the other region being within the fitted shape and not having the detected change in capacitance value that meets or exceeds the threshold value. The method and apparatus may assign an assigned change in capacitance value to the other region. | 02-14-2013 |
20130021291 | QUADRATURE SIGNAL RECEIVER USING SYNCHRONIZED OSCILLATOR - A system comprises a processing device, a signal generator to generate a first signal and a single receiver to receive a second signal from a capacitive sense array. The single receiver is configured to process the second signal for stylus sensing of a stylus proximate to the capacitive sense array in a first mode of operation and to process the second signal for touch sensing of a passive touch object proximate to the capacitive sense array in a second mode of operation. The second signal is unsynchronized with the first signal. | 01-24-2013 |
20130015868 | CAPACITANCE SENSING CIRCUITS, METHODS AND SYSTEMS HAVING GROUND INSERTION ELECTRODES - A capacitance sensing system can include a plurality of transmit (TX) electrodes disposed in a first direction; a plurality of first electrodes disposed in a second direction and coupled to the TX electrodes by a mutual capacitance, and coupled to a capacitance sense circuit when at least one TX electrode receives a transmit signal; and a plurality of second electrodes structures, interspersed with the first electrodes and coupled to a ground node at least while the one TX electrode receives the transmit signal. | 01-17-2013 |
20130015798 | REDUCED ELETROMAGNETIC INTERFERENCE FOR PULSE-WIDTH MODULATION - A method and apparatus to drive a load using a pulse-width modulated (PWM) signal and spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a constant duty cycle for the load. | 01-17-2013 |
20120320385 | OPTICAL NAVIGATION MODULE WITH CAPACITIVE SENSOR - Optical navigation modules and methods of operating the same to sense relative movement between the optical navigation module and a tracking surface are provided. In one embodiment, the optical navigation module comprises: (i) a light source to illuminate at least a portion of a surface relative to which the optical navigation module is moved; (ii) an integrated circuit (IC) including a photo-detector array (PDA) to detect a light pattern propagated onto the PDA from the surface, and a signal processor to translate changes in the light pattern propagated onto the PDA into data representing motion of the optical navigation module relative to the surface; and (iii) a substrate to which the light source and IC are mounted, the substrate including an aperture in a light path between the surface and the PDA. Other embodiments are also disclosed. | 12-20-2012 |
20120286800 | CAPACITANCE SENSOR WITH SENSOR CAPACITANCE COMPENSATION - A capacitance sensing circuit may include a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode, and a current mirror that generates a mirror current based on the sensor current. Based on the mirror current, a measurement circuit generates an output signal representative of a capacitance of the capacitive sensor electrode. | 11-15-2012 |
20120268142 | CAPACITIVE PANEL SCANNING WITH REDUCED NUMBER OF SENSING CIRCUITS - Embodiments described herein provide capacitive sensor devices and methods for operating capacitive sensor devices. A first number of electrodes on the capacitive sensor array is activated. A signal is received from each of the first number of electrodes with a second number of receiver circuits on a controller associated with the capacitive sensor array. The first number is greater than the second number. It is determined if an object is proximate the capacitive sensor array based on the signals received from the first number of electrodes. | 10-25-2012 |
20120256869 | ACTIVE INTEGRATOR FOR A CAPACITIVE SENSE ARRAY - An active integrator for sensing capacitance of a touch sense array is disclosed. The active integrator is configured to receive from the touch sense array a response signal having a positive portion and a negative portion. The response signal is representative of a presence or an absence of a conductive object on the touch sense array. The active integrator is configured to continuously integrate the response signal. | 10-11-2012 |
20120256642 | SINGLE LAYER TOUCH SENSOR - Embodiments described herein provide capacitance sensing devices and methods for forming such devices. The capacitance sensing devices include a substrate having a central and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors are coupled to the insulating material. Each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors. | 10-11-2012 |
20120256638 | NOISE DETECTION FOR A CAPACITANCE SENSING PANEL - An embodiment of a method for detecting noise for a capacitance sensing panel may comprise generating an input signal based on a noise signal, performing a series of measurements for measuring capacitances from a capacitive sensor sensitive to the noise signal, and controlling timing for at least one of the subconversions based on the input signal. | 10-11-2012 |
20120255167 | SINGLE LAYER TOUCH SENSOR - Embodiments for constructing capacitance sensing devices include, but are not limited to, forming a plurality of electrodes on a central portion of a substrate, the substrate comprising a central portion and an outer portion, forming a first plurality of conductors on the substrate, each of the first plurality of conductors being connected to and extending from at least one of the plurality of electrodes, and forming an insulating material on the outer portion of the substrate and at least partially over some of the first plurality of conductors. The constructing also includes forming a second plurality of conductors on the insulating material, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to at least some of the first plurality of conductors and is insulated from the others of the first plurality of conductors. | 10-11-2012 |
20120243301 | MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE - A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein. | 09-27-2012 |
20120230367 | TEMPERATURE SENSOR WITH DIGITAL BANDGAP - A system comprises a temperature sensor generate multiple base-emitter voltage signals by sequentially providing various currents to a transistor, and a system controller to determine a differential voltage signal according to the multiple base-emitter voltage signals, the differential voltage signal proportional to an environmental temperature associated with the transistor. | 09-13-2012 |
20120229417 | Two Prong Capacitive Sensor Pattern - One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element capacitively coupled with each of the first plurality of sensor elements. The second sensor element may further comprise a first main trace and a second main trace, where the first main trace and the second main trace intersect each of the first plurality of sensor elements, and where each of the main traces cross at least one of a plurality of unit cells associated with the second sensor element. The second sensor element may also comprise a connecting subtrace electrically coupled to both the first main trace and the second main trace, and within each unit cell, at least one primary subtrace branching away from the first main trace or the second main trace. | 09-13-2012 |
20120227259 | SINGLE LAYER TOUCH SENSOR - Embodiments described herein provide capacitance sensing devices and methods for forming such devices. The capacitance sensing devices include a substrate having a central and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors are coupled to the insulating material. Each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors. | 09-13-2012 |
20120217982 | Capacitive Sensing Button On Chip - An embodiment of an integrated circuit device may comprise an integrated circuit package, a sensor element attached within the integrated circuit package, a capacitance sensor coupled with the sensor element and situated within the integrated circuit package, wherein the capacitance sensor is configured to measure a capacitance of the sensor element, and an output pin positioned at the exterior of the integrated circuit package, wherein the output pin is configured to carry a signal based on the measured capacitance of the sensor element. | 08-30-2012 |
20120213027 | METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY - A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's. | 08-23-2012 |
20120200524 | NOISE FILTERING DEVICES, SYSTEMS AND METHODS FOR CAPACITANCE SENSING DEVICES - A capacitance sensing system can filter noise that presents in a subset of electrodes in the proximity of a sense object (i.e., finger). A capacitance sensing system can include a sense network comprising a plurality of electrodes for generating sense values; a noise listening circuit configured to detect noise on a plurality of the electrodes; and a filtering circuit that enables a filtering for localized noise events when detected noise values are above one level, and disables the filtering for localized noise events when detected noise values are below the one level. | 08-09-2012 |
20120200307 | COMPENSATION CIRCUIT FOR A TX-RX CAPACITIVE SENSOR - A capacitive sensor may include a transmit electrode and a receive electrode capacitively coupled with the transmit electrode. A capacitance sensing circuit senses a capacitance between the transmit and receive electrodes by applying a signal to the transmit electrode and rectifying a signal induced at the receive electrode. A compensation circuit reduces the effect of a mutual and parasitic capacitances of the transmit and receive electrode pair by adding a compensation signal to the rectified signal. | 08-09-2012 |
20120200229 | MUTLI-STRING LED CURRENT CONTROL SYSTEM AND METHOD - Embodiments described herein provide a LED lighting system and method. A transformer has a primary winding and a secondary winding. A plurality of LED strings are coupled to the secondary winding of the transformer. At least one switch is coupled to at least one of the plurality of LED strings. A controller is coupled to the at least one switch and configured to control the operation of the at least one switch such that current flows through the plurality of LED strings in an alternating manner. | 08-09-2012 |
20120188826 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 07-26-2012 |
20120188163 | CELLULAR COMMUNICATION DEVICE WITH WIRELESS POINTING DEVICE FUNCTION - A method and apparatus receive first input through a touch screen and communicate over a cellular network responsive to the first input. The method and apparatus receive second input through the touch screen and use the second input to control, through a wireless network other than the cellular network, an image displayed on a screen of a second device. | 07-26-2012 |
20120182073 | Apparatus and Method for Programmable Power Management in a Programmable Analog Circuit Block - An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block. | 07-19-2012 |
20120176854 | STATE-MONITORING MEMORY ELEMENT - Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage. | 07-12-2012 |
20120166700 | SPECIALIZED UNIVERSAL SERIAL BUS CONTROLLER - An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB. | 06-28-2012 |
20120154324 | Predictive Touch Surface Scanning - A method for locating a conductive object at a touch-sensing surface may include detecting a first resolved location for the conductive object at the touch-sensing surface based on a first scan of the touch-sensing surface, predicting a location for the conductive object, and determining a second resolved location for the conductive object by performing a second scan of a subset of sensor elements of the touch-sensing surface, wherein the subset of sensor elements is selected based on the predicted location of the conductive object. | 06-21-2012 |
20120139620 | SUPPLY REGULATED CHARGE PUMP SYSTEM - An apparatus and a method for maintaining an output voltage of a charge pump circuit near a target voltage is disclosed. A regulated supply voltage is generated based on the output voltage of the charge pump. The regulated supply voltage is applied to a voltage input to the charge pump circuit and to a voltage input of a clock driver that provides a regulated clock signal to the charge pump circuit. | 06-07-2012 |
20120133611 | Asymmetric Sensor Pattern - An embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace that intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to a corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. The capacitive sensor array may further comprise a plurality of open zones, where each of the plurality of open zones is staggered relative to an adjacent open zone. | 05-31-2012 |
20120113718 | 5T HIGH DENSITY NVDRAM CELL - A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line. | 05-10-2012 |
20120105362 | SYNCHRONIZING A STYLUS WITH A CAPACITIVE SENSE ARRAY - A system and method for tracking a stylus on a capacitive sense array. The system comprising the capacitive sense array configured to detect a presence of the stylus, a processing device to generate a synchronization signal, and a transmitter to transmit the synchronization signal to the stylus to synchronize the stylus to the capacitive sense array. The system further comprises a magnetic antenna configured to inductively transmit the synchronization signal to the stylus, wherein the magnetic antenna is disposed around the outer edges of the capacitance sense array, according to an embodiment of the invention. | 05-03-2012 |
20120105361 | CAPACITIVE STYLUS WITH PALM REJECTION - A system comprising a sensing device and a capacitive sense array configured to detect a presence of a passive touch object and a stylus where the capacitive sense array receives a transmit signal from the stylus via capacitive coupling. The system further comprising a processing device configured to determine the stylus location on the capacitive sense array based on the transmit signal and to synchronize the stylus to the capacitive sense array. | 05-03-2012 |
20120098783 | Flexible Capacitive Sensor Array - A method for detecting force applied to a capacitive sensor array and compensating for coordinate inaccuracy due to force includes receiving a plurality of capacitance measurements from the capacitive sensor array, where the plurality of capacitance measurements includes a first capacitance measurement and a second capacitance measurement, and detecting pressure on the capacitive sensor array based on a comparison between the first capacitance measurement and the second capacitance measurement. | 04-26-2012 |
20120096301 | MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK - An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain. | 04-19-2012 |
20120086666 | Force Sensing Capacitive Hybrid Touch Sensor - A method for detecting a magnitude of force applied to a capacitive sensor array may comprise receiving a plurality of capacitance measurements affected by a contact at a touch-sensing surface, and determining a magnitude of a force applied to the touch-sensing surface at a location of the contact based on the location of the contact and a capacitance measurement of the first plurality of capacitance measurements. | 04-12-2012 |
20120084470 | Utilitzing USB Resources - At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port. | 04-05-2012 |
20120078441 | WIRELESS LOCATING AND MONITORING SYSTEM - A wireless tracking device including a positioning system for determining a location of the device and a processor connected to the positioning system. The wireless tracking device further including a wireless radio connected to the processor for transmitting the location of the device across a wireless area network. | 03-29-2012 |
20120068964 | CAPACITIVE STYLUS FOR A TOUCH SCREEN - A system comprising a sensing device and a capacitive sense array configured to track the position of a stylus and synchronize the capacitive sense array to the stylus transmit signal. The system is configured to track the position of both a stylus and a passive touch object. The system is further configured to track the position of the stylus using self capacitance sensing and track the position of the passive touch object using mutual capacitance sensing. The system further configured to modulate the stylus transmit signal to include additional data to support additional stylus functions. | 03-22-2012 |
20120046104 | Method and Apparatus For Sensing the Force With Which a Button is Pressed - An example method includes measuring a capacitance of an actuator and a conductive element when, responsive to a force applied to the actuator, the actuator is coupled to a reference voltage and deformed such that surface area of the actuator proximate to the conductive element increases. The example method includes determining the force applied to the actuator based on the measured capacitance. | 02-23-2012 |
20120044201 | APPARATUS AND METHODS FOR DETECTING A CONDUCTIVE OBJECT AT A LOCATION - A method and apparatus to detect a conductive object at a location determines a capacitance variation of a first sensor element and a capacitance variation of a second sensor element. The method and apparatus detects a touch at a first location if the capacitance variation of the first sensor element is greater than a reference value and the capacitance variation of the second sensor element is not greater than the reference value. The method and apparatus detects the touch at a second location if the capacitance variation of the first sensor element is not greater than the reference value and the capacitance variation of the second sensor element is greater than the reference value. The method and apparatus detects the touch at a third location if the capacitance variation of the first sensor element and the capacitance variation of the second sensor element are both greater than the reference value. | 02-23-2012 |
20120044199 | Capacitance Scanning Proximity Detection - A method and apparatus for scanning a first set of electrodes of a capacitive sense array using a first sensing mode to identify a presence of an object in proximity to the capacitive sense array, where scanning using the first sensing mode identifies objects not in physical contact with the capacitive sense array. The first set of electrodes is scanned using a second sensing mode to determine a location of the object in relation to the capacitive sense array, where rescanning using the second sensing mode determines locations of objects in physical contact with the capacitive sense array. | 02-23-2012 |
20120044198 | SELF SHIELDING CAPACITANCE SENSING PANEL - A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source. | 02-23-2012 |
20120044197 | Capacitive Sensor Arrangement - An example capacitive sensor arrangement includes an integrated member residing within an interior region of a capacitive sensor element. The capacitive sensor element has a first resistance to a flow of current and the integrated member has a second resistance to the flow of current that is less than the first resistance. | 02-23-2012 |
20120044193 | TRACE PATTERN FOR TOUCH-SENSING APPLICATION - One embodiment of a capacitive sensor array comprises a plurality of row sensor elements including a first row sensor element, a plurality of column sensor elements including a first column sensor element, and a plurality of unit cells, wherein a first unit cell contains an intersection between the first row sensor element and the first column sensor element, and wherein a ratio between 1) a boundary length between the first row sensor element and the first column sensor element within the first unit cell and 2) a perimeter of the first unit cell is greater than √{square root over (2)}/2. | 02-23-2012 |
20120044188 | Method and Apparatus for Identification of Touch Panels - A method for configuring a touchscreen controller may include identifying a model of a touchscreen by measuring a capacitance or resistance of at least one element integrated in the touchscreen, identifying the model of the touchscreen based on the measured capacitance or resistance, and configuring the touchscreen controller based on the identified model of the touchscreen. | 02-23-2012 |
20120044187 | Capacitive Touch Screen - One embodiment in accordance with the invention can include a capacitive touch screen. The capacitive touch screen includes a substantially transparent substrate and a plurality of electrodes formed on the substantially transparent substrate. The plurality of electrodes are substantially parallel in a first direction and each of the plurality of electrodes includes a layer of light altering material. | 02-23-2012 |
20120044150 | Touch Identification for Multi-Touch Technology - A method of operating a touch-sensing surface may include determining a first plurality of contact locations including a first contact location, determining a second plurality of contact locations including a second contact location, performing a first correlation process for correlating the second contact location with the first contact location when the number of contacts is less than or equal to a first threshold number, and performing a second correlation process for correlating the second contact location with the first contact location when the number of contacts is greater than a second threshold number. | 02-23-2012 |
20120043977 | Mutual Capacitance Sensing Circuits, Methods and Systems - A capacitance sensing system may include a first selection circuit that couples N electrodes of a first electrode set to a capacitance sense circuit; and a second selection circuit that couples M electrodes of a second electrode set, substantially simultaneously, to a signal generator circuit as a group to induce current in the N electrodes by mutual capacitance between the M and N electrodes; wherein N is at least one, and M>N. | 02-23-2012 |
20120043971 | METHODS AND CIRCUITS FOR MEASURING MUTUAL AND SELF CAPACITANCE - A capacitance measurement circuit for measuring self and mutual capacitances may include a first electrode capacitively coupled with a second electrode, a first plurality of switches coupled with the first electrode, and a second plurality of switches coupled with the second electrode, wherein, during a first operation stage, the first plurality of switches is configured to apply a first initial voltage to the first electrode and the second plurality of switches is configured to apply a second initial voltage to the second electrode, and wherein, during a second operation stage, the first plurality of switches is configured to connect the first electrode with a measurement circuit, and the second plurality of switches is configured to connect the second electrode with a constant voltage. | 02-23-2012 |
20120043970 | Automatic Tuning of a Capacitive Sensing Device - An apparatus, system and method for automatically tuning a capacitance sensor based on comparisons of measured capacitance values to expected values and ranges of values is described. Measured capacitance is converted to a digital value with a capacitance to digital converter. The digital value is use to adjust the range, resolution, baseline offset and thresholds of the capacitance sensor according to logic executed by a controller and stored in programs in a memory. | 02-23-2012 |
20120043141 | Toothed Slider - An example method includes measuring a capacitance variation of a first conductive element and a capacitance variation of a second conductive element. The example method includes calculating a centroid position through the measured capacitance variation of the first conductive element and the measured capacitance variation of the second conductive element. A conductive sub-element of the first conductive element may be interleaved with a conductive sub-element of the second conductive element. The conductive sub-element of the first conductive element and the conductive sub-element of the second conductive element may each have a varying width. | 02-23-2012 |
20120043140 | TOUCH SENSING - In one embodiment, an apparatus comprises a plurality of capacitors, each having a first electrode and a second electrode. The apparatus includes charging circuitry coupled to the first electrodes and sensing circuitry coupled to the second electrodes, the sensing circuitry configured to detect changes in capacitance across the capacitors responsive to movement of an input object relative to the apparatus. Interpolating circuitry identifies which one of the capacitors is nearest to the input object according to the detected capacitance changes. | 02-23-2012 |
20120014202 | MEMORY DEVICE AND METHOD - A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period | 01-19-2012 |
20120008378 | MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE - A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks. | 01-12-2012 |
20120005693 | Development, Programming, and Debugging Environment - A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code. | 01-05-2012 |
20110316756 | ANTENNA WITH MULTIPLE FOLDS - An example antenna includes a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion. The intermediate portion includes multiple folds. The second end portion includes a first conductor to couple with a communication interface of a communication module, and a second conductor to couple with a ground. | 12-29-2011 |
20110316567 | Lattice Structure for Capacitance Sensing Electrodes - One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace. | 12-29-2011 |
20110308955 | INTEGRATED SHIELDING FOR WAFER PLATING - A semiconductor substrate carrier for use during wet chemical processing may comprise a conductive flange to couple the carrier with processing equipment, a frame coupled with the conductive flange, where the frame is configured to hold a semiconductor substrate, and an integrated shield coupled with the frame. The integrated shield is configured to alter an electric field near at least a portion of a surface of the semiconductor substrate during the wet chemical processing. | 12-22-2011 |
20110304354 | UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING - A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other mirco-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O. | 12-15-2011 |
20110283057 | Microcontroller Programmable System on a Chip - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 11-17-2011 |
20110261489 | ESD TRIGGER FOR SYSTEM LEVEL ESD EVENTS - A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal. | 10-27-2011 |
20110252162 | MEMORY SYSTEM AND METHOD - In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller. | 10-13-2011 |
20110248153 | Optical Navigation System Having A Filter-Window To Seal An Enclosure Thereof - An optical navigation system and method are provided. In one embodiment, the system includes: (i) a coherent light source to emit light to illuminate a portion of a finger; and (ii) a detector to receive light reflected from the portion of the finger, the detector including a speckle-based sensor configured to sense movement of the finger relative to the detector based on changes in a complex interference pattern created by the light reflected from the portion of the finger. Other embodiments are also described. | 10-13-2011 |
20110234264 | Load Driver - A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage. | 09-29-2011 |
20110208329 | CLOCK SYNTHESIS SYSTEMS, CIRCUITS AND METHODS - A clock synthesis system may include a feed forward divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronous pulse; a modulator that modulates the select signal in response to at least a difference value; a multiplier circuit that frequency multiplies the reference clock to generate an output clock; and a timing circuit that generates the difference value in response to the source clock and synchronous pulse. | 08-25-2011 |
20110176647 | CIRCUIT, SYSTEM AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER - An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains. | 07-21-2011 |
20110169814 | DIGITAL DRIVING CIRCUITS, METHODS AND SYSTEMS FOR LIQUID CRYSTAL DISPLAY DEVICES - A method may include controlling a display device in at least first mode by varying a correlation between display driver signals applied across display segments within the display device; wherein the display driver signals vary between substantially only two levels, and a display segment is activated when an average voltage magnitude across the segment over a time period exceeds a threshold value. | 07-14-2011 |
20110156724 | CAPACITANCE MEASUREMENT SYSTEMS AND METHODS - A first capacitor and a second capacitor are charged until voltage at the second capacitor settles to a settling voltage. While charging, the first capacitor is alternately switched between a current source and ground. When the settling voltage is reached, charging of the first capacitor is halted. The second capacitor continues to be charged until voltage at the second capacitor reaches a reference voltage. The amount of time it takes for the settling voltage to reach the reference voltage corresponds to a measure of capacitance on the first capacitor. | 06-30-2011 |
20110115729 | METHOD AND APPARATUS FOR REDUCING COUPLED NOISE INFLUENCE IN TOUCH SCREEN CONTROLLERS - A method and apparatus for reducing influence of noise for touch screen controllers employing noise listening synchronization, delay lines, filtering and sensing selected touch screen electrodes. | 05-19-2011 |
20110026519 | DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP - An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data. | 02-03-2011 |
20110025629 | Dynamic Mode Switching for Fast Touch Response - A method of operating a touch-sensing surface may include determining a presence of at least one conductive object at the touch-sensing surface by performing a search measurement of a first set of sensor elements of the touch-sensing surface, and in response to determining the presence of the at least one conductive object, determining a location of the at least one conductive object by performing a tracking measurement of a second set of sensor elements of the touch-sensing surface. | 02-03-2011 |
20110018829 | MUTUAL CAPACITANCE SENSING ARRAY - A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. Each sensor element comprises an outer frame including a conductive material. A cavity is formed within the interior of the outer frame. | 01-27-2011 |
20110016374 | SERIAL INTERFACE DEVICES, SYSTEMS AND METHODS - A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values. | 01-20-2011 |
20100312952 | Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory - A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request. | 12-09-2010 |
20100293325 | MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-SPEED ACCESS OF MEMORY MODULES - A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed. | 11-18-2010 |
20100287571 | DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT - A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code. | 11-11-2010 |
20100281145 | AUTONOMOUS CONTROL IN A PROGRAMMABLE SYSTEM - A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously of the microcontroller. | 11-04-2010 |
20100275173 | Model For a Hardware Device-Independent Method of Defining Embedded Firmware for Programmable Systems - A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution. | 10-28-2010 |
20100264836 | LIGHTING ASSEMBLY, CIRCUITS AND METHODS - A circuit in accordance with one embodiment of the invention can include an LED drive circuit that may isolate a sense circuit from a supply voltage in a passive mode, and maintain a predetermined voltage difference between the sense circuit and the supply voltage in an operational mode. | 10-21-2010 |
20100228926 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 09-09-2010 |
20100228908 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 09-09-2010 |
20100156804 | MULTI-FINGER SUB-GESTURE REPORTING FOR A USER INTERFACE DEVICE - Touch sensor methods, devices and systems are disclosed. One embodiment of the present invention pertains to a method for reporting a sub-gesture on a touch sensing surface, e.g., laid over a display of a user interface device. The method comprises determining a number of fingers simultaneously placed on the touch sensing surface. The method also comprises periodically sampling respective position data of the fingers moving along the touch sensing surface and calculating event data based on the position data, wherein each of the event data includes a geometric shape associated with the number of fingers and a centroid of the geometric shape. The method further comprises forwarding the event data to a presentation layer of application of the user interface device, where the application is configured to identify a gesture based on a subset of the event data. | 06-24-2010 |
20100149115 | FINGER GESTURE RECOGNITION FOR TOUCH SENSING SURFACE - Touch sensor methods, devices and systems are disclosed. One embodiment of the present invention pertains to a method comprising monitoring a finger movement along a touch sensing surface based on position data of a finger touching the touch sensing surface, where the position data is obtained by locating a position of a force applied by the finger in a coordinate of the touch sensing surface. In addition, the method comprises generating direction data associated with the finger movement if the finger movement travels for more than a threshold distance. Furthermore, the method comprises determining a finger gesture which corresponds to the finger movement using a lookup table having multiple preconfigured finger gestures based on the direction data. | 06-17-2010 |
20100123411 | COMPENSATION METHOD AND CIRCUIT FOR LINE REJECTION ENHANCEMENT - An embodiment of the present invention is directed to a method and circuit to control light emitting diode (LED) output. The method includes receiving a line voltage signal which powers a lighting circuit comprising an LED and determining an adjustment of a threshold based on a variation of the line voltage signal and/or a controller delay or other practical controller limitation or imperfection. The method further includes dynamically adjusting a threshold or other reference of a controller which controls a switch of said lighting circuit for compensating for line variations to maintain a substantially uniform LED current. | 05-20-2010 |
20100082861 | MEMORY SYSTEM AND METHOD - In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component. | 04-01-2010 |
20100079384 | CAPACITANCE TOUCH SCREEN - A touch screen is described. The touch screen is configured to have an array of conductive, optically transmissive sensor elements coupled to sensor circuitry. The sensor elements are disposed over a display to have a single layer of conductive, optically transmissive material positioned over pixels of the display. | 04-01-2010 |
20100079090 | Light Emitting Driver Circuit with Compensation and Method - A light emitting driver circuit, system, and method are provided. The driver circuit system and method can be implemented in various ways. An embodiment includes a bypass circuit which diverts current from the LEDs whenever a switch coupled to the LEDs incurs residual current when turned off. In an additional or alternative embodiment, the residual current can be sensed and the amount of residual current used to trigger fetching of a compensation value. That compensation value can change a dimming function forwarded to the switch in order to compensate for, offset, or substantially eliminate the residual current through that switch. | 04-01-2010 |
20100079083 | SYSTEM AND METHOD FOR REMOTE CONTROL LIGHTING - Remote lighting control methods, devices and systems are disclosed. One embodiment of the present invention pertains to a light device. The light device includes a light source for emitting light and a control circuit for setting an intensity level of the light source based on receipt of control data via a power line when the light device is electrically coupled to the power line. The control data is generated in response to user input to an input panel of a remote lighting control module for the light device. In addition, the light device comprises a unique address associated with a region on the input panel. | 04-01-2010 |
20100079074 | Light Emitting Driver Circuit with Bypass and Method - A light emitting driver circuit, system, and method are provided. The driver circuit system and method can be implemented in various ways. An embodiment includes a bypass circuit which diverts current from the LEDs whenever a switch coupled to the LEDs incurs residual current when turned off. In an additional or alternative embodiment, the residual current can be sensed and the amount of residual current used to trigger fetching of a compensation value. That compensation value can change a dimming function forwarded to the switch in order to compensate for, offset, or substantially eliminate the residual current through that switch. | 04-01-2010 |
20100074028 | Memory Architecture Having Two Independently Controlled Voltage Pumps - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 03-25-2010 |
20100073090 | CURRENT SENSE AMPLIFIER - A system includes a current sense amplifier to receive an input voltage based on a sense current provided to load circuitry. The current sense amplifier is configured to generate an output voltage from the input voltage based, at least in part, on one or more reconfigurable characteristics of the current sense amplifier. The system also includes a microcontroller to compare the output voltage from the current sense amplifier to one or more programmable thresholds. The microcontroller is configured to direct a current controller to regulate the sense current provided to the load circuitry according to the comparison. | 03-25-2010 |
20100067551 | Method for Providing Packet Framing in a DSSS Radio System - An improved method of framing data packets in a direct sequence spread spectrum (DSSS) system that uses one pseudo-noise code (PN-Code) to frame the packet with a start-of-packet (SOP) and end-of-packet (EOP) indicator, and a different PN-Code to encode the data payload. Furthermore, the SOP is represented by the framing PN-Code, and the EOP is represented by the inverse of the framing PN-Code. This method creates a robust framing system that enables a DSSS system to operate with a low threshold of detection, thus maximizing transmission range even in noisy environments. Additionally, the PN-Code used for the SOP and EOP indicators can be used to indicate an acknowledgement response. | 03-18-2010 |
20090267534 | LIGHT EMITTING DIODE ASSEMBLY - A circuit in accordance with one embodiment of the invention can include a light emitting diode (LED) assembly comprising a plurality of LED channels that are controlled independently with a switch mode driver. The circuit also includes N+1 wires coupled to said LED assembly, where N is equal to the number of said plurality of LED channels of said LED assembly. | 10-29-2009 |
20090230289 | Pixel Structure Having Shielded Storage Node - A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node. | 09-17-2009 |
20090170449 | CELLULAR COMMUNICATION DEVICE WITH WIRELESS POINTING DEVICE FUNCTION - A device includes a first wireless transceiver adapted to communicate over a cellular network, a second wireless transceiver adapted to communicate over a local network separate from the cellular network, and a mechanism adapted to report movement information to a computer via the second wireless transceiver. The mechanism is optionally an optical sensor reporting relative position information. The device is operable as both a cellular communication device and a computer pointing device. A button of the device is adapted to operate as a mouse button, and optionally, in some modes, controls operation of the cellular communication device. The second wireless transceiver optionally uses Universal Serial Bus protocol. The device optionally transfers files via the second wireless transceiver. In some usage scenarios, the device and a separate wireless pointing device communicate with a same computer and are used to operate an application, such as a gaming application. | 07-02-2009 |
20090160627 | POWER LINE COMMUNICATON FOR ELECTRICAL FIXTURE CONTROL - We disclose an apparatus capable of receiving control command data for one or more electrical fixtures and modulating an alternating current by modifying firing phase angles to transmit the data corresponding to the control commands via a power line transmitting the alternating current. | 06-25-2009 |
20090160369 | CONTROLLING A LIGHT EMITTING DIODE FIXTURE - One embodiment in accordance with the invention can include a circuit for controlling a light emitting diode (LED) lighting fixture via a power line. The circuit can include a power switch coupled to the power line and is for outputting a firing angle. Additionally, the circuit can include a control circuit coupled to the power switch and is for implementing firing angle control of the power switch. Furthermore, the circuit can include a translator coupled to receive the firing angle and for mapping the firing angle to a function of the LED lighting fixture. | 06-25-2009 |
20090160368 | Phase Control for Hysteretic Controller - A driver circuit, and light emitting system and method are provided. The driver circuit includes possibly a controller and a phase detector coupled to produce an intermittent output proportional to a value of an input relative to upper and lower threshold values, and a difference between the input signal, which is the intermittent output signal, and a reference value. The light emitting system can include a switch and at least one light emitting device coupled to the switch. The driver circuit can be coupled to forward the intermittent output signal to the switch that is active in proportion to current level through the light emitting device, rising and falling between the modifiable upper and lower threshold values. | 06-25-2009 |
20090153152 | COMPENSATION CIRCUIT FOR A TX-RX CAPACITIVE SENSOR - A capacitive sensor may include a transmit electrode and a receive electrode capacitively coupled with the transmit electrode. A capacitance sensing circuit senses a capacitance between the transmit and receive electrodes by applying a signal to the transmit electrode and rectifying a current waveform induced at the receive electrode. A compensation circuit reduces the effect of a mutual and parasitic capacitances of the transmit and receive electrode pair by adding a compensation current to the rectified current. | 06-18-2009 |
20090055592 | DIGITAL SIGNAL PROCESSOR CONTROL ARCHITECTURE - A system includes a control store memory populated with data path instructions indexable by control store addresses and jump addresses. The system further includes a control state machine to provide at least one control store address and at least one jump address to the control store memory, wherein the control store memory is configured to identify one or more data path instructions for both the control store address and the jump address. | 02-26-2009 |
20090024828 | METHOD AND SYSTEM OF DIGITAL SIGNAL PROCESSING - A system comprises a system interface to receive one or more instruction sets from a microcontroller and to receive digital data to be processed. The system further comprises a controller that is reconfigurable according to the one or more instruction sets received by the system interface. The system further comprises a data path device to perform digital filtering operations on the digital data as directed by the controller according to the reconfiguration of the controller by the one or more instruction sets. | 01-22-2009 |