Cray Inc. Patent applications |
Patent application number | Title | Published |
20160026553 | COMPUTER WORKLOAD MANAGER - A computer-implemented method includes: scheduling computing jobs; processing data by executing the computing jobs; arranging the data in a file system; managing the arranging the data by monitoring a performance parameter of the file system and extracting information about the scheduling, and tuning one of the arranging and the scheduling based on the performance parameter and the information about the scheduling. An article of manufacture includes a computer-readable medium storing signals representing instructions for a computer program executing the method. | 01-28-2016 |
20150089468 | ASSISTING PARALLELIZATION OF A COMPUTER PROGRAM - A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables. | 03-26-2015 |
20140281663 | RE-FORMING AN APPLICATION CONTROL TREE WITHOUT TERMINATING THE APPLICATION - A reconnection system re-forms a control tree for an application that is executed in parallel without terminating execution of the application. The reconnection system detects when a node of a control tree has failed and directs the nodes that have not failed to reconnect to effect the re-forming of the control tree without the failed node and without terminating the application. Upon being directed to reconnect, a node identifies new child nodes that are to be its child nodes in the re-formed control tree. The node maintains the existing connection with each of its current child nodes that is also a new child node, terminates the existing connection with each of its current child nodes that is not also a new child node, establishes a new connection with any new child node that is not a current child node, and directs each new child node to reconnect. | 09-18-2014 |
20140280282 | INTERFACE BETWEEN SPARQL SYSTEMS AND A NON-SPARQL SYSTEM - A method and system for interfacing SPARQL front ends of SPARQL systems to a non-SPARQL system is provided. A translated SPARQL (“tSPARQL”) system inputs a translated SPARQL query, generates commands for a non-SPARQL system based on the tSPARQL query, and provides those commands to the non-SPARQL system for executing the SPARQL query corresponding to the tSPARQL query. The tSPARQL system translates the tSPARQL query into commands that are provided to a non-SPARQL query engine for executing the SPARQL query represented by the tSPARQL query. When the tSPARQL system receives results of the commands, it provides the results to the SPARQL front end. | 09-18-2014 |
20140251574 | COOLING SYSTEMS AND HEAT EXCHANGERS FOR COOLING COMPUTER COMPONENTS - Computer systems having heat exchangers for cooling computer components are disclosed herein. The computer systems include a computer cabinet having an air inlet, an air outlet spaced apart from the air inlet, and a plurality of computer module compartments positioned between the air inlet and the air outlet. The air inlet, the air outlet, and the computer module compartments define an air flow path through the computer cabinet. The computer systems also include a heat exchanger positioned between two adjacent computer module compartments. The heat exchanger includes a plurality of heat exchange elements canted relative to the air flow path. | 09-11-2014 |
20140244657 | DYNAMIC GRAPH SYSTEM FOR A SEMANTIC DATABASE - A method and system in a computer system for dynamically providing a graphical representation of a data store of entries via a matrix interface is disclosed. A dynamic graph system provides a matrix interface that exposes to an application program a graphical representation of data stored in a data store such as a semantic database storing triples. To the application program, the matrix interface represents the graph as a sparse adjacency matrix that is stored in compressed form. Each entry of the data store is considered to represent a link between nodes of the graph. Each entry has a first field and a second field identifying the nodes connected by the link and a third field with a value for the link that connects the identified nodes. The first, second, and third fields represent the rows, column, and elements of the adjacency matrix. | 08-28-2014 |
20140140341 | INCREASINGLY MINIMAL BIAS ROUTING - A system and algorithm configured to generate diversity at the traffic source so that packets are uniformly distributed over all of the available paths, but to increase the likelihood of taking a minimal path with each hop the packet takes. This is achieved by configuring routing biases so as to prefer non-minimal paths at the injection point, but increasingly prefer minimal paths as the packet proceeds, referred to herein as Increasing Minimal Bias (IMB). | 05-22-2014 |
20140081934 | DYNAMIC UPDATES TO A SEMANTIC DATABASE USING FINE-GRAIN LOCKING - A system for updating an index into a tuple table of tuples is provided. An indexing system updates an index into a tuple table using fine-grain locking of the index. The index includes a values table with an entry for each index value of an index field that references a value-tuple table that includes, for each tuple with the index value, a row that identifies a tuple of the tuple table with that indexed value. After a new tuple is added to the tuple table with a value, the index is updated by locking the entry in the values table, updating the value-tuple table for the value, and then unlocking the entry. When the index is accessed for locating tuples with a value, the accessor locks the entry in the values table for the value, uses the value-tuple table to locate the tuples, and unlocks the entry. | 03-20-2014 |
20130229768 | COMPUTER CABINETS HAVING PROGRESSIVE AIR VELOCITY COOLING SYSTEMS AND ASSOCIATED METHODS OF MANUFACTURE AND USE - Computer cabinets, such as supercomputer cabinets, having progressive air velocity cooling systems are described herein. In one embodiment, a computer cabinet includes an air mover positioned beneath a plurality of computer module compartments. The computer module compartments can be arranged in tiers with the computer modules in each successive tier being positioned closer together than the computer modules in the tier directly below. The computer cabinet can also include one or more shrouds, flow restrictors, and/or sidewalls that further control the direction and/or speed of the cooling air flow through the cabinet. | 09-05-2013 |
20130128459 | TRANSVERSE COOLING SYSTEM AND METHOD - A system and method for cooling a plurality of electronics cabinets having horizontally positioned electronics assemblies. The system includes at least one blower configured to direct air horizontally across the electronics assemblies, and at least one intercooler configured to extract heat from the air flow such that the system is room neutral, meaning that the ambient temperature remains constant during operation of the system. A plurality of chassis backplanes and power supplies may also include an intercooler, wherein the intercoolers are electronically controlled such that the system is room neutral. | 05-23-2013 |
20120311537 | PERFORMANCE VISUALIZATION INCLUDING HIERARCHICAL DISPLAY OF PERFORMANCE DATA - Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node. | 12-06-2012 |
20120265883 | MULTIPLE OVERLAPPING BLOCK TRANSFERS - A computerized system comprising multiple processing nodes, a physical channel configured to transfer data between a memory local to a processing node and a network target remote from the processing node, and a block transfer engine configured to allocate multiple virtual channels to the physical channel and to transfer multiple address-overlapping blocks of data simultaneously using the virtual channels. | 10-18-2012 |
20120246544 | METHOD AND APPARATUS FOR MEMORY READ-REFRESH, SCRUBBING AND VARIABLE-RATE REFRESH - A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described. | 09-27-2012 |
20120221830 | CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR - A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. | 08-30-2012 |
20120198470 | COMPACT NODE ORDERED APPLICATION PLACEMENT IN A MULTIPROCESSOR COMPUTER - A multiprocessor computer system comprises a plurality of nodes, wherein the nodes are ordered using a snaking dimension-ordered numbering. An application placement module is operable to place an application in nodes with preference given to nodes ordered near one another. | 08-02-2012 |
20120176711 | METHOD AND APPARATUS FOR SWITCHED ELECTROSTATIC DISCHARGE PROTECTION - One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting. | 07-12-2012 |
20120144065 | TABLE-DRIVEN ROUTING IN A DRAGONFLY PROCESSOR INTERCONNECT NETWORK - A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables. | 06-07-2012 |
20120144064 | PROGRESSIVE ADAPTIVE ROUTING IN A DRAGONFLY PROCESSOR INTERCONNECT NETWORK - A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to adaptively route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more of network congestion information from neighboring routers and failed network link information from neighboring routers. | 06-07-2012 |
20120072704 | "OR" BIT MATRIX MULTIPLY VECTOR INSTRUCTION - A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system. | 03-22-2012 |
20120059938 | DIMENSION-ORDERED APPLICATION PLACEMENT IN A MULTIPROCESSOR COMPUTER - A multiprocessor computer system comprises a plurality of nodes, wherein the nodes are ordered using dimension-ordered numbering. An application placement module is operable to place an application in nodes with preference given to nodes ordered near one another. | 03-08-2012 |
20110271259 | SYSTEMS AND METHODS FOR DEBUGGING APPLICATIONS USING DUAL CODE GENERATION - Systems and methods provide a debugger that debugs code using two versions of code, an optimized and a debuggable version of object code for subroutines, methods or functions. The debugger causes the appropriate version of the code to be executed depending on whether debug commands have been applied with respect to particular subroutines, methods or functions. | 11-03-2011 |
20110150136 | DUTY CYCLE COMPENSATING DIGITAL DATA RECEIVER - A data communication receiver includes an interface operable to receive at least one incoming data signal. A transition point tracker is operable to track data transition points of the data signal, and a data sampler is operable to sample the data signal at a desired sampling point between transition points. | 06-23-2011 |
20110051724 | FLEXIBLE ROUTING TABLES FOR A HIGH-RADIX ROUTER - A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table. | 03-03-2011 |
20110010522 | MULTIPROCESSOR COMMUNICATION PROTOCOL BRIDGE BETWEEN SCALAR AND VECTOR COMPUTE NODES - A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor interconnect network and the indirect processor interconnect network. | 01-13-2011 |
20100324854 | MEMORY-DAUGHTER-CARD-TESTING METHOD AND APPARATUS - A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions. | 12-23-2010 |
20100318979 | VECTOR ATOMIC MEMORY OPERATION VECTOR UPDATE SYSTEM AND METHOD - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which may have recurring data points. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector resident in memory, wherein the virtual interior loop includes a vector atomic memory operation (AMO) instruction. | 12-16-2010 |
20100318831 | GLOBAL CLOCK VIA EMBEDDED SPANNING TREE - In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes. | 12-16-2010 |
20100318774 | PROCESSOR INSTRUCTION GRADUATION TIMEOUT - A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates. | 12-16-2010 |
20100318773 | INCLUSIVE "OR" BIT MATRIX COMPARE RESOLUTION OF VECTOR UPDATE CONFLICT MASKS - A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array. | 12-16-2010 |
20100318769 | USING VECTOR ATOMIC MEMORY OPERATION TO HANDLE DATA OF DIFFERENT LENGTHS - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts. | 12-16-2010 |
20100318764 | SYSTEM AND METHOD FOR MANAGING PROCESSOR-IN-MEMORY (PIM) OPERATIONS - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed at least in part in a vector atomic memory operation (AMO) functional unit attached to memory. If so, the compiled code includes vector AMO instructions. | 12-16-2010 |
20100318751 | Multiple error management in a multiprocessor computer system - An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size. | 12-16-2010 |
20100318747 | ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING - An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory. | 12-16-2010 |
20100318741 | MULTIPROCESSOR COMPUTER CACHE COHERENCE PROTOCOL - A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L | 12-16-2010 |
20100318626 | EXTENDED FAST MEMORY ACCESS IN A MULTIPROCESSOR COMPUTER SYSTEM - A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address. | 12-16-2010 |
20100318591 | INCLUSIVE OR BIT MATRIX TO COMPARE MULTIPLE CORRESPONDING SUBFIELDS - A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern. | 12-16-2010 |
20100306489 | ERROR MANAGEMENT FIREWALL IN A MULTIPROCESSOR COMPUTER - A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory. | 12-02-2010 |
20100199121 | ERROR MANAGEMENT WATCHDOG TIMERS IN A MULTIPROCESSOR COMPUTER - A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management. | 08-05-2010 |
20100185897 | FAULT TOLERANT MEMORY APPARATUS, METHODS, AND SYSTEMS - Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error. | 07-22-2010 |
20100122261 | APPLICATION LEVEL PLACEMENT SCHEDULER IN A MULTIPROCESSOR COMPUTING ENVIRONMENT - A multiprocessor computer system program scheduler comprises an application-level placement scheduler module that is operable to receive requests for resources in a multiprocessor computer system, operable to manage processing node resource availability data; operable to reserve processing node resources for specific applications based on the received requests for resources and the processing node resource availability data; and operable to reclaim processing node resources reserved for specific applications upon application termination. | 05-13-2010 |
20100122254 | BATCH AND APPLICATION SCHEDULER INTERFACE LAYER IN A MULTIPROCESSOR COMPUTING ENVIRONMENT - A multiprocessor computer system batch system interface between an application level placement scheduler and one or more batch systems comprises a predefined protocol operable to convey processing node resource request and availability data between the application level placement scheduler and the one or more batch systems. | 05-13-2010 |
20100121904 | RESOURCE RESERVATIONS IN A MULTIPROCESSOR COMPUTING ENVIRONMENT - A multiprocessor computer system reservation system comprises a plurality of processing nodes that each comprise computing resources such as processors and local memory. A resource reservation module is operable to reserve computing resources for a batch application such that the computing resources reserved for the batch application will be available to the application throughout a reservation period. The resource reservation module is operable to communicate computing resource reservation information with a placement scheduler that is operable to distribute application processes across processing nodes, and is operable to provide computing resource availability information to a batch system and to place reservations for a batch system that comprises a mechanism for scheduling batch jobs across processing nodes. | 05-13-2010 |
20100115236 | HIERARCHICAL SHARED SEMAPHORE REGISTERS - A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores. | 05-06-2010 |
20100115234 | CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR - A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. | 05-06-2010 |
20100115228 | Unified address space architecture - A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space. | 05-06-2010 |
20100095255 | SYSTEM AND METHOD FOR VERIFYING RACE-DRIVEN REGISTERS - Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have not used a property instance entering the expired state, and computing a new solution space based on the current solution space and target transition. | 04-15-2010 |
20100017513 | MULTIPLE OVERLAPPING BLOCK TRANSFERS - This document describes, among other things, a computerized system comprising a plurality of processing nodes, a physical channel configured to transfer data between a memory local to a processing node and a network target remote from the processing node, and a block transfer engine configured to allocate a plurality of virtual channels to the physical channel and to transfer a plurality of address-overlapping blocks of data simultaneously using the virtual channels. | 01-21-2010 |
20090292900 | MULTIPROCESSOR NODE CONTROL TREE - Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other attached processor nodes in parallel. | 11-26-2009 |
20090268358 | METHOD AND APPARATUS FOR SWITCHED ELECTROSTATIC DISCHARGE PROTECTION - One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting. | 10-29-2009 |
20090238257 | LONELY PULSE COMPENSATION - An apparatus comprising a transmission line, a receiver circuit, and a high pass filter circuit coupled between the transmission line and a receiver circuit input. The receiver circuit is configured to receive a data signal over the transmission line at a first data rate. The high pass filter circuit is connected between the transmission line and a receiver circuit input and has a corner frequency that is less than approximately the first data rate and is greater or equal to than approximately one-half the second data rate. The second data rate is an effective data rate caused by an expected data pattern on the transmission line. Other devices, systems, and methods are disclosed. | 09-24-2009 |
20090041049 | LOAD BALANCING FOR COMMUNICATIONS WITHIN A MULTIPROCESSOR COMPUTER SYSTEM - In a system having a N output ports, wherein N is an integer greater than one, a method of distributing packets across the plurality of output ports. A packet having two or more fields is received and a first number is computed as a function of one or more of the plurality of fields. A second number is computed that is modulo base N of the first number and an output port is selected as a function of the second number. | 02-12-2009 |
20090028172 | SPECULATIVE FORWARDING IN A HIGH-RADIX ROUTER - A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet. | 01-29-2009 |
20080313621 | SCALAR CODE REDUCTION USING SHORTEST PATH ROUTING - This document discusses, among other things, a system and method computing the shortest path expression in a loop having a plurality of expressions. Candidate expressions in the loop are identified and partitioned into sets. A cost matrix is computed as a function of the sets. Paths are found through the cost matrix and, if there are cycles in the paths, the cycles are broken. One or more shortest path expressions are generated as a function of the paths and one or more of the expressions in the loop are replaced with the shortest path expressions. | 12-18-2008 |
20080285598 | PHASE ROTATOR FOR DELAY LOCKED LOOP BASED SERDES - An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed. | 11-20-2008 |
20080285562 | FLEXIBLE ROUTING TABLES FOR A HIGH-RADIX ROUTER - A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table. | 11-20-2008 |
20080266807 | ELECTRONIC ASSEMBLY WITH EMI SHIELDING HEAT SINK - An example electronic assembly includes a substrate that has a first surface and a second surface. The first surface of the substrate includes a grounding ring. The electronic assembly further includes one or more electronic components that are mounted on the first surface of the substrate such that the grounding ring at least partially surrounds the electronic components(s). A heat sink engages the electronic component(s) and the grounding ring in order provide cooling and EMI shielding to the electronic components(s). In some embodiments, the grounding ring surrounds the entire electronic components(s) and the heat sink engages the entire grounding ring, although in other embodiments, the grounding ring may partially surround the electronic components(s) and/or the heat sink may engage just a portion of the grounding ring. | 10-30-2008 |