Cadence Design Systems, Inc. Patent applications |
Patent application number | Title | Published |
20160070841 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING HIGH CURRENT CARRYING INTERCONNECTS IN ELECTRONIC DESIGNS - Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type. | 03-10-2016 |
20160063171 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SCHEMATIC DRIVEN, UNIFIED THERMAL AND ELECTROMAGNETIC INTERFERENCE COMPLIANCE ANALYSES FOR ELECTRONIC CIRCUIT DESIGNS - Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes. | 03-03-2016 |
20140282415 | METHOD AND SYSTEM FOR DEBUGGING A PROGRAM - A computer-implemented method and system for debugging a program is disclosed. The method may include obtaining data on inter-component calls of a call chain of an execution run of the program between segments of Multilanguage software components of the program, the data relating to the identity of the Multilanguage software components in which these segments are included and an order in which the segments are called in the call chain. The method may further include obtaining a user selection relating to one of the segments of the Multilanguage software components that were called in the call chain. The method may also include invoking a debugger designed for debugging the software component of the Multilanguage software components that includes the selected segment and displaying a user interface of that debugger on a display device. | 09-18-2014 |
20140282414 | METHOD AND SYSTEM FOR DEBUGGING OF A PROGRAM - A computer implemented method for debugging of a program may include parsing a code segment of the program, the code segment invoking one or a plurality of execution events during an execution of the program to derive a plurality of questions, each relating to an execution event of said one or a plurality of execution events, based on the parsing of the code segment and on information recorded during the execution of the program. The method may also include selecting one of the questions as a current question. The method may further include presenting in a user interface the current question with one or a plurality of causes related to the current question, and one or a plurality of other questions of said one or a plurality of questions for selection by the user. | 09-18-2014 |
20140281730 | DEBUGGING SESSION HANDOVER - A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software debugging tool of a step of the operation as a event of interest, collecting data related to that event of interest. A unique identifier is assigned to the collected data. Access to the collected data is enabled for a second user of the software debugging tool. | 09-18-2014 |
20140258948 | DESIGN SYNTHESIS OF CLOCK GATED CIRCUIT - Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements. | 09-11-2014 |
20140258947 | FINITE-STATE MACHINE ENCODING DURING DESIGN SYNTHESIS - Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic respectively associated with states of the FSM, and/or the like. The values may also be determined based on power considerations, such as estimated power consumption for the circuit. The design synthesis may include generation of a structural description of the encoded FSM. | 09-11-2014 |
20140237440 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 08-21-2014 |
20140215422 | METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING - A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process. | 07-31-2014 |
20140173541 | Method and Apparatus for Verifying Debugging of Integrated Circuit Designs - Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful, and that errors in operation will not recur. In another aspect, the invention provides a facility that enables the IP provider to demonstrate to an IP consumer that a repaired IP component will work under a sufficiently broad set of circumstances, without that demonstration revealing the provider's proprietary IP to the consumer. | 06-19-2014 |
20140173539 | Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs - Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP. | 06-19-2014 |
20140172347 | GENERATION OF A RANDOM SUB-SPACE OF THE SPACE OF ASSIGNMENTS FOR A SET OF GENERATIVE ATTRIBUTES FOR VERIFICATION COVERAGE CLOSURE - System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a device under test using the generated random sub-space of the space of assignments for a set of generative variables. | 06-19-2014 |
20140123094 | PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN - A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure. | 05-01-2014 |
20140096099 | GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS - A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform. | 04-03-2014 |
20140089875 | Method and Apparatus for Optimizing Memory-Built-In-Self Test - Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results. | 03-27-2014 |
20140089874 | Method and Apparatus for Optimizing Memory-Built-In-Self Test - Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results. | 03-27-2014 |
20140082421 | CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TESTING OF AN INTEGRATED CIRCUIT - A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module. | 03-20-2014 |
20140068527 | SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK - The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer. | 03-06-2014 |
20140067358 | DETERMINING AN OPTIMAL GLOBAL QUANTUM FOR AN EVENT-DRIVEN SIMULATION - An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against expected events. Based on the comparison detecting at least one of the expected events being absent in the sequence chart, providing the optimal global quantum value as being smaller than the provisional global quantum value. Based on the comparison detecting no difference between the events in the sequence chart and the expected events, providing the optimal global quantum value as being larger than the provisional global quantum value. | 03-06-2014 |
20130338991 | INTEGRATED CIRCUIT SIMULATION USING ANALOG POWER DOMAIN IN ANALOG BLOCK MIXED SIGNAL - A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to simulate operation of the analog representation; wherein simulating the digital representation includes transitioning the defined power domain between supply values from among the multiple respective supply values; wherein simulating the analog representation includes periodically storing in a storage location a power supply value currently in use during digital simulation of the digital representation; and wherein simulating the analog representation includes using the stored currently in use power supply value to supply voltage to the analog representation. | 12-19-2013 |
20130326440 | ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION - For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks. | 12-05-2013 |
20130298092 | METHOD AND SYSTEM FOR AUTOMATICALLY ESTABLISHING HIERARCHICAL PARAMETERIZED CELL (PCELL) DEBUGGING ENVIRONMENT - A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools. | 11-07-2013 |
20130290834 | SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS - A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. According to an embodiment, the layouts or documents may be connected via an interposer. | 10-31-2013 |
20130246900 | SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS - A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. Upon selection of any active element or predefined net list, the elements physically or logically connected to the selected element or net list may be highlighted in the active documents, listed, or otherwise identified. An inter-document net list may identify connections between existing net lists in multiple documents. | 09-19-2013 |
20130227350 | RECORDING AND PLAYBACK OF TRACE AND VIDEO LOG DATA FOR PROGRAMS - Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized. | 08-29-2013 |
20130191793 | DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN - A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment. | 07-25-2013 |
20130097572 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 04-18-2013 |
20130080126 | SHOOTING PNOISE CIRCUIT SIMULATION WITH FULL SPECTRUM ACCURACY - An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results. | 03-28-2013 |
20130024623 | METHOD AND APPARATUS FOR HIGH SPEED CACHE FLUSHING IN A NON-VOLATILE MEMORY - An invention is provided for performing flush cache in a non-volatile memory. The invention includes maintaining a plurality of free memory blocks within a non-volatile memory. When a flush cache command is issued, a flush cache map is examined to obtain a memory address of a memory block in the plurality of free memory blocks within the non-volatile memory. The flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks. Then, a cache block is written to a memory block at the obtained memory address within the non-volatile memory. In this manner, when a flush cache command is received, the flush cache map allows cache blocks to be written to free memory blocks in the non-volatile memory without requiring a non-volatile memory search for free blocks or requiring erasing of memory blocks storing old data. | 01-24-2013 |
20130018644 | System and Method For Controlling Granularity of Transaction Recording In Discrete Event SimulationAANM Motel; VincentAACI GrenobleAACO FRAAGP Motel; Vincent Grenoble FRAANM Bhatnagar; NeetiAACI San JoseAAST CAAACO USAAGP Bhatnagar; Neeti San Jose CA USAANM Frazier; George F.AACI LawrenceAAST KSAACO USAAGP Frazier; George F. Lawrence KS USAANM LaRue, JR.; William W.AACI LeawoodAAST KSAACO USAAGP LaRue, JR.; William W. Leawood KS US - A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity setting, a group of consecutive transactions is grouped into a super transaction, and the statistical values representing the super transaction are recorded to represent the group of transactions. The super transactions are visualized in a visualization tool for analyzing the performance of the model. | 01-17-2013 |
20120317533 | SYSTEM AND METHOD FOR DYNAMICALLY INJECTING ERRORS TO A USER DESIGN - A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition. | 12-13-2012 |
20120316858 | METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR - A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. | 12-13-2012 |
20120311513 | METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRONIC DESIGN - Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design. | 12-06-2012 |
20120272201 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20120272200 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20120266110 | DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN - A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment. | 10-18-2012 |
20120254818 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA - Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs. | 10-04-2012 |
20120253732 | METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR - A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. | 10-04-2012 |
20120227024 | LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD - According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present. | 09-06-2012 |
20120221990 | METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure. | 08-30-2012 |
20120221988 | METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) associated with an electronic circuit design. Embodiments may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the circuit design and generating a three dimensional adaptive mesh model that is based upon, at least in part, the extracted EM model. Numerous other features are also within the scope of the present disclosure. | 08-30-2012 |
20120221312 | METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure. | 08-30-2012 |
20120198411 | METHOD AND APPARATUS FOR AMS SIMULATION OF INTEGRATED CIRCUIT DESIGN - A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media. | 08-02-2012 |
20120198405 | METHOD AND APPARATUS FOR AMS SIMULATION OF INTEGRATED CIRCUIT DESIGN - A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media. | 08-02-2012 |
20120159113 | System and Method For Providing Compact Mapping Between Dissimilar Memory Systems - A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space. | 06-21-2012 |
20120151422 | ROBUST DESIGN USING MANUFACTURABILITY MODELS - The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products. | 06-14-2012 |
20120131524 | METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY - A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels. | 05-24-2012 |
20120102440 | METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems. | 04-26-2012 |
20120096414 | METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems. | 04-19-2012 |
20120089954 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty. | 04-12-2012 |
20120047434 | METHOD TO PREVIEW AN UNDO/REDO LIST - A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document. | 02-23-2012 |
20120030644 | METHOD AND SYSTEM FOR IMPLEMENTING STACKED VIAS - The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element. | 02-02-2012 |
20120023471 | METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation. | 01-26-2012 |
20120023467 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness. | 01-26-2012 |
20120023465 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 01-26-2012 |
20120022846 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools. | 01-26-2012 |
20110314432 | METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS - Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking. | 12-22-2011 |
20110276908 | SYSTEM AND METHOD FOR MANAGEMENT OF CONTROLS IN A GRAPHICAL USER INTERFACE - Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within the scope for the control. If so, resources of the different instance are referenced to be shared for use with the control and new resources are not created for the control. If no different instance exists within the scope, new resources for the control are created and stored. The window and the controls in the GUI are displayed. | 11-10-2011 |
20110270556 | METHOD AND SYSTEM FOR IMPLEMENTING CIRCUIT SIMULATORS - A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided. | 11-03-2011 |
20110252389 | REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL SLACK - A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow. | 10-13-2011 |
20110239177 | METHOD AND SYSTEM FOR APPROXIMATE PLACEMENT IN ELECTRONIC DESIGNS - Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function. | 09-29-2011 |
20110239168 | INTELLIGENT PATTERN SIGNATURE BASED ON LITHOGRAPHY EFFECTS - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 09-29-2011 |
20110219352 | METHOD AND SYSTEM FOR SEARCHING AND REPLACING GRAPHICAL OBJECTS OF A DESIGN - Searching and/or replacing graphical objects of a design using a computer system. In one aspect of the inventions, a method includes searching a graphical design for all matching instances of graphical objects that match a search pattern. A graphical replacement pattern is received and caused to be displayed based on user input, and the matching instances in the graphical design are replaced with the graphical replacement pattern. At least one result of the replacement of the matching instances is caused to be displayed on a display device. | 09-08-2011 |
20110219341 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR INTERACTIVE CHECKING FOR DOUBLE PATTERN LITHOGRAPHY VIOLATIONS - Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively. | 09-08-2011 |
20110219320 | METHOD AND SYSTEM FOR SEARCHING FOR GRAPHICAL OBJECTS OF A DESIGN - Searching for graphical objects of a design using a computer system. In one aspect of the inventions, a method includes defining a graphical search pattern based on input received from a user in a graphical interface displayed on a display device, where the search pattern is a graphical object and is defined with a plurality of types of characteristics. The graphical design is searched for all matching instances of graphical objects in the design that match the search pattern and match the characteristics specified by the search pattern. At least one of the matching instances is caused to be displayed on the display device as a result of the searching. | 09-08-2011 |
20110192994 | SYSTEM AND METHOD OF ELECTRON BEAM WRITING - A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information. | 08-11-2011 |
20110173582 | METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTRACTION IN A MULTI-TECHNOLOGY ENVIRONMENT - A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object. | 07-14-2011 |
20110167400 | METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN AN IC DESIGN - Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern. | 07-07-2011 |
20110161900 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20110161899 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED-SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20110154276 | METHOD AND SYSTEM FOR OPTIMALLY PLACING AND ASSIGNING INTERFACES IN A CROSS-FABRIC DESIGN ENVIRONMENT - A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface. | 06-23-2011 |
20110153289 | METHOD AND SYSTEM FOR SPECIFYING SYSTEM LEVEL CONSTRAINTS IN A CROSS-FABRIC DESIGN ENVIRONMENT - A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format. | 06-23-2011 |
20110153288 | METHOD AND SYSTEM FOR OPTIMALLY CONNECTING INTERFACES ACROSS MUTIPLE FABRICS - A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface. | 06-23-2011 |
20110153272 | METHODS AND SYSTEMS FOR HIGH SIGMA YIELD ESTIMATION USING REDUCED DIMENSIONALITY - For an integrated circuit associated with a first plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples. A second plurality of parameters is selected that has fewer parameters than the first plurality of parameters. The failed samples are clustered in the space of the second plurality of parameters using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters. The method further includes selecting a second plurality of samples using the composite probability distribution function and performing a second test to determine an outcome for each of the second plurality of samples. A failure probability can then be computed. | 06-23-2011 |
20110153271 | METHODS AND SYSTEMS FOR HIGH SIGMA YIELD ESTIMATION - For an integrated circuit associated with a plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples, and clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters. The method further includes selecting a second plurality of samples using the composite probability distribution function and performing a second test to determine an outcome for each of the second plurality of samples. A failure probability can then be computed. | 06-23-2011 |
20110133806 | INTEGRATED CLOCK GATING CELL FOR CIRCUITS WITH DOUBLE EDGE TRIGGERED FLIP-FLOPS - A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state. | 06-09-2011 |
20110131544 | VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES BASED ON A CURSOR - Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed cursor, and wherein no labels are displayed outside of the zone. | 06-02-2011 |
20110131543 | VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES - Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more shapes describing the connections of the shapes. | 06-02-2011 |
20110131525 | VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES BASED ON USER ZONE OF FOCUS - Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor on the display device. Labels are displayed on the display device, each label associated with a different displayed shape. One or more of the labels are displayed within a zone of focus of eyes of a user of the graphical interface and one or more of the labels are displayed outside the zone of focus, where the labels displayed in the zone of focus are displayed differently than the labels displayed outside the zone of focus. | 06-02-2011 |
20110113393 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY SIDEWALL-IMAGE TRANSFER - Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions. | 05-12-2011 |
20110099530 | SPINE SELECTION MODE FOR LAYOUT EDITING - Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking. | 04-28-2011 |
20110093826 | METHOD AND SYSTEM FOR MODEL-BASED ROUTING OF AN INTEGRATED CIRCUIT - Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations. | 04-21-2011 |
20110083114 | METHOD AND SYSTEM FOR RE-USING DIGITAL ASSERTIONS IN A MIXED SIGNAL DESIGN - A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process. | 04-07-2011 |
20110078651 | METHOD AND SYSTEM FOR TEST REDUCTION AND ANALYSIS - Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller and therefore easier to understand and debug. | 03-31-2011 |
20110066997 | MODELING AND SIMULATING DEVICE MISMATCH FOR DESIGNING INTEGRATED CIRCUITS - A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles. | 03-17-2011 |
20110066995 | ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS - A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media. | 03-17-2011 |
20110061034 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 03-10-2011 |
20110046767 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREPARING MULTIPLE LAYERS OF SEMICONDUCTOR SUBSTRATES FOR ELECTRONIC DESIGNS - Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks. | 02-24-2011 |
20110014786 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY DOUBLED PATTERNING - Disclosed are a method, apparatus, and program product for routing an electronic design using double patenting that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patenting, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning. | 01-20-2011 |
20100333050 | ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION - For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks. | 12-30-2010 |
20100325597 | GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects. | 12-23-2010 |
20100325595 | METHOD AND SYSTEM PERFORMING RC EXTRACTION - A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes. | 12-23-2010 |
20100324878 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING HOTSPOT DETECTION, REPAIR, AND OPTIMIZATION OF AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction. | 12-23-2010 |
20100321055 | IC TEST VECTOR GENERATOR FOR SYNCHRONIZED PHYSICAL PROBING - Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times. | 12-23-2010 |
20100287493 | METHOD AND SYSTEM FOR VIEWING AND EDITING AN IMAGE IN A MAGNIFIED VIEW - Viewing and editing of a displayed image in a magnified view. In one aspect, a method for displaying a magnified image using a computer system includes causing a display on a display device of a first image, and causing a display on the display device of a second image that is a portion of the first image. The second image has a zoomed-in view that is a closer view of the portion than in the first image. At least one edit is caused to the second image in response to at least one input received at the second image. | 11-11-2010 |
20100205575 | Methods, Systems, and Computer-Program Products for Item Selection and Positioning Suitable for High-Altitude and Context Sensitive Editing of Electrical Circuits - Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user. | 08-12-2010 |
20100205572 | ADAPTIVE MESH RESOLUTION IN ELECTRIC CIRCUIT SIMULATION AND ANALYSIS - An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size. | 08-12-2010 |
20100169853 | Method and System for Implementing Graphical Analysis of Hierarchical Coverage Information Using Treemaps - An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach provides relative comparison of coverage of the nodes and allows the user to identify whether there is any missing coverage, and if so, whether the missing coverage evenly balanced. This information is very useful for the decision made by the user regarding overall coverage and steps to be taken to improve the coverage. | 07-01-2010 |
20100162191 | METHOD AND SYSTEM FOR PERFORMING CELL MODELING AND SELECTION - An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design. | 06-24-2010 |
20100162189 | SYSTEM AND METHOD FOR SYNTHESIS REUSE - A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints. | 06-24-2010 |
20100162188 | METHOD AND SYSTEM PERFORMING BLOCK-LEVEL RC EXTRACTION - A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography. | 06-24-2010 |
20100161303 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND USER INTERFACE FOR PERFORMING POWER INFERENCE - An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to allow the user to interact with and modify the design information related to power management. | 06-24-2010 |
20100153924 | Method and System for Performing Software Verification - Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a tightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from the verification tool that is external to the virtual machine provides the stimulation that incrementally operates and changes the state of the virtual machine. The stimulus is created and coverage is collected from outside the virtual machine by first stopping the virtual machine, depositing stimulus, and then reading coverage directly from the virtual machine memory while the machine is stopped. | 06-17-2010 |
20100153888 | Method and System for Implementing a User Interface with Ghosting - An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the user's manipulation of the object until a legal configuration is achieved. The improved approach provides a visual representation that corresponds to the expected end result, but is also be useful to track the user's actions if there is a violation. | 06-17-2010 |
20100148836 | Contention-Free Level Converting Flip-Flops for Low-Swing Clocking - The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function. | 06-17-2010 |
20100125822 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING INTERACTIVE CROSS-DOMAIN PACKAGE DRIVEN I/O PLANNING AND PLACEMENT OPTIMIZATION - Disclosed are a method, a system, and a computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization of an electronic circuit design. In some embodiments, the method identifies an object on a first EDA tool session, determines a drop location for the first object based on a tentative location in the first EDA tool session, places the first object at the drop location, and adjusts the drop location via a second EDA tool session, performs placement or routing of a portion of the design. The method or the system further comprises placing a corresponding first object in the second EDA tool session, initiating the second EDA tool session object move in the first EDA tool session, determining whether a constraint is satisfied. | 05-20-2010 |
20100122228 | METHOD AND SYSTEM FOR CONDUCTING DESIGN EXPLORATIONS OF AN INTEGRATED CIRCUIT - Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations. | 05-13-2010 |
20100115487 | METHOD AND SYSTEM FOR SCHEMATIC-VISUALIZATION DRIVEN TOPOLOGICALLY-EQUIVALENT LAYOUT DESIGN IN RFSiP - An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout. | 05-06-2010 |
20100115478 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty. | 05-06-2010 |
20100115477 | OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMING INFORMATION - A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow. | 05-06-2010 |
20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS - An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data. | 05-06-2010 |
20100083200 | METHODS, SYSTEM, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING COMPACT MANUFACTURING MODEL IN ELECTRONIC DESIGN AUTOMATION - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design. | 04-01-2010 |
20100070941 | Achieving Clock Timing Closure in Designing an Integrated Circuit - Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist. | 03-18-2010 |
20100070934 | Analysis of Physical Systems via Model Libraries Thereof - A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and used to determine a corresponding characteristic of the physical system without repeating the numerical solution method originally used to create the model. Instead, a mapping may be applied to the storable model to seamlessly obtain the characteristic upon request. | 03-18-2010 |
20100058129 | TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS - A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage. | 03-04-2010 |
20100050146 | METHOD AND SYSTEM FOR ROUTING - Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers. | 02-25-2010 |
20100050143 | METHOD AND SYSTEM FOR ROUTING - Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers. | 02-25-2010 |
20100049935 | MANAGEMENT OF VERY LARGE STREAMING DATA SETS FOR EFFICIENT WRITES AND READS TO AND FROM PERSISTENT STORAGE - A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that indicates a location in persistent memory of a different respective packet in the packet sequence that was transferred to persistent memory prior to such providing of the respective pointer. | 02-25-2010 |
20100037196 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING INCREMENTAL PLACEMENT IN ELECTRONICS DESIGN - Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing the perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, the abstract flow is computed, the target locations of various electronic components to be placed are identified, the relative ordering of electronic components are determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using the incremental placement technique while minimizing the perturbation impact or the total quadratic movement of instances. In some embodiments, an augmented or incremental clumping technique based data structure is utilized for rapid and substantially exact perturbation prediction of effects of local incremental placement operations. | 02-11-2010 |
20100037136 | Context-Aware Non-Linear Graphic Editing - A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context. | 02-11-2010 |
20100004902 | SPINE SELECTION MODE FOR LAYOUT EDITING - Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking. | 01-07-2010 |
20090326854 | TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS - A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence. | 12-31-2009 |
20090320002 | METHOD AND SYSTEM FOR TESTING AND ANALYZING USER INTERFACES - A system and method is described in which the state of the art in automated software applications is significantly improved. According to some approaches, interface testing is implemented and based upon a verification language and a verification environment. The system and method support the concepts of constrained random test generation, coverage, constrained random generation, and dynamic checks. | 12-24-2009 |
20090319976 | METHOD AND SYSTEM PERFORMING CIRCUIT DESIGN PREDICTIONS - Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions). | 12-24-2009 |
20090271167 | PEAK POWER DETECTION IN DIGITAL DESIGNS USING EMULATION SYSTEMS - A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium. | 10-29-2009 |
20090210202 | METHOD AND APPARATUS FOR SIMULATING QUASI-PERIODIC CIRCUIT OPERATING CONDITIONS USING A MIXED FREQUENCY/TIME ALGORITHM - Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships between the values at the distinct time points and the values the reference time points. The process also finds a second set of relationships between the values at the distinct time points and the values at the reference time points. The process then combines the first and second sets of relationships to establish a system of nonlinear equations in terms of the values at the distinct time points only. By solving the system of nonlinear equations, the process finds simulated responses of the circuit in time domain. The process then converts the simulated circuit responses from time domain to frequency domain. | 08-20-2009 |
20090204931 | Method And Apparatus For Processing Assertions In Assertion-Based Verification of A Logic Design - Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation. | 08-13-2009 |
20090199145 | Method for Accounting for Process Variation in the Design of Integrated Circuits - A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations. | 08-06-2009 |
20090172632 | Method, System, and Computer Program Product for Implementing External Domain Independent Modeling Framework in a System Design - Disclosed are a method, system, and computer program product for implementing external domain independent modeling framework in a system design. In some embodiments, the method or system comprises importing an external model in an external format into the framework while substantially preserving some or all of the interpretation of the external model, determining a internal common representation for the external model within the framework, and displaying or storing the internal common representation in a tangible computer readable medium. In some embodiments, the method or system further comprises validating the accuracy of the internal common representation, determining an analysis or transformation capability for the framework, or outputting a first output model in a second external format. In various embodiments, the method or system requires no external tool compliance. | 07-02-2009 |
20090172628 | Method and System for Utilizing Hard and Preferred Rules for C-Routing of Electronic Designs - An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing. | 07-02-2009 |
20090172626 | METHOD AND SYSTEM FOR VISUAL IMPLEMENTATION OF LAYOUT STRUCTURES FOR AN INTEGRATED CIRCUIT - The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual presentation could be employed to display layout choices during the initial design entry phase for the electronic design. | 07-02-2009 |
20090172625 | METHOD AND MECHANISM FOR PERFORMING CLEARANCE-BASED ZONING - A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects. | 07-02-2009 |
20090172624 | Method and System for Implementing Stacked Vias - The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element. | 07-02-2009 |
20090172623 | METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS - Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking. | 07-02-2009 |
20090172619 | METHOD AND SYSTEM FOR IMPLEMENTING TIMING ANALYSIS AND OPTIMIZATION OF AN ELECTRONIC DESIGN BASED UPON EXTENDED REGIONS OF ANALYSIS - Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process. | 07-02-2009 |
20090172616 | Method, System, and Computer Program Product for Implementing a Direct Measurement Model for an Electronic Circuit Design - Various embodiments of the present invention are generally directed to a method, system, and computer program product for implementing direct measurement model with simulation and calibration of manufacturing process model in the manufacturing of precision devices such as electronic integrated circuits. The method and the system determine the measured measurement result and the direct measurement information and compare the direct measurement information against the other to determine whether to adjust the process models and the empirical parameters thereof. | 07-02-2009 |
20090172042 | Method, System, and Computer Program Product for Implementing a Model Exchange Framework - Disclosed are a method, a system, and a computer program products for implementing model exchange in a system design. In various embodiments, the method or system receives a model exchange request from a client where model exchange request comprises a first synchronization record which comprises a delta of both a program aspect and a data aspect between a system design on the client and a system design on the server, implements the first model exchange request by processing the first model exchange, generates a second synchronization record in response to the first model exchange, transmitting the second synchronization record to the first client by using a fusion technology, and displaying a result of implementing the first model exchange request or storing the result in a tangible computer readable medium. | 07-02-2009 |
20090169114 | INTERPOLATION OF IRREGULAR DATA IN A FINITE-DIMENSIONAL METRIC SPACE IN LITHOGRAPHIC SIMULATION - A method, system, and computer program product for preprocessing a pattern in a library of patterns and querying a preprocessed library of patterns are disclosed. Embodiments for querying a preprocessed library of patterns are disclosed for determining a distance between the representation for the first pattern and the representation for the second pattern, determining whether the distance between the representation for the first pattern and the representation for the second pattern is within the range for the first pattern, and transforming the second pattern with the transformation matrix to provide information about the second pattern. Embodiments for preprocessing a pattern in a library of patterns are disclosed for determining a transformation matrix for the first pattern, determining a range for the first pattern, wherein a distance between a representation for a first pattern and a representation for a second pattern is within the range and the second pattern can be transformed with the transformation matrix to provide information about the second pattern, and associating the range and the transformation matrix with the first pattern. | 07-02-2009 |
20090164968 | Method and System for Implementing Top Down Design and Verification of an Electronic Design - Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design. | 06-25-2009 |
20090150836 | Intelligent Pattern Signature Based on Lithography Effects - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 06-11-2009 |
20090144683 | AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT - An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described. | 06-04-2009 |
20090144681 | AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT - An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described. | 06-04-2009 |
20090144680 | AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT - An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described. | 06-04-2009 |
20090144671 | DESIGNING INTEGRATED CIRCUITS FOR YIELD - Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found. | 06-04-2009 |
20090138524 | METHOD AND SYSTEM FOR ENHANCING SOFTWARE DOCUMENTATION AND HELP SYSTEMS - A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided. | 05-28-2009 |
20090138519 | METHOD AND SYSTEM FOR ENHANCING SOFTWARE DOCUMENTATION AND HELP SYSTEMS - A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided. | 05-28-2009 |
20090119634 | Method and System for Implementing Controlled Breaks Between Features Using Sub-Resolution Assist Features - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems. | 05-07-2009 |
20090119559 | DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS - A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response. | 05-07-2009 |
20090119310 | SAVING AND RESTARTING DISCRETE EVENT SIMULATIONS - Method, system, and computer program product for saving and restarting discrete event simulations are provided. A discrete event simulation of a scenario is performed via a process executing on a system. The process includes one or more application threads. A checkpoint of the process is created at a point in time when a command to save the discrete event simulation of the scenario is received. The checkpoint includes data elements of the process and the one or more application threads of the process that are stored in components of the system at the point in time. These data elements reflect a state of the process and the one or more application threads of the process at the point in time. The checkpoint is saved to one or more files in the system that are usable to later restart the discrete event simulation of the scenario from the point in time. | 05-07-2009 |
20090113369 | REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS - A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element. | 04-30-2009 |
20090113366 | METHOD AND MECHANISM FOR PERFORMING TIMING AWARE VIA INSERTION - A method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster, while the path based method has a better insight of the worst slack/slew for the entire design. | 04-30-2009 |
20090113363 | METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MULTI-STRENGTH SIGNALS FOR VERIFICATION - A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs. | 04-30-2009 |
20090089725 | SYNTHESIS OF ASSERTIONS FROM STATEMENTS OF POWER INTENT - A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data. | 04-02-2009 |
20090089722 | Method and System for Mapping Source Elements to Destination Elements as Interconnect Routing Assignments - Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution. | 04-02-2009 |
20090083685 | METHOD FOR GENERATING OPTIMIZED CONSTRAINT SYSTEMS FOR RETIMABLE DIGITAL DESIGNS - A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit. | 03-26-2009 |
20090083683 | Method and Apparatus for Implementing Communication Between a Software Side and a Hardware Side of a Test Bench in a Transaction-Based Acceleration Verification System - Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are automatically bound to hardware side endpoints of the communication channels during verification based on naming attributes of the transactors and communication channels with respect to the software side and the hardware side of the test bench. | 03-26-2009 |
20090077521 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
20090077520 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
20090077513 | GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects. | 03-19-2009 |
20090077505 | GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects. | 03-19-2009 |
20090064071 | METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS - Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis. | 03-05-2009 |
20090031271 | ROBUST DESIGN USING MANUFACTURABILITY MODELS - The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products. | 01-29-2009 |
20090031261 | CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS - A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits. | 01-29-2009 |
20090013315 | Method and Apparatus for Restructuring a Software Program Hierarchy - Method, apparatus, and computer readable medium for restructuring a software program hierarchy having interface files and implementation files that include the interface files are described. In one example, dependencies between program units in the interface files and the implementation files are determined. The dependencies are represented as a plurality of bit strings. Correlated bitstrings of the plurality of bit strings are clustered into a plurality of partitions. Each of the plurality of partitions is transformed into corresponding program units. New interface files are respectively created having the corresponding program units for each of the plurality of partitions. | 01-08-2009 |
20090007031 | METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS - Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design. | 01-01-2009 |
20080284453 | IC TEST VECTOR GENERATOR FOR SYNCHRONIZED PHYSICAL PROBING - Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times. | 11-20-2008 |
20080270105 | Method and apparatus for controlling power in an emulation system - Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system. | 10-30-2008 |
20080235640 | Method and apparatus for performing static analysis optimization in a design verification system - Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification. | 09-25-2008 |
20080216027 | Electronic Design for Integrated Circuits Based on Process Related Variations - An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined. | 09-04-2008 |
20080203324 | METHOD AND SYSTEM FOR IMPROVEMENT OF DOSE CORRECTION FOR PARTICLE BEAM WRITERS - A method and system for dose correction of a particle beam writer is disclosed. The method and system includes reading a file of writing objects that includes dose intensity, calculating a rate of dose intensity change between adjacent writing objects, selecting a writing object that may need accuracy improvement of dose correction based on the rate of dose intensity change, and improving accuracy of the dose correction of the writing object that is selected and its adjacent objects. | 08-28-2008 |