ATI Technologies ULC Patent applications |
Patent application number | Title | Published |
20160134865 | CONTROLLING POWER CONSUMPTION IN VIDEO ENCODING BASED ON INFORMATION REGARDING STATIC AMOUNT OF AN IMAGE FRAME - An apparatus and methods for controlling power consumption in video encoding obtain, before motion estimation is performed on an image frame to be encoded, information regarding an amount of the image frame to be encoded that is static with respect to a previously encoded image frame. The apparatus and methods adjust power consumption of the video encoder based on the obtained information regarding the amount of the image frame to be encoded that is static. | 05-12-2016 |
20160119619 | METHOD AND APPARATUS FOR ENCODING INSTANTANEOUS DECODER REFRESH UNITS - Method and apparatus for encoding instantaneous decoder refresh (IDR) units are disclosed. The method includes partially encoding an IDR block as a non-IDR block, decoding the partially encoded IDF block to generate a reconstructed IDR block and fully encoding the reconstructed IDF block as an IDR block. In a first pass, an IDR unit is partially encoded (no entropy encoding) using regular encoding parameters of a non-IDR unit in the same picture. The partially-encoded IDR unit is then inverse quantized and inverse transformed to generate a reconstructed video data of the IDR unit. In the second pass, the reconstructed video data of the IDR unit is passed as an input to the prediction module and fully encoded using the IDR settings. The reconstructed IDR unit may be encoded with very high fidelity. | 04-28-2016 |
20160117794 | MODIFYING GRADATION IN AN IMAGE FRAME INCLUDING APPLYING A WEIGHTING TO A PREVIOUSLY PROCESSED PORTION OF THE IMAGE FRAME - An apparatus and methods for modifying gradation in an image frame determine a blend factor indicating a first weighting associated with a previously processed portion of the image frame. The apparatus and methods generate a weighted value associated with a current region of the image frame based on the current region of the image frame and based on applying the first weighting to the previously processed portion of the image frame so as to modify the gradation in the image frame. | 04-28-2016 |
20160037166 | ADAPTIVE SEARCH WINDOW POSITIONING FOR VIDEO ENCODING - A method, system, and computer program product that exploits motion hints associated with rendered video frames. These motion hints are provided to a video encoder to guide a motion-compensation prediction process performed by the video encoder. Specifically, these motion hints can be used to better position a search window in a reference video frame to better capture the motion of a block of pixels in the reference video frame. Because the search window is better positioned in the reference video frame, the memory required to perform the encoding process can be reduced without sacrificing the level of encoded image quality. | 02-04-2016 |
20150363310 | MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM - A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor. | 12-17-2015 |
20150347050 | METHODS AND APPARATUS FOR DIVIDING SECONDARY STORAGE - Methods and apparatus for restricting access by one or more processors to an area of a secondary storage unit are presented herein. The methods and apparatus may comprise an independent programmable storage controller logic that divides a storage area of the secondary storage unit into at least a first area and a second area and controls usage of the areas as at least two virtual secondary storage units such that the processor(s) access the at least two virtual secondary storage units as if accessing at least two physical secondary storage units by selecting one of the at least two virtual secondary storage units as an active virtual secondary storage unit to provide the processor(s) access to the active virtual secondary storage unit based on a secondary storage unit configuration. Each virtual secondary storage unit may contain at least one region of which an access permission setting is modifiable. | 12-03-2015 |
20150346798 | SYSTEM AND METHOD FOR ADJUSTING PERFORMANCE BASED ON THERMAL CONDITIONS WITHIN A PROCESSOR - A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads each of a first thermal design power (TDP) value for the processing units and a second TDP value for a platform housing the semiconductor chip. The power manager determines a ratio of the first TDP value to the second TDP value. Additionally, the power manager determines another ratio of the first TDP value to the calculated power value. Using the measured temperature, the ratios and the calculated power value, the power manager determines a manner to adjust the operating parameters. | 12-03-2015 |
20150339171 | DYNAMIC FEEDBACK LOAD BALANCING - A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating. | 11-26-2015 |
20150324318 | BUS PROTOCOL COMPATIBLE DEVICE AND METHOD THEREFOR - A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link. | 11-12-2015 |
20150286573 | SYSTEM AND METHOD OF TESTING PROCESSOR UNITS USING CACHE RESIDENT TESTING - Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache. | 10-08-2015 |
20150279319 | SPATIAL DITHERING FOR A DISPLAY PANEL - A method, a device, and a non-transitory computer readable medium for performing dithering on an L bit long input data are presented. An M bit long random data is generated, wherein M is a number of least significant bits of the input data. An M bit long frame counter value is added to the random data. The input data is rounded up to L-M most significant bits when the M least significant bits of the input data is greater than the sum of the frame counter value and the random data. The input data is truncated to the L-M most significant bits when the M least significant bits of the input data is less than or equal to the sum of the frame counter value and the random data. | 10-01-2015 |
20150271491 | ENHANCED INTRA PREDICTION MODE SELECTION FOR USE IN VIDEO TRANSCODING - An apparatus and a method for selecting an intra prediction mode for use in video transcoding obtain information from a decoder portion of a video transcoder regarding one or more intra prediction modes used in previously encoding one or more data blocks of a source image. The apparatus and method select an intra prediction mode for encoding a decoded data block corresponding to the one or more data blocks of the source image based on the information obtained from the decoder portion regarding the one or more intra prediction modes used in previously encoding the one or more data blocks of the source image. | 09-24-2015 |
20150194418 | ELECTROSTATIC DISCHARGE EQUALIZER - An integrated circuit including an electrostatic discharge (ESD) equalizer is described. The integrated circuit may include a first ESD protection circuit coupled between a first node and a ground node of the integrated circuit and a second ESD protection circuit coupled between a second node and the ground node. The integrated circuit may also include an ESD equalizer that changes from an impedance of a path between the first node and the second node from a high impedance to a low impedance in response to electrostatic discharge (ESD) through the first node or the second node. | 07-09-2015 |
20150120978 | INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE - The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests. | 04-30-2015 |
20150106916 | LEVERAGING A PERIPHERAL DEVICE TO EXECUTE A MACHINE INSTRUCTION - A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. | 04-16-2015 |
20150100818 | BACK-OFF MECHANISM FOR A PERIPHERAL PAGE REQUEST LOG - A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log. | 04-09-2015 |
20150098507 | MOTION ESTIMATION APPARATUS AND METHOD FOR MULTIVIEW VIDEO - A motion estimation apparatus and method (carried out electronically) provides for encoding of multiview video, such as stereoscopic video, by providing motion estimation for pixels in a dependent eye view, using motion vector information from a colocated group of pixels in a base eye view and neighboring pixels to the colocated group of pixels in the base eye view. The method and apparatus encodes a group of pixels in a dependent eye view based on the estimated motion vector information. The method and apparatus may also include obtaining a frame of pixels that includes both base eye view pixels and dependent eye pixels so that, for example, frame compatible format packing can be employed. In one example, estimating the motion vector information for a block of pixels, for example, in a dependent eye view is based on a median value calculation of motion vectors for a block of pixels in a base eye view and motion vectors for neighboring blocks of pixels to the colocated group of pixels in the base eye view. An apparatus and method may include transmitting the encoded dependent eye view and base eye view information to another device and decoding the encoded dependent eye view and base eye view information for display. | 04-09-2015 |
20150092856 | Exploiting Camera Depth Information for Video Encoding - The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. The method and system of the present disclosure can be further used in other applications where camera and depth information of a rendered or captured video frame is available. | 04-02-2015 |
20150071339 | PERFORMING VIDEO ENCODING MODE DECISION BASED ON MOTION ACTIVITY - A method and apparatus are described for performing video encoding mode decisions. A down-scaled frame is received that includes a macroblock corresponding to a first subset of macroblocks of a first area in a full-scale frame. A first average motion vector is calculated for the first subset of macroblocks, and a second average motion vector is calculated for a second subset of macroblocks of a second area surrounding the first subset of macroblocks. A comparison of a threshold to a distance measure between absolute values of the first and second average motion vectors is performed. A prediction mode for the macroblock in the down-scaled frame is determined based on the comparison to generate predicted blocks. | 03-12-2015 |
20150061747 | PROPORTIONAL-TO-SUPPLY ANALOG CURRENT GENERATOR - A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current. | 03-05-2015 |
20150061737 | PHASE LOCKED LOOP WITH BANDWIDTH CONTROL - A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal. | 03-05-2015 |
20150030082 | PERFORMING VIDEO ENCODING MODE DECISIONS BASED ON DOWN-SCALED MACROBLOCK TEXTURE COMPLEXITY - A method and apparatus are described for performing video encoding mode decisions in a video transcoding system. A down-scaled frame may be received that includes at least one macroblock. The down-scaled frame may be associated with a full-scale frame having a plurality of macroblocks that have been downsampled. A weighting factor and a distance measure factor may be determined for each of the macroblocks in the full-scale frame. Predicted blocks may be generated based on the weighting and distance measure factors. | 01-29-2015 |
20140375658 | Processor Core to Graphics Processor Task Scheduling and Execution - An apparatus and method for processor core to graphics processor scheduling and execution is disclosed. In one embodiment, an apparatus includes a general purpose processor configured to execute instructions from a first instruction set and a graphic processing unit (GPU) configured to execute instructions from a second instruction set. The apparatus also includes a microcode unit configured to store microcode instructions that, when executed by the general purpose processor core, generate translated instructions, wherein the translated instructions are generated by translating selected instructions from the first instruction set translated into instructions of the second instruction set. The general purpose processor is configured to, responsive to performing a translation, pass the translated instructions to the GPU. The GPU is configured to execute the translated instructions and pass corresponding results back to the general purpose processor. | 12-25-2014 |
20140351546 | METHOD AND APPARATUS FOR MAPPING A PHYSICAL MEMORY HAVING A PLURALITY OF MEMORY REGIONS - A method and apparatus are described for mapping a physical memory having different memory regions. A plurality of virtual non-uniform memory access (NUMA) nodes may be defined in system memory to represent memory segments of various performance characteristics. Memory segments of a high-bandwidth memory (HBM) system memory may be allocated to a first memory region of the physical memory having memory segments represented by a first one of the NUMA nodes. The physical memory may include a second memory region having memory segments represented by a second one of the NUMA nodes. Memory segments of system memory may be allocated to the second memory region. The physical memory may further include a third memory region having memory segments represented by a third one of the NUMA nodes. Memory segments of an interleaved uniform memory access (UMA) graphics memory may be allocated to the third memory region. | 11-27-2014 |
20140344650 | METHOD AND APPARATUS FOR PROVIDING A DISPLAY STREAM EMBEDDED WITH NON-DISPLAY DATA - A video device having data lanes and a method of operating the video device includes obtaining a stream of debug data in response to a test operation, framing the stream of debug data independent of establishing a video blanking period, and transmitting the framed stream of debug data across one or more data lanes of the video link for operation between a video source device and a video sink device. The method also includes generating a stream of video data related to the test operation, framing the stream of video data to establish a video blanking period, and transmitting the framed stream of debug data concurrently with the framed stream of video data across the one or more data lanes of the video link. | 11-20-2014 |
20140344605 | CONTENT PRESENTATION SYSTEM AND METHOD - The present disclosure relates to a method and system for content presentation in a main processor shutoff mode. A method for content presentation includes transferring content to at least one of a co-processor and storage accessible by the co-processor and shutting off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. The content may include at least one of multimedia data, text data, and image data. A disclosed system includes a main processor in communication with a co-processor. The main processor includes data transfer logic operative to transfer the content and to shut off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. | 11-20-2014 |
20140344587 | EVENT BASED DYNAMIC POWER MANAGEMENT - An apparatus, computer readable medium, and method of event based dynamic power management. The method includes responding to receiving an indication of an event that is external to a hardware block engine by adjusting the power to the hardware block engine, if the event indicates that the power to the hardware block engine should be adjusted. The method may include receiving a second event that is external to the hardware block engine. The method may include determining whether or not the power should be adjusted to the hardware block engine based on the event and the second event. If it is determined that the power should be adjusted, then the power may be adjusted to the hardware block based on the event and second event. A method of monitoring a component and sending an indication of an event that the component will not require a hardware block engine is disclosed. | 11-20-2014 |
20140321533 | SINGLE-PATH VARIABLE BIT RATE VIDEO COMPRESSION - Apparatuses, computer readable mediums, and methods of encoding video are disclosed. A video comprising a plurality of frames is encoded. The method may determine whether to encode a frame as an interframe (I frame) or a predicted frame (P frame). An I frame may be encoded with a quantization parameter (QP), which may be determined for the I frame. A P frame may be encoded with a QP limited to vary between a lower QP and an upper QP. After encoding N P frames, QP may be adjusted, where N is a fixed or dynamically adjusted number of frames. If a number of bits used to encode the N P frames exceeds a first budget threshold then the value of QP may be raised, and if the number of bits used to encode the N P frames is below a second budget threshold then the value of QP may be lowered. | 10-30-2014 |
20140312710 | MULTIPLE OUTPUT CHARGE PUMP WITH PEAK VOLTAGE FOLLOWING FREQUENCY DIVIDER CONTROL - A power converter for a load with varying power requirements dynamically adjusts its supply voltage to the load so as to track the radio frequency (RF) envelope of the signal being carried by the load. The supply voltage can be provided by a multiple-output charge pump providing multiple output voltage levels concurrently, and a switch to provide a selected one of the different output voltage levels as the supply voltage to the load. A controller controls the switch to dynamically modify the voltage level selected for output as the supply voltage such that the supply voltage tracks the RF envelope of the signal being carried by the load. As the switching losses of transistors of the power converter may exceed the power savings achieved through envelope tracking, the power converter employs a peak following frequency divider circuit that limits the switching frequency of the power converter to a threshold frequency. | 10-23-2014 |
20140292756 | Hybrid Render with Deferred Primitive Batch Binning - A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed. | 10-02-2014 |
20140217997 | ASYMMETRIC TOPOLOGY TO BOOST LOW LOAD EFFICIENCY IN MULTI-PHASE SWITCH-MODE POWER CONVERSION - Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number. | 08-07-2014 |
20140211855 | APPARATUS AND METHOD FOR VIDEO DATA PROCESSING - Methods and apparatus for facilitating processing a reference frame to produce an output frame. Motion vector data for a block of reference frame pels estimates the displacement of the reference frame pels from corresponding pels in a prior input frame. Comparison metrics are produced for a pel of the reference frame with respect to that pel and a plurality of neighboring reference frame pels A first comparison metric is based on a comparison with corresponding pels of a prior output frame that corresponds to the prior input frame as previously processed. A second comparison metric is based on a comparison with corresponding pels of a motion compensated prior output frame derived from applying motion vector data to the pels of the prior output frame. A pel of the output frame that corresponds to the reference frame pel is determined using the first and second comparison metrics. | 07-31-2014 |
20140211854 | APPARATUS AND METHOD FOR VIDEO PROCESSING - Methods and apparatus for facilitating motion estimation in video processing are provided. In one embodiment, search block is defined within one frame. A relative location of a corresponding block in another frame with respect to the search block is determined based on comparative searching at a predetermined granularity to produce a motion vector for the search block with a first precision. Correlation values are determined with respect to the search block for the corresponding block and for one block or more blocks defined at relative locations of less than the predetermined granularity with respect to the corresponding block in different directions. A refined motion vector for the search block with a second higher precision is determined based on the relative location of the block having a selected correlation value that is selected from among the determined correlation values. | 07-31-2014 |
20140181491 | FIELD-PROGRAMMABLE MODULE FOR INTERFACE BRIDGING AND INPUT/OUTPUT EXPANSION - One or more specialized field programmable modules (e.g. CPLD and FPGA blocks) and their programming interface are embedded into a processing system (e.g. a CPU, GPU, APU and/or chipset). The field programmable modules are in-system programmable, in contrast to the application specific integrated circuit (ASIC) modules that perform the core functions of the processing system. The programmable flexibility of the field programmable modules can have various benefits during different stages of the integrated circuit life cycle for the processing system, such as reconfigurable interface bridging and two-way I/O expansion. | 06-26-2014 |
20140181355 | CONFIGURABLE COMMUNICATIONS CONTROLLER - A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate. | 06-26-2014 |
20140177729 | METHOD AND APPARATUS FOR TRANSCODING VIDEO DATA - A method and apparatus for transcoding video data decodes video that is encoded in the first format and produces decoded data blocks that include decoded tile data such that each decoded block includes pixel data for multiple display lines. The method and apparatus performs a linear write operation on the decoded data block by controlling storing of the decoded data block rows in consecutive linear addresses in memory such that one line of memory comprises decoded data for multiple display lines from the same block. The method and apparatus fetches the line of memory and re-encodes the data into a data block format, In one example translation of the fetched line of memory back into the original decoded data block format is performed for re-encoding such that the block of data includes data for multiple display lines. The video data is re-encoded to the second format using the decoded data block that was translated from the fetched line of memory. | 06-26-2014 |
20140176580 | PROVIDING MULTIPLE VIEWER PREFERENCES ON A DISPLAY DEVICE - A system and method for providing viewer preferences on a display device are presented. An embodiment includes a storage medium for storing preset viewer preferences, each preference being categorized based on one of a plurality of viewers, a processor that accesses the storage medium and acquires the stored preset viewer preference for a given one of the plurality of viewers, and a display device that provides content to the viewer in accordance with the viewer's preferences using at least one optical element. | 06-26-2014 |
20140169481 | SCALABLE HIGH THROUGHPUT VIDEO ENCODER - A scalable high throughput video encoder is described herein. A plurality of dedicated, hardware video encoders runs in a staggered, parallel architecture, where each video encoder encodes a video frame and the stagger or delay is a programmable number of macroblock rows. In an example method, after a first video encoder finishes encoding the first x macroblock rows of a frame, the first video encoder signals a second video encoder to start encoding a macroblock row of a next unprocessed frame. Both video encoders continue encoding in parallel in a synchronized, staggered manner. At the end of the frame, the first video encoder starts encoding x macroblock rows of another unprocessed frame. | 06-19-2014 |
20140167261 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 06-19-2014 |
20140157026 | METHODS AND APPARATUS FOR DYNAMICALLY ADJUSTING A POWER LEVEL OF AN ELECTRONIC DEVICE - Methods and apparatus for dynamically adjusting a power level of an electronic device ( | 06-05-2014 |
20140156968 | FLEXIBLE PAGE SIZES FOR VIRTUAL MEMORY - A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address. | 06-05-2014 |
20140146883 | BANDWIDTH SAVING ARCHITECTURE FOR SCALABLE VIDEO CODING SPATIAL MODE - A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth. | 05-29-2014 |
20140145701 | Self-Calibrating Digital Bandgap Voltage and Current Reference - A reference voltage generator is provided. In an example, the reference voltage generator includes a temperature-dependent device, a processing module configured to process a digital representations of first and second voltages derived from the temperature-dependent device and a reference voltage to determine a value, and a digital to analog converter (DAC) configured to generate a reference voltage based on the value. The first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute temperature (CTAT) and the reference voltage is substantially independent of absolute temperature in an operating temperature range of the reference voltage generator. | 05-29-2014 |
20140143885 | FIRMWARE-IMPLEMENTED SOFTWARE LICENSING - A device receives a request to use a software program, determines a comparison indicator based on receiving the request, and determines whether a license for the software program is valid based on a license validity indicator, stored in a secure environment, and the comparison indicator. The device permits execution of secure code stored in the secure environment when the license is determined to be valid, and prevents execution of the secure code stored in the secure environment when the license is determined to be invalid. | 05-22-2014 |
20140139513 | METHOD AND APPARATUS FOR ENHANCED PROCESSING OF THREE DIMENSIONAL (3D) GRAPHICS DATA - A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space. | 05-22-2014 |
20140139178 | WIRELESS POWER TRANSFER DEVICE FOR CHARGING MOBILE/PORTABLE DEVICES - A charging system having a charging device with a groove for receiving a mobile/portable device for charging is provided having a magnetic core located in a housing of the charging device with the magnetic core having a base and two legs that are located around the groove. A coil is wrapped around the base and a driver circuit is connected to the coil as well as to an external power source. A power receiver is located in a mobile/portable device that can be placed in the groove in the charging device. The power receiver includes a receiver magnetic core as well as a receiving coil wrapped around the receiver magnetic core for receiving an inductive current from the charging device. A charging circuit is connected to the receiving coil and adapted to be connected to the battery of the mobile/portable device for charging. | 05-22-2014 |
20140130079 | METHOD AND DEVICE FOR PROVIDING A VIDEO STREAM FOR AN OBJECT OF INTEREST - A method and device for ranking video feeds provide a user with the best feed depending on what the user wishes to see. The method includes obtaining one or more video feeds and ranking the video feeds. The ranking is based, at least in part, upon input from a viewer indicating an object of interest. The ranking can consider things such as video stream resolution and signal strength. | 05-08-2014 |
20140129738 | Flexible Implementation of Serial Bus Support Over Display Interface - Systems and methods are used to configure a communication channel. A source device can dynamically map Display Port lanes to support both display devices and USB3.0 devices. A method for configuring a communication channel includes detecting a device connection event indicating a change to a configuration of the communication channel in response to a branch device of the communication channel satisfying a dynamic configuration capability criteria indicating that the communication channel is reconfigurable. Configuration parameters of a sink device in the communication channel are identified. The communication channel is reconfigured to carry a source data stream to the sink device based on the configuration parameters. | 05-08-2014 |
20140126665 | OUTPUT DRIVER WITH ADJUSTABLE VOLTAGE SWING - A system adjusts a voltage swing of an output driver based on a supply voltage. A supply voltage monitor generates a digital code indicating the difference between the supply voltage and nominal voltage representing a preferred level for the supply voltage. An impedance controller sets the voltage swing for the output driver based on the digital code, thereby keeping the voltage swing of the output driver output signal within specified limits while maintaining an impedance match with a load coupled to the output driver. | 05-08-2014 |
20140126612 | ADAPTIVE CLOCK MISMATCH COMPENSATION SYMBOL INSERTION IN SIGNAL TRANSMISSIONS - A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data. | 05-08-2014 |
20140115192 | METHOD AND DEVICE FOR PROVIDING HIGH SPEED DATA TRANSMISSION WITH VIDEO DATA - A method and device for operating a data link having multiple data lanes is provided. The method includes supplying first data (such as video data that follows the DisplayPort protocol) on one or more data lanes of a data interface between a video source device and a video sink device. In addition to being video stream data (such as the above mentioned DisplayPort video data) the first data can also be audio stream data (such as DisplayPort audio data), source-sink interface configuration data (such as DisplayPort AUX data) and sink related interrupt data (such as DisplayPort Hot Plug Detect “HPD” data). The method also includes receiving second data on one or more unidirectional data lanes of the data interface. The second data being data other than video stream data, source-sink interface configuration data and sink related interrupt data. | 04-24-2014 |
20140110837 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 04-24-2014 |
20140098849 | METHOD AND DEVICE FOR CREATING AND MAINTAINING SYNCHRONIZATION BETWEEN VIDEO SIGNALS - A method and device for providing synchronized data output is provided. The method includes generating two data streams sending data to be presented in synchronization. Both streams are generated by the same processor-based device. The first data stream follows a first protocol and the second data stream follows a second (different) protocol. The processor of the processor-based device adjusts a data rate of the second data stream to cause a reduction in any timing offset between the streams. | 04-10-2014 |
20140098296 | METHOD AND APPARATUS FOR CHANGING A PERSPECTIVE OF A VIDEO - A method and apparatus provides for changing a perspective of a video such as a display perspective of an object displayed in the video. In one example, the method and apparatus changes the display perspective of an object displayed in the video based on information indicating an orientation and/or position of the recording device that captures the object on the video. To do so, the method and apparatus may determine a current display perspective for an object displayed in the video based on information indicating an orientation and/or position of the recording device. By comparing the current display perspective to a desired display perspective for the object, the method and apparatus determines an amount of display perspective adjustment for the object and selects appropriate perspective adjustment methods to carry out the adjustment. Accordingly, the display perspective adjustment is made to the video automatically for the object displayed in the video without user intervention. | 04-10-2014 |
20140098295 | METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR DESCRIBING VIDEO PROCESSING - An upstream video processor may perform video processing upon video data to created processed video data. The video processing may include at least one of color correction, contrast correction, gamma correction, sharpness enhancement, and edge enhancement. Metadata indicative of the performed video processing may also be generated. The processed video data and metadata may be passed to a downstream video processor, the latter for use in determining what further video processing, if any, to apply. An intermediate video processor may receive video data and metadata indicating video processing performed thereupon by an upstream video processor. Based on the received metadata, additional video processing may be performed, and new metadata indicating the additional video processing may be generated. Composite metadata may be generated from the received and new metadata and may be passed along with the processed video data to a downstream video processor for use in determining what further video processing, if any, to apply. | 04-10-2014 |
20140093003 | DATA TRANSMISSION BETWEEN ASYNCHRONOUS ENVIRONMENTS - A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency. | 04-03-2014 |
20140089541 | BUS PROTOCOL COMPATIBLE DEVICE AND METHOD THEREFOR - A bus protocol compatible device, includes a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training sequence to the output, and a power state controller for placing the transmitter in the first mode for a first period of time in response to a change in a link state, and in the second mode after an expiration of the first period of time. | 03-27-2014 |
20140085273 | METHOD AND DEVICE FOR LINK OVER-TRAINING - A method and device of over training a connection is provided. Noise is intentionally supplied and added to a signal that is subjected to a link training operation. The link training operation is used to obtain a link between a source device and a receiving device. The device includes a noise source from which noise is obtained and added to a signal to aid in link over-training. | 03-27-2014 |
20140085197 | CONTROL AND VISUALIZATION FOR MULTI TOUCH CONNECTED DEVICES - A method and device for facilitating interaction between a touch screen device and a computing device are provided. The method includes displaying a pointer location indicator (mouse cursor) on the touch screen device. The mouse cursor moves responsively to movement of a mouse of a linked computing device. The device includes a touch screen having an input operable to receive indications of operation of a pointing device coupled to a second computing device. The touch screen is further operable to display a pointer location indicator and the pointer location indicator is operable to move responsively to movement of the pointing device. | 03-27-2014 |
20140082558 | Method and Apparatus For Providing a User Interface For a File System - A method and apparatus provides a user an interface for a file system. In one example, the method and apparatus displays the file as a visualized object, e.g., a graphical representation of the file as a real life object, receives selection of visualized objects and activates data elements represented by the visualized objects. The visualization of the file may be determined based on visualizer identification information associated with the file. For the activated data elements, the method and apparatus displays tool interfaces, in combination with the visualized objects. The tool interfaces may be selectively displayed for the activated data element base on tool identification information associated with a data type of the data element. Furthermore, the method and apparatus can process the activated data elements using the selected tool actions from different programs. | 03-20-2014 |
20140082389 | Direct Hardware Access Media Player - A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The media content is processed using the dedicated hardware pipeline to reduce the power consumption during processing. | 03-20-2014 |
20140075171 | MULTI-PURPOSE POWER CONTROLLER AND METHOD - The present invention provides a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex mid-size complex programmable logic devices (CPLD) or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. | 03-13-2014 |
20140072027 | SYSTEM FOR VIDEO COMPRESSION - A system and method for providing video compression that includes encoding using an encoding engine a YUV stream wherein Y, U and V color values are encoded in parallel and patching together the Y, U and V color streams to form a compressed YUV output stream. The encoding engine further includes encoding each color value of the YUV stream in parallel using parallel encoding engines and a control engine for controlling operation all of the encoding engines in parallel. The YUV stream has an average bits per pixel value that varies from a first value to a second value that is double the first value. The encoding engine includes encoding the YUV stream in generally the same amount of time regardless of the average bits per pixel value. | 03-13-2014 |
20140071159 | Method and Apparatus For Providing a User Interface For a File System - A method and apparatus provides for controlling presentation of multimedia content. In one example, the method and apparatus changes a display perspective of a multimedia presenting system that presents the multimedia content by determining an amount of display perspective adjustment based on a relative position between a user and the multimedia presenting system. According to the determined amount of display perspective adjustment, the method and apparatus issues one or more control commands that instruct the multimedia presenting system to change the display perspective. The display perspective may be changed for example by moving a display or portion thereof and/or by changing the perspective of the displayed image on the display while leaving the position of the display alone. | 03-13-2014 |
20140071141 | RENDERING SETTINGS IN A MULTI-GRAPHICS PROCESSING UNIT SYSTEM - Graphics rendering settings in a computer system are adjusted when an activity level on a bus meets a trigger condition. The graphics rendering settings of the system are returned to a previous level when the bus activity drops below a threshold. The trigger condition may be related to bandwidth usage on the bus or latency of data sent over the bus. | 03-13-2014 |
20140063034 | METHOD AND DEVICE FOR SELECTIVE DISPLAY REFRESH - A method of and device for providing image frames is provided. The method includes outputting portions of a first frame that have changed relative to the one or more other frames without outputting portions of the first frame that have not changed relative to the one or more other frames. Each of the portions are determined to be changed if a rendering engine has written to a frame buffer for a location within boundaries of the portion. This outputting is done in response to one or more portions of a first frame having changed relative to one or more other frames. | 03-06-2014 |
20140049292 | INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY - An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format. | 02-20-2014 |
20140037265 | METHOD AND APPARATUS FOR VIDEO STREAM PROCESSING - A method and apparatus for video stream processing is implemented in a monitor scaler chip (MSC). The MSC receives the video stream and determines whether the video stream includes copy protected content. The MSC routes the video stream based upon the determination. | 02-06-2014 |
20140037027 | Methods and Systems for Processing Network Messages in an Accelerated Processing Device - The present method and system enables receiving a radio frequency (RF) signal. The received RF signal is assigned to a single instruction multiple data (SIMD) module in an accelerated processing device (APD) for processing to extract network messages. The extracted network layer messages are further processed by the SIMD module to obtain data transmitted via the RF signal. | 02-06-2014 |
20140035936 | METHODS AND APPARATUS FOR PROCESSING GRAPHICS DATA USING MULTIPLE PROCESSING CIRCUITS - Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed. | 02-06-2014 |
20140029646 | DISABLING SPREAD-SPECTRUM CLOCK SIGNAL GENERATION - A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle. | 01-30-2014 |
20140022452 | SYSTEM AND METHOD FOR ARTIFACT REMOVAL - A method and apparatus provide for improving signal quality. The method includes receiving a first media signal, such as a video signal, in a first format, such as 1080p. The provided video signal is one that is created by upsampling a video signal recorded in a format having a lower sampling rate. The method also includes obtaining a second signal indicative of error within the first media signal. The second signal is in a second format, such as the format having a lower sampling rage in which the video signal was recorded. The signal is processed to place the second signal in the format of the first signal. Then, the estimated error signal is combined with the original signal to arrive at an error corrected output. | 01-23-2014 |
20130346735 | ENHANCED SYSTEM MANAGEMENT BUS - A method and device are provided for retrieving system data needed for boot up and/or wake-up. A bus hub is provided that retrieves needed data prior to such data being requested by the processor. The bus hub then stores the data. When a request is received for the data from the processor, the bus hub responds by sending the stored data. | 12-26-2013 |
20130346026 | MODULAR COMPUTING ARCHITECTURE ENABLING DIAGNOSTICS - A device and method for providing computer operation diagnostics. The method includes coupling a mobile device (such as a mobile smartphone) to the computer via a diagnostic port. The smartphone has a diagnostic program (application) thereon that is initiated so as to be able to communicate with a diagnostic module within the computer to request and receive information from the computer. | 12-26-2013 |
20130344822 | REMOTE AUDIO KEEP ALIVE FOR WIRELESS DISPLAY - An apparatus and method is provided for improving initialization and synchronization of display devices to audio data. Current implementations to retain synchronization between a transmitter and a display use “Keep Alive” silent audio data stream in the format of the latest data stream on an interface between the transmitter and the display even when no data is available. Implementing the above solution in a system where the silent audio data stream is transmitted over a wireless link is bandwidth and power inefficient. The techniques provide an apparatus and method to efficiently generate and transmit silent audio data stream for maintaining synchronization. | 12-26-2013 |
20130315481 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 11-28-2013 |
20130301725 | EFFICIENT MODE DECISION METHOD FOR MULTIVIEW VIDEO CODING - A method for determining a macroblock (MB) coding mode for a current MB in a dependent view. A window around a co-located MB in a base view is determined, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view. A coding mode complexity value (CMCV) is determined for each MB in the window, wherein the CMCV is based on a coding mode used to encode the MB. Rate distortion optimization (RDO) is performed for the current MB using a reduced number of coding modes if a total CMCV for all MBs in the window is less than a threshold, or using all supported coding modes if the total CMCV for all MBs in the window is greater than the threshold. A coding mode for the current MB is determined based on the RDO results. | 11-14-2013 |
20130275778 | PROCESSOR BRIDGE POWER MANAGEMENT - A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor. | 10-17-2013 |
20130263141 | Visibility Ordering in a Memory Model for a Unified Computing System - Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations. | 10-03-2013 |
20130262814 | Mapping Memory Instructions into a Shared Memory Address Place - Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor. | 10-03-2013 |
20130262784 | Memory Heaps in a Memory Model for a Unified Computing System - A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor. | 10-03-2013 |
20130262776 | Managing Coherent Memory Between an Accelerated Processing Device and a Central Processing Unit - Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter. | 10-03-2013 |
20130262775 | Cache Management for Memory Operations - Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item. | 10-03-2013 |
20130262736 | MEMORY TYPES FOR CACHING POLICIES - The present system enables receiving a request from an I/O device to translate a virtual address to a physical address to access the page in system memory. One or more memory attributes of the page defining a cacheability characteristic of the page is identified. A response including the physical address and the cacheability characteristic of the page is sent to the I/O device. | 10-03-2013 |
20130247061 | METHOD AND APPARATUS FOR THE SCHEDULING OF COMPUTING TASKS - Described herein are methods and related apparatus for the allocation of computing resources to perform computing tasks. The methods described herein may be used to allocate computing tasks to many different types of computing resources, such as processor cores, individual computers, and virtual machines. Characteristics of the available computing resources, as well as other aspects of the computing environment, are modeled in a multidimensional coordinate system. Each coordinate point in the coordinate system corresponds to a unique combination of attributes of the computing resources/computing environment, and each coordinate point is associated with a weight that indicates the relative desirability of the coordinate point. To allocate a computing resource to execute a task, the weights of the coordinate points, as well as other related factors, are analyzed. | 09-19-2013 |
20130238856 | System and Method for Cache Organization in Row-Based Memories - The present disclosure relates to a method and system for mapping cache lines to a row-based cache. In particular, a method includes, in response to a plurality of memory access requests each including an address associated with a cache line of a main memory, mapping sequentially addressed cache lines of the main memory to a row of the row-based cache. A disclosed system includes row index computation logic operative to map sequentially addressed cache lines of a main memory to a row of a row-based cache in response to a plurality of memory access requests each including an address associated with a cache line of the main memory. | 09-12-2013 |
20130236032 | ADJUSTING A DATA RATE OF A DIGITAL AUDIO STREAM BASED ON DYNAMICALLY DETERMINED AUDIO PLAYBACK SYSTEM CAPABILITIES - A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound. | 09-12-2013 |
20130235077 | COMPOSITING IN MULTIPLE VIDEO PROCESSING UNIT (VPU) SYSTEMS - The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels. | 09-12-2013 |
20130235057 | AREA-BASED DEPENDENCY CHAIN ANALYSIS OF SHADERS AND COMMAND STREAM - A method and device are provided for performing tile based rendering. The method and device analyze past and current commands to determine when tiles are renderable independently of other tiles. In such cases, all rendering passes are performed successively without rendering other tiles in between. | 09-12-2013 |
20130229421 | GPU Display Abstraction and Emulation in a Virtualization System - A method, computer program product, and system that includes a virtual function module with an emulated display timing device, a first independent resource, and a second independent resource, where the first and second independent resources signal a physical function module that a new surface has been rendered, and where the physical function module signals the virtual function module via the emulated timing device and the first and second independent resources when the rendered new surface has been displayed, copied, used, or otherwise consumed. | 09-05-2013 |
20130219134 | WRITE DATA MASK METHOD AND SYSTEM - A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command. | 08-22-2013 |
20130216198 | METHOD AND APPARATUS FOR AUTOMATIC TIME-SHIFTING FOR A CONTENT RECORDER - A content player includes a pausable mass storage device player that can be used to record and play content. The pausable mass storage device can become paused in response to an assertion of a pause signal. Once paused, the content player remains paused until the pause signal is deasserted. The content player also includes an event detector that is coupled to the pausable mass storage device player. The content player detects a non-viewer initiated event, (e.g., an automatic event such as the receipt of an email with embedded enhanced content), and to assert the pause signal in response thereto. The content player receives content, detects an event, and in response to detecting the event, pauses the content to a presentation device and spools the content onto the mass storage device. | 08-22-2013 |
20130215128 | MULTI-THREAD GRAPHICS PROCESSING SYSTEM - A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads. | 08-22-2013 |
20130182069 | 3D VIDEO PROCESSING - A method, an apparatus, and a non-transitory computer readable medium for performing 2D to 3D conversion are presented. A 2D input source is extracted into left and right 3D images. Motion vectors are calculated for the left and right 3D images. Frame rate conversion is performed on the left 3D image and the right 3D image, using the respective calculated motion vectors, to produce motion compensated left and right 3D images. The left and right 3D images and the motion compensated left and right 3D images are reordered for display. | 07-18-2013 |
20130174208 | METHOD AND APPARATUS FOR ELECTRONIC DEVICE COMMUNICATION - The present disclosure relates to a method and apparatus for electronic device communication. A method includes translating monitor control commands to an internet protocol (IP) format to produce IP formatted monitor control commands, and communicating the IP formatted monitor control commands to an IP port dedicated for communicating IP formatted monitor control commands. | 07-04-2013 |
20130174144 | HARDWARE BASED VIRTUALIZATION SYSTEM - A method for changing between virtual machines on a graphics processing unit (GPU) includes requesting to switch from a first virtual machine (VM) with a first global context to a second VM with a second global context; stopping taking of new commands in the first VM; saving the first global context; and switching out of the first VM. | 07-04-2013 |
20130167140 | METHOD AND APPARATUS FOR DISTRIBUTED OPERATING SYSTEM IMAGE DEPLOYMENT - A method and apparatus provides for controlling the distribution and installation of operating systems. In one example, the method and apparatus partitions a storage device of a device into a first partition and a second partition. The method and apparatus installs a first operating system into the first partition of the storage device, obtains an image of the second operating system, the image including at least the second operating system pre-configured for operation with the device, and installs, using the first operating system, the image of the operating system to the second partition of the storage device. In an embodiment, the image is transmitted from one or more other devices. In an embodiment, two or more images are cached on the device according to the likelihood they will be used in the future. | 06-27-2013 |
20130166922 | METHOD AND SYSTEM FOR FRAME BUFFER PROTECTION - When content, such as premium video or audio, is decoded, the content is stored in protected memory segments. Read access to the protected memory segments from a component not in a frame buffer protected (FBP) mode is blocked by a memory controller. The memory controller also blocks components in the FBP mode from writing to unprotected memory segments. The content may be processed by a processing engine operating in the FBP mode and may only be written back to protected memory segments. The memory segment may later be marked as unprotected if the memory segment is no longer needed. If the content is encrypted in protected memory, the encrypting key associated with the memory segment may be removed. If the content is stored in the clear, the protected memory segments are scrubbed before releasing the segments for use as unprotected memory segments. | 06-27-2013 |
20130166875 | WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface. | 06-27-2013 |
20130163670 | MULTIVIEW VIDEO CODING REFERENCE PICTURE SELECTION UNDER A ONE REFERENCE PICTURE CONSTRAINT - A method for coding a dependent view picture based on a reference picture includes selecting a reference picture from a base view picture list if a metric of intra macroblocks in an evaluated picture is greater than a first threshold, selecting a reference picture from a dependent view picture list if a metric of skipped macroblocks in the evaluated picture is greater than a second threshold, and coding a dependent view picture using the selected reference picture. An application-controlled weighting mechanism may be used if both of the thresholds are not met. | 06-27-2013 |
20130162911 | DOWNSTREAM VIDEO COMPOSITION - A video source, a display and a method of processing multilayered video are disclosed. The video source decodes a multilayered video bit stream to transmit synchronized streams of decompressed video images and corresponding overlay images to an interconnected display. The display receives separate streams of video and overlay images. Transmission and reception of corresponding video and overlay images is synchronized in time. A video image received in the display can be selectively processed separately from its corresponding overlay image. The video image as processed at the display is later composited with its corresponding overlay image to form an output image for display. | 06-27-2013 |
20130162682 | VERTICAL SCAN PANEL WITH CONVERSION MODE CAPABILITY - A method and apparatus for providing an image on a vertical scan panel determines whether a mode of operation for a vertical scan panel is either a scan conversion pass-through mode or a horizontal scan conversion mode. If the determined mode is the horizontal scan conversion mode, the method and apparatus converts display data in the vertical scan panel from a horizontal scan format to a vertical scan format and displays the converted display data on the vertical scan panel. However, if the determined mode is the scan conversion pass-through mode, the method and apparatus includes displaying display data on the vertical scan panel in a vertical scan format without applying a scan conversion operation on the display data. | 06-27-2013 |
20130162658 | SYNCHRONIZATION WITH SEMAPHORES IN A MULTI-ENGINE GPU - A method for performing an operation using more than one resource may include several steps: requesting an operation performed by a resource; populating a ring frame with an indirect buffer command packet corresponding to the operation using a method that may include for the resource requested to perform the operation, creating a semaphore object with a resource identifier and timestamp, in the event that the resource is found to be unavailable; inserting a command packet (wait) into the ring frame, wherein the command packet (wait) corresponds to the semaphore object; and submitting the ring frame to the graphics engine. | 06-27-2013 |
20130162341 | AUTO-CALIBRATING A VOLTAGE REFERENCE - A method and circuitry for determining a temperature-independent bandgap reference voltage are disclosed. The method includes determining a quantity proportional to an internal series resistance of a p-n junction diode and determining the temperature-independent bandgap reference voltage using the quantity proportional to an internal series resistance. | 06-27-2013 |
20130162300 | HIGH SPEED SERIAL INPUT/OUTPUT BUS VOLTAGE MODE DRIVER WITH TUNABLE AMPLITUDE AND RESISTANCE - A device having a voltage mode driver with tunable amplitude and resistance that supports a predetermined output resistance and output amplitude is described herein. The voltage mode driver includes multiple configurable drivers. The voltage mode driver is controlled by a control module. Resistance tuning is controlled by the number of active configurable drivers and amplitude tuning is controlled by setting the high or low drive state of each active configurable driver. The slew rate of the device is controlled by delaying the setting of the high or low drive state of an active configurable driver by a predetermined interval. | 06-27-2013 |
20130162289 | METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT - A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level. | 06-27-2013 |
20130160111 | Device and Method for Use of Real-Time Biometric Data To Control Content and Device Access - A device and method for unobtrusively conducting security access checks via biometric data. The device and method obtains biometric data in response to a request for content and initiates a security clearance process that is substantially unobservable to an individual with clearance to access the requested content. | 06-20-2013 |
20130159755 | APPARATUS AND METHOD FOR MANAGING POWER ON A SHARED THERMAL PLATFORM FOR A MULTI-PROCESSOR SYSTEM - A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform. | 06-20-2013 |
20130159630 | SELECTIVE CACHE FOR INTER-OPERATIONS IN A PROCESSOR-BASED ENVIRONMENT - The present invention provides embodiments of methods and apparatuses for selective caching of data for inter-operations in a heterogeneous computing environment. One embodiment of a method includes allocating a portion of a first cache for caching for two or more processing elements and defining a replacement policy for the allocated portion of the first cache. The replacement policy restricts access to the first cache to operations associated with more than one of the processing elements. | 06-20-2013 |
20130156090 | METHOD AND APPARATUS FOR ENABLING MULTIUSER USE - Methods and apparatus for enabling multiple user participation with a single multimedia computing platform and multiple displays. In particular, the methods enable multi-display rendering. For example, in a gaming environment, each user has the ability to select a particular view of the game that maybe different from other users and is private to that user. A system has a single multimedia computing platform with wired, wireless or combinations thereof. In a multiuser multiple display configuration, an application designates and renders particular or different frames to each of the users that may not be seen by the other users. Each frame is rendered from the perspective of the specific user or based on user selection. A display controller directs the frames to the appropriate displays. A video encoder engine encodes the frames and transmits the compressed frames to the appropriate wireless displays. | 06-20-2013 |
20130155793 | MEMORY ACCESS CONTROL SYSTEM AND METHOD - The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request. | 06-20-2013 |
20130155101 | SYSTEM AND METHOD FOR DISPLAYING CONTENT IN AN EXCLUSIVE MODE ENVIRONMENT - The present disclosure relates to a method and system for providing an image for display on a monitor. A method for providing an image for display includes detecting an exclusive display mode. In the exclusive display mode, an application is blocked from display on a monitor. In response to detecting the exclusive display mode, a composited surface is generated that comprises display data of a blocked application surface and display data of an exclusive application surface. A disclosed system includes a display mode detector that detects an exclusive display mode and a surface compositing module that causes a generation of a composited surface. | 06-20-2013 |
20130155097 | METHOD AND APPARATUS FOR MULTIPLE VIRTUAL THEMES FOR A USER INTERFACE (UI) - A method and apparatus for creating one or more themed user interfaces (UI) each capable of displaying content unique to the theme selected. This may allow the use of the one or more display configurations for themed content. A device may be associated with a UI, which is capable of displaying content. One or more display configurations associated with one or more themes may be created. Upon selection of a particular theme, content specific to the particular theme is displayed via the associated display configuration. | 06-20-2013 |
20130155081 | POWER MANAGEMENT IN MULTIPLE PROCESSOR SYSTEM - Power management for a processing system that has multiple processing units, (e.g., multiple graphics processing units (GPUs), is described herein. The processing system includes a power manager that obtains performance, power, operational or environmental data from a power management unit associated with each processor (e.g., GPU). The power manager determines, for example, an average value with respect to at least one of the performance, power, operational or environmental data. If the average value is below a predetermined threshold for a predetermined amount of time, then the power manager notifies a configuration manager to alter the number of active processors (e.g., GPUs), if possible. The power may then be distributed among the remaining GPUs or other processors, if beneficial for the operating and environmental conditions. | 06-20-2013 |
20130155078 | CONFIGURABLE GRAPHICS CONTROL AND MONITORING - A method and a graphics control and monitoring system are described. The graphics control and monitoring system is configurable and is equipped with a control and processing device, a computer, a data acquisition device, and a display. The control and processing device is equipped with a field programmable device that is configurable to work with a variety of data acquisition devices. The control and processing device receives data collected by the data acquisition device and processes the data. Further, graphics processing is performed by the processor which can be a central processing unit (CPU), a graphics processing unit (GPU), general purpose computation on GPU (GPGPU) that is equipped with parallel computation capability, among others. After processing, display data is provided to a display. | 06-20-2013 |
20130155073 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A PROCESSOR IN A VIRTUAL ENVIRONMENT - A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core. | 06-20-2013 |
20130155045 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A GRAPHICS PROCESSING CORE IN A VIRTUAL ENVIRONMENT - A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request. | 06-20-2013 |
20130154695 | PHASE LOCK LOOP WITH ADAPTIVE LOOP BANDWIDTH - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors. | 06-20-2013 |
20130154694 | PHASE-LOCKED LOOP FREQUENCY STEPPING - A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division. | 06-20-2013 |
20130152108 | METHOD AND APPARATUS FOR VIDEO PROCESSING - A method and system for video processing is disclosed. A device driver interface (DDI) call for flipping or updating an overlay may be skipped or ignored, and may not be used by a user mode driver to pass overlay properties to a kernel mode driver (KMD). Instead, the overlay properties may be passed to the KMD at rendering time during a DDI call for rendering. The user mode driver may call a DDI for rendering an overlay frame while simultaneously passing the overlay property data to the KMD. The KMD may store the overlay property data in an overlay flip queue, program the overlay hardware per the overlay property data stored in the overlay flip queue, and flip the overlay in response to the vertical synchronization deferred procedure call. | 06-13-2013 |
20130151797 | METHOD AND APPARATUS FOR CENTRALIZED TIMESTAMP PROCESSING - Method and apparatus for centralized timestamp processing is described herein. A graphics processing system includes multiple graphics engines and a timestamp module. For each task, a graphics driver assigns the task to a graphics engine and writes a task command packet to a memory buffer associated with the graphics engine. The graphics driver also writes a timestamp command packet for each task to a timestamp module memory buffer. A command processor associated with the graphics engine signals the timestamp module memory buffer upon completion of the task. If the read pointer is at the appropriate position in the timestamp module memory buffer, the timestamp module/timestamp module memory buffer executes the timestamp command packet and writes the timestamp to a timestamp memory. The timestamp memory is accessible by the graphics driver. | 06-13-2013 |
20130151787 | Mechanism for Using a GPU Controller for Preloading Caches - Provided is a method and system for preloading a cache on a graphical processing unit. The method includes receiving a command message, the command message including data related to a portion of memory. The method also includes interpreting the command message, identifying policy information of the cache, identifying a location and size of the portion of memory, and creating a fetch message including data related to contents of the portion, wherein the fetch message causes the cache to preload data of the portion of memory. | 06-13-2013 |
20130148947 | VIDEO PLAYER WITH MULTIPLE GRPAHICS PROCESSORS - A device and method for playing digital video are disclosed. The device includes multiple graphics processing units. The method involves using the multiple graphics processors to decode and output compressed audiovisual stream to a display and a speaker. Audiovisual bit streams possibly containing multi-stream video are efficiently decoded and displayed by sharing decoding-related tasks among multiple graphical processing units. | 06-13-2013 |
20130147832 | METHOD AND APPARATUS FOR REMOTE EXTENSION DISPLAY - A method and apparatus for extending the display area of a source device (SD) to one or more target devices (TDs), are described. According to a method, information that may be displayed at the SD is transmitted to the one or more TDs. At the TDs, the information is displayed and manipulated by a user. An indication of the user's manipulations of the information is received at the SD where the information is physically updated. The SD transmits the updated information to the one or more TDs in order to synchronize the information displayed by the one or more TDs with the transmitted information. | 06-13-2013 |
20130147817 | Systems and Methods for Reducing Clock Domain Crossings - In an embodiment, a graphics processing device is provided. The graphics processing device includes a global clock generator configured to generate a global clock signal and a plurality of graphics pipelines each configured to transmit image frames to a respective display device. Each of the graphics pipelines comprises a timing generator. Each of the timing generators is configured to generate a respective virtual clock signal based on the global clock signal and wherein each virtual clock signal is used to advance logic of a respective one of the display devices. | 06-13-2013 |
20130147815 | MULTI-PROCESSOR ARCHITECTURE AND METHOD - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 06-13-2013 |
20130147026 | HEATSINK INTERPOSER - According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package. | 06-13-2013 |
20130138977 | METHOD AND APPARATUS FOR ADJUSTING POWER CONSUMPTION LEVEL OF AN INTEGRATED CIRCUIT - Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency. | 05-30-2013 |
20130138897 | METHOD AND APPARATUS FOR DYNAMICALLY CONTROLLING DEPTH AND POWER CONSUMPTION OF FIFO MEMORY - A method and apparatus are described for controlling depth and power consumption of a first-in first-out (FIFO) memory including a data storage, a FIFO top register, a FIFO bottom register and control logic. The data storage may be segmented into a plurality of data storage segments. The FIFO top register may be configured to generate a first value indicating where a first entry in the data storage is stored. The FIFO bottom register may be configured to generate a second value indicating where a last entry in the data storage is stored. The control logic may be configured to determine which of the data storage segments to activate or deactivate based at least in part on the first and second values, and to monitor an available capacity and a write/read rate of the FIFO memory as data is read from and written to the activated data storage segments. | 05-30-2013 |
20130136379 | METHOD AND APPARATUS FOR CORRECTING ROTATION OF VIDEO FRAMES - A method and apparatus for correcting a rotation of a video frame are described. According to a method, an amount of the rotation of the video frame with respect to a reference is determined. The rotation of the video frame is corrected based at least in part on the detected amount of the rotation of the video frame. | 05-30-2013 |
20130113818 | IMAGE QUALITY CONFIGURATION APPARATUS, SYSTEM AND METHOD - A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed. | 05-09-2013 |
20130095614 | WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. | 04-18-2013 |
20130094571 | LOW LATENCY VIDEO COMPRESSION - A method and system are described for low-latency video. In the method a frame, selected from a group of frames, is divided into P-regions and an I-region based on an assigned refresh pattern in a refresh loop. An I-region bit budget and a P-region bit budget are determined. Quantization parameters are determined using the I-region bit budget and the P-region bit budget. Macroblocks of the selected frame are encoded based on the quantization parameters. The I-complexity and P-complexity are updated and a new frame bit budget is determined. The dividing, determining of the I-region bit budget, determining of the P-region bit budget, determining of quantization parameters and encoding are repeated for each remaining frame in the group of frames. | 04-18-2013 |
20130083043 | Methods and Systems to Reduce Display Artifacts When Changing Display Clock Rate - Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing. | 04-04-2013 |
20130076776 | METHOD AND APPARATUS FOR PROVIDING INDEPENDENT GAMUT REMAPPING FOR MULTIPLE SCREEN SUBSECTIONS - An apparatus and method for providing display information generates, independently from an operating system, different screen subsections of a screen image using independent gamut remapping configurations to generate an output image in a target gamut space of a display. The method and apparatus also provides the generated output image for display or may display the generated output image. | 03-28-2013 |
20130063574 | METHOD AND APPARATUS FOR PROVIDING VIDEO ENHANCEMENTS FOR DISPLAY IMAGES - A method and apparatus for processing video utilize individually collected image enhancement statistic information from differing processor cores for a same frame or multi-view that are then either shared between the processor cores or used by a third processor core to combine the statistical information that has been individually collected to generate global image-enhancement control information. The global image enhancement control information is based on a global analysis of both left and right eye views for example using the independently generated statistic information for a pair of frames. Respective image output information is produced by each of the plurality of processor cores based on the global image enhancement control information, for display on one or more displays. | 03-14-2013 |
20130060505 | TECHNIQUE FOR WAFER TESTING WITH MULTIDIMENSIONAL TRANSFORM - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors. | 03-07-2013 |
20130054851 | METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL - A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol. | 02-28-2013 |
20130050572 | METHOD AND APPARATUS FOR PROVIDING DROPPED PICTURE IMAGE PROCESSING - A method and apparatus adaptively creates a dropped frame rate converted frame from a plurality of source frames using at least one alternate support frame in lieu of neighboring source frame, in response to corrupted picture identification information. Stated another way, a frame rate converter, in response to corrupted picture indication information, replaces at least one corrupted source frame with a temporally modified frame created from at least one alternate source frame. The corrupted picture identification information indicates that a source frame, or segment thereof, includes at least one corrupted or dropped source frame (or segment thereof). Accordingly, although a source frame has been dropped or is corrupted, the frame rate converter does not base its output on a repeated frame or a corrupted frame output by a decoder and instead utilizes other non-neighboring source images as though they were neighboring frames, instead of using a repeated frame or corrupted frame. | 02-28-2013 |
20130032941 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 02-07-2013 |
20130010168 | GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION - A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera. | 01-10-2013 |
20130009980 | VIEWING-FOCUS ORIENTED IMAGE PROCESSING - A method and a processor for implementing the method are disclosed for processing of an image. A first algorithm is selected to be used for processing information representing an area of interest in the image. A second algorithm is selected to be used for processing information representing an area of the image that is not in the area of interest. The first and second algorithms are applied to their respective portions of the information representing the image. | 01-10-2013 |
20130009970 | Method and System for Display Output Stutter - Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system. | 01-10-2013 |
20120314777 | METHOD AND APPARATUS FOR GENERATING A DISPLAY DATA STREAM FOR TRANSMISSION TO A REMOTE DISPLAY - A method and apparatus are described for generating a display data stream for transmission to a remote display. A display control unit in a processor is configured to multiplex the outputs of a plurality of display controllers to generate a video data stream. A video compression engine (VCE) in the processor receives the video data stream directly from the display control unit without having to go through an external memory or an external display interface. The VCE compresses the video data stream, and optionally encrypts the video data stream. In one embodiment, audio and video data streams may be synchronized into a multiplexed, (and optionally encrypted), audio/video stream before being forwarded for transmission to a remote display. In another embodiment, separate audio and video streams (optionally encrypted) may be forwarded for transmission to the remote display. | 12-13-2012 |
20120314758 | METHOD AND APPARATUS FOR PROCESSING VIDEO DATA - A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream. | 12-13-2012 |
20120303995 | METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 11-29-2012 |
20120281150 | APPARATUS AND METHOD FOR MULTI-STREAMING FOR MORE THAN THREE PIXEL COMPONENT VALUES - A method and apparatus provides pixel information for one or more displays by producing for output on a single link, packet based pixel component multi-stream information on two or more streams. A first stream may include a portion of per-pixel component values, such as RGB pixel component values, whereas the second stream of the multi-stream may include a remaining portion of the per-pixel component values, such as a corresponding alpha value. Hence, multi-streams are employed to communicate, for example, an extended pixel component format for output to one or more displays. The multi-streams are synchronized to provide the pixel component values at a proper time for the receiving display or plurality of displays. | 11-08-2012 |
20120278029 | Transient Thermal Modeling of Multisource Power Devices - Embodiments of systems and methods for improved measurement of transient thermal responses in electronic systems are described herein. Embodiments of the disclosure use the known thermal transfer function of an electronic system to generate an equivalent resistor-capacitor (RC) network having a dynamic response that is identical to a given power excitation as the actual electronic system would have to that power excitation. Using the analogy between thermal and electrical systems, a Foster RC network is constructed, comprising a plurality of RC stages in which resistors and capacitors are connected in parallel. Subsequently, the analog thermal RC network is converted into an infinite impulse response (IIR) digital filter, whose coefficients can be obtained the Z-transform of the analog thermal RC network. This IIR digital filter establishes the recursive relationship between temperature output at the current time step and measured power input at the previous time step. Using this IIR digital filter, temperature response subject to arbitrary time-dependent power can be calculated in very small amount of time compared with prior art methods. | 11-01-2012 |
20120270388 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 10-25-2012 |
20120249559 | Controlling the Power State of an Idle Processing Device - A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided. | 10-04-2012 |
20120236755 | Embedded Clock Recovery - Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters. | 09-20-2012 |
20120229481 | ACCESSIBILITY OF GRAPHICS PROCESSING COMPUTE RESOURCES - A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU. | 09-13-2012 |
20120224642 | METHOD AND SYSTEM FOR PROVIDING SINGLE VIEW VIDEO SIGNAL BASED ON A MULTIVIEW VIDEO CODING (MVC) SIGNAL STREAM - A method and system for producing a single view video signal based on a multiview video coding (MVC) signal stream. A MVC signal stream representing multiple spatially related views of a scene, including a base view and at least one dependent view, is decoded to provide multiple decoded video signals representing the spatially related views, with respective portions of the MVC signal stream representing one of multiple temporally adjacent video frames, and the MVC signal stream representing multiple sequences of spatially adjacent video frames. The decoded video signals are processed to provide a processed video signal representing one of the spatially related views using image information from more than one of the decoded video signals. As a result, more image data is used during processing, thereby improving the spatial and temporal image quality. | 09-06-2012 |
20120223938 | METHOD AND SYSTEM FOR PROVIDING USER CONTROL OF TWO-DIMENSIONAL IMAGE DEPTH WITHIN THREE-DIMENSIONAL DISPLAY SPACE - A system and method for providing user control of the projection of two-dimensional (2D) image information within the three-dimensional (3D) display space of a 3D-capable display device. Advantageously, the system and method disclosed herein allow a user to view 3D video even when the source video includes 2D content, by allowing the user to adjust the z-axis position of the 2D content, thereby causing the 2D content to be projected at a user-specified image depth within 3D space. The user can adjust the z-axis position of the 2D content in real time while contemporaneously viewing the imagery, e.g., via a remote control, and such adjustment can be stored for later use when similar or other 2D content is being viewed. | 09-06-2012 |
20120221883 | DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED - A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. | 08-30-2012 |
20120221758 | ELECTRONIC DEVICES USING DIVIDED MULTI CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi- connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. | 08-30-2012 |
20120192043 | LOOPBACK TESTING WITH PHASE ALIGNMENT OF A SAMPLING CLOCK AT A TEST RECEIVER APPARATUS - Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal. | 07-26-2012 |
20120191894 | DISPLAY WITH MULTIPLE VIDEO INPUTS AND PERIPHERAL ATTACHMENTS - A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link. | 07-26-2012 |
20120183215 | METHOD AND APPARATUS FOR COMPRESSION OF MULTI-SAMPLED ANTI-ALIASING COLOR DATA - The present invention provides a scheme for compressing the color components of image data, and in particular, data used in multi-sampled anti-aliasing applications. Adjacent pixels are grouped into rectangular tiles, with the sample colors stored in compressed formats accessible via an encoded pointer. In one embodiment, duplicate colors are stored once. Unlike prior compression schemes that rely on pixel to pixel correlation, the present invention takes advantages of the sample to sample correlation that exists within the pixels. A memory and graphics processor configuration incorporating the tile compression schemes is also provided. The configuration defines the tile sizes in main memory and cache memory. In one embodiment, graphics processor relies on a Tile Format Table (TFT) to process incoming tiles in compressed formats. The present invention reduces memory consumption and speeds up essential and oft-repeated operations in rendering. Thus it is valuable in the design and manufacture of graphic sub-systems. | 07-19-2012 |
20120169930 | Audio and Video Clock Synchronization - Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal. | 07-05-2012 |
20120162533 | PHYSICALLY SMALL TUNABLE NARROW BAND ANTENNA - A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna. | 06-28-2012 |
20120162250 | Displaying Compressed Supertile Images - A method for the display of compressed supertile images is disclosed. In one embodiment, a method for displaying an image frame from a plurality of compressed supertile frames includes: reading the compressed supertile frames; expanding the compressed supertile frames; and combining the expanded supertile frames to generate the image frame. The expanding can include generating an expanded supertile frame corresponding to each of the compressed supertile frames by inserting blank pixels for tiles in the expanded supertile frame that are not in the corresponding compressed supertile frame. Corresponding system and computer program products are also disclosed. | 06-28-2012 |
20120159093 | METHOD AND APPARATUS FOR DATA TRANSFER - A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements. | 06-21-2012 |
20120154411 | MULTIPLE DISPLAY FRAME RENDERING METHOD AND APPARATUS - An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays. | 06-21-2012 |
20120147020 | METHOD AND APPARATUS FOR PROVIDING INDICATION OF A STATIC FRAME - A method and apparatus provides for providing an indication of a static frame. In one example, the method and apparatus notifies the arrival of a static frame by changing a vertical blanking interval for the static frame. For example, the method and apparatus may determine that a display frame is a static frame if no graphic processing activity and/or lack of update to the frame buffer have been detected for a period of time. In response to a display frame being a static frame, the method and apparatus may change the vertical blanking interval that is immediately before the static frame by increasing the number of blanking scan lines in the vertical blanking interval. The changed vertical blanking interval may be transmitted with the static frame as an indicator of the arrival of a static frame, so that the apparatus may enter a self-refresh mode to repeatedly display the static frame. | 06-14-2012 |
20120146968 | Self-Refresh Panel Time Synchronization - In an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state. | 06-14-2012 |
20120144167 | APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE - A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. | 06-07-2012 |
20120133659 | METHOD AND APPARATUS FOR PROVIDING STATIC FRAME - A method and apparatus provides for providing a static frame. In one example, the method and apparatus divides a frame into regions and sends the divided regions of the frame from a display data transmitter, e.g., a processor such as a graphic processing unit (GPU), to a display data receiver, e.g., a timing controller (TCON). In a self-refresh mode when the frame is static, the method and apparatus detects alteration of one or more regions in the static frame. The alteration may be due to data errors in one or more regions of the static frame captured by the display data receiver and/or due to updated content (e.g., movement of a cursor) in one or more regions of the static frame in the display data transmitter. The method and apparatus then, in one example, only resends those altered regions from the display data transmitter to the display data receiver to redress the alteration. | 05-31-2012 |
20120131596 | Method and System for Synchronizing Thread Wavefront Data and Events - Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed. | 05-24-2012 |
20120127689 | INTEGRATED PACKAGE CIRCUIT WITH STIFFENER - The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. | 05-24-2012 |
20120127367 | METHOD AND APPARATUS FOR PROVIDING TEMPORAL IMAGE PROCESSING USING MULTI-STREAM FIELD INFORMATION - An apparatus and method provides temporal image processing by producing, for output on a single link such as a single cable or wireless interface, packet based multi-steam information wherein one stream provides at least frame N information for temporal imaging processing and a second stream that provides frame N−1 information for the same display, such as a current frame and a previous frame or a current frame and next frame. The method and apparatus also outputs the packet based multi-stream information and sends it for the same display for use by the same display so that the receiving display may perform temporal image processing using the multi-stream multi-frame information sent with a single link. | 05-24-2012 |
20120110309 | Data Output Transfer To Memory - Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory. | 05-03-2012 |
20120096218 | APPARATUS AND METHODS FOR TUNING A MEMORY INTERFACE - The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device. | 04-19-2012 |
20120075353 | System and Method for Providing Control Data for Dynamically Adjusting Lighting and Adjusting Video Pixel Data for a Display to Substantially Maintain Image Display Quality While Reducing Power Consumption - System and method for providing control data for dynamically adjusting lighting and adjusting video pixel data for a display to substantially maintain image display quality while reducing power consumption. In accordance with one or more embodiments, image statistics, e.g., histogram data representing luma values corresponding to pixels for a video frame, are analyzed to determine whether the pixels represent one or more of a plurality of images which includes an image containing primarily natural imagery, an image containing primarily graphics imagery, and an image containing a combination of at least respective portions of natural and graphics imagery. Based on such analysis, control data are provided to enable light source brightness reduction by one of a plurality of percentages and pixel brightness increases, e.g., in accordance with one of a plurality of multiple-segment piecewise linear curves defined in accordance with respective segment slopes, thresholds, and threshold offsets in accordance with whether the incoming pixel data primarily represents a natural image, primarily represents a graphics image, or represents a combination of natural and graphics images. | 03-29-2012 |
20120070094 | VARIABLE-LENGTH CODE DECODER - An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers. | 03-22-2012 |
20120066640 | APPARATUS FOR PROVIDING MULTI-MODE WARPING OF GRAPHICAL USER INTERFACE OBJECTS - Apparatus provides for providing multi-mode warping of graphical user interface (GUI) objects, such as but not limited to a pointing object (e.g., cursor) and a window. In one example, the apparatus includes logic operative to provide a user interface that allows a user to select different warping modes. In one example, a user may select a pointing object warping mode and/or a window warping mode. In the pointing object warping mode, the apparatus applies a warp operation to one or more pointing objects that uses display content information to determine where to move the pointing object. In the window warping mode, the apparatus applies a warp operation to one or more windows that also uses display content information to determine where to move the window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content. | 03-15-2012 |
20120066624 | METHOD AND APPARATUS FOR CONTROLLING MOVEMENT OF GRAPHICAL USER INTERFACE OBJECTS - A method and apparatus provides for controlling movement of one or more graphical user interface (GUI) objects such as a cursor and/or a window. In one example, the method and apparatus applies a warp operation to the GUI object that uses display content information to determine where to move the cursor and/or window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content. The display content may be any visible object to be displayed on the display screen, including but is not limited to, windows, taskbars, sidebars, docks, program launchers, icons, controls, and background (wallpaper). The warp operation may be an immediate relocation of the GUI object to the destination position without any user intervention during the relocation. | 03-15-2012 |
20120047526 | System and Method for Mapping Audio and Video Streams from Audio/Video Source to Multiple Audio/Video Sinks - System and method for mapping audio and video streams from an audio/video (AV) source to respective ones of a plurality of AV sinks. In accordance with one or more embodiments, the audio and video playback and content protection capabilities of each one of the AV sinks are determined based on AV data received via a video channel interface from each one of the AV sinks. Also determined are the audio and video streams available from the AV source. Respective ones of the audio and video streams available from the AV source are mapped to each one of the AV sinks in accordance with their audio and video playback and content protection capabilities. | 02-23-2012 |
20120038835 | STAND-BY MODE TRANSITIONING - A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality. | 02-16-2012 |
20120030488 | METHOD AND APPARATUS FOR INDICATING MULTI-POWER RAIL STATUS OF INTEGRATED CIRCUITS - Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal. | 02-02-2012 |
20120025870 | METHOD AND APPARATUS FOR VOLTAGE LEVEL SHIFTING WITH CONCURRENT SYNCHRONIZATION - Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal. | 02-02-2012 |
20120019543 | MULTI-THREAD GRAPHICS PROCESSING SYSTEM - A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads. | 01-26-2012 |
20120017118 | METHOD AND APPARATUS FOR TESTING AN INTEGRATED CIRCUIT INCLUDING AN I/O INTERFACE - Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz. | 01-19-2012 |
20120002873 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 01-05-2012 |
20120001925 | Dynamic Feedback Load Balancing - A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating. | 01-05-2012 |
20120001905 | Seamless Integration of Multi-GPU Rendering - A computer based rendering system is provided. The computer based rendering system includes an abstraction mechanism to provide configuring instructions to two or more processors, the configuring instructions being operative to facilitate scene rendering. The configuring provides processor setup instructions to at least one driver. Each of the two or more processors renders a respective portion of the scene independent of the other of the processors. | 01-05-2012 |
20110320890 | DATA TRANSMISSION APPARATUS WITH INFORMATION SKEW AND REDUNDANT CONTROL INFORMATION AND METHOD - Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed. | 12-29-2011 |
20110279156 | PROGRAMMABLE FINE LOCK/UNLOCK DETECTION CIRCUIT - An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition. | 11-17-2011 |
20110268425 | POWER MANAGEMENT IN MULTI-STREAM AUDIO/VIDEO DEVICES - A method of managing power consumption in a video device capable of displaying encoded multi-stream video is disclosed. Power reduction is achieved by limiting the amount of video and audio decoding and processing performed on at least some of the encoded streams, by taking particular application contexts into account. In a normal power consumption mode, audio/video data from all streams are decoded and digitally processed for output. In response to detecting a reduced power consumption mode, audio/video from at least some of the streams are processed in a modified manner to reduce power consumption. | 11-03-2011 |
20110255002 | METHOD AND APPARATUS FOR DISPLAY OF A DIGITAL VIDEO SIGNAL - A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels. | 10-20-2011 |
20110254154 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 10-20-2011 |
20110242142 | MULTIPLE DISPLAY CHROMINANCE AND LUMINANCE METHOD AND APPARATUS - An apparatus includes a chrominance and luminance module. The chrominance and luminance module obtains display characteristics of each of a plurality of displays. The chrominance and luminance module selectively adjusts, on a per display basis, chrominance and luminance for each of the displays based on the display characteristics. In one example, the displays collectively display a single large surface. | 10-06-2011 |
20110225813 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 09-22-2011 |
20110219190 | CACHE WITH RELOAD CAPABILITY AFTER POWER RESTORATION - A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache. | 09-08-2011 |
20110216077 | GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER - A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer. | 09-08-2011 |
20110215823 | APPARATUS AND METHOD FOR MONITORING CURRENT FLOW TO INTEGRATED CIRCUIT IN TEMPERATURE-COMPENSATED MANNER - A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate. | 09-08-2011 |
20110211074 | FIELD SEQUENCE DETECTOR, METHOD AND VIDEO DEVICE - A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences. | 09-01-2011 |
20110164065 | Method And Apparatus For Configuring Display Bezel Compensation For A Single Large Surface Display Formed By A Plurality Of Displays - A method includes displaying, on a single large surface display, a first moveable and second fixed portion of a visual test object. The first portion is displayed on the display to be configured and the second portion is displayed on at least one neighboring display, and are shown in a relative orientation adjacent to a common border formed by a first bezel of the display to be configured and a second bezel of the at least one neighboring display, and any space in between. The method obtains bezel compensation configuration information in response to input aligning the first portion with the second portion. A user may provide input by moving the first portion to align it with the second portion so that a third portion of the visual test object appears hidden by the common border. The object therefore appears aligned “behind” the bezel. | 07-07-2011 |
20110161547 | METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL - A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol. | 06-30-2011 |
20110157302 | THREE-DIMENSIONAL VIDEO DISPLAY SYSTEM WITH MULTI-STREAM SENDING/RECEIVING OPERATION - A three-dimensional processing circuit includes a multi-stream 3D image sender that produces packet based multi-stream information that includes a first stream that has first eye view information, such as left eye frame information and a second stream that includes corresponding second eye view information, such as right eye frame information, for display on a single display, wherein each stream comprises a same object viewed from differing view perspectives. In one example, the multi-stream information is communicated as packetized data over a single cable, for example wherein a packet includes both the left eye and right eye information. In addition, the encoder provides as part of the multi-stream information, control information indicating that the first and second streams are for a single display. In one example, the multi-streams are communicated concurrently so that the single display can display stereoscopic left and right eye frame information. A corresponding receiver is also disclosed that decodes the packet based multi-stream information and combines the decoded left eye frame information and corresponding right eye information for a 3D viewing effect. In one example this may be based on control information associated with the packet based multi-stream information. Related methods are also set forth. | 06-30-2011 |