| ASMEDIA TECHNOLOGY INC. Patent applications |
| Patent application number | Title | Published |
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| 20160135291 | PRINTED CIRCUIT BOARD STRUCTURE - A printed circuit board structure includes a main body and a connecting interface. The connecting interface connects and is located at a side of the main body. The connecting interface includes conductive layers and insulation layers. The conductive layers at least include a first, a second, a third, a fourth conductive layer. The insulation layers at least include a first, a second, a third insulation layers. The insulation layers and the conductive layers are alternately disposed. The first insulation layer is located between the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer are partially overlapped in their orthographic projections on the first insulation layer. The second insulation layer is located between the second conductive layer and the third conductive layer. The third insulation layer is located between the third conductive layer and the fourth conductive layer. | 05-12-2016 |
| 20140365713 | ELECTRONIC SYSTEM AND OPERATING METHOD THEREOF - An electronic system and an operating method thereof are provided. When a computer host is booting up and an external storage device is connected with the computer host, the BIOS of the computer host may read the parameter information recorded in a memory of a bridge unit via a bridge unit of the external device and displays the parameter information without initializing the storage unit and reading the parameter information from a magnetic region of the storage unit. | 12-11-2014 |
| 20140359247 | METHOD FOR DATA MANAGEMENT - A method for data management adapted for a host controller to store device context data of a universal serial bus (USB) device is provided, and the host controller includes a memory. The method includes following steps: storing a device slot index table in the memory; allocating a plurality of memory blocks in the memory according to state information of the USB device when it is detected that the USB device is coupled to the host controller, so as to store the device context data of the USB device, and storing an initial address of the memory blocks in the device slot index table; and releasing the memory blocks and erasing the initial address of the memory blocks stored in the device slot index table when it is detected that the USB device is detached from the host controller. | 12-04-2014 |
| 20140351510 | DISK ARRAY SYSTEM AND DATA PROCESSING METHOD - A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command. and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command. | 11-27-2014 |
| 20140351509 | DISK ARRAY SYSTEM AND DATA PROCESSING METHOD - A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided. | 11-27-2014 |
| 20140325198 | ELECTRONIC DEVICE AND LOADING METHOD OF CONTROL PROGRAM - An electronic device comprises a first memory unit, a processing unit and an operating interface. The processing unit is electronically connected to the first memory unit. The operating interface is electronically connected to the processing unit. When the processing unit is communicated with a host device via the operating interface, the processing unit executes a loading program and transmits a notification signal to the host device. The host device transmits at least one control program to the first memory unit according to the notification signal. When the control program is transmitted, the processing unit is reset and then executes the control program stored in the first memory unit. The stored firmware can be added or modified, and the circuit layout is simplified. | 10-30-2014 |
| 20140218000 | VOLTAGE REGULATOR CIRCUIT - A voltage regulator circuit includes a soft start module, a pulse width modulation (PWM) module, and a voltage regulator module. The soft start module is used to receive a current feedback voltage corresponding to an input current, and compare the current feedback voltage with a comparison voltage, so as to output a switching signal. The PWM module is used to receive a clock signal and the switching signal, and determine a first PWM signal and a second PWM signal outputted by the PWM module is a high voltage level or a low voltage level according to the clock signal and the switching signal. The voltage regulator module is used to receive and adjust an output voltage corresponding to the first PWM signal and the second PWM signal. | 08-07-2014 |
| 20140217963 | PROTECTIVE CIRCUIT - A protective circuit is provided. The protective circuit includes a charging unit, a voltage regulating unit, and a comparing unit. The charging unit receives a rise signal and an over-current signal, and outputs a first reference voltage. The voltage regulating unit receives the first reference voltage and adjusts an output voltage according, to the first reference voltage and a feedback voltage. The comparing unit receives the feedback voltage and compares the feedback voltage with a first threshold voltage to determine whether to output the rise signal to the charging unit. | 08-07-2014 |
| 20140208125 | ENCRYPTION AND DECRYPTION DEVICE FOR PORTABLE STORAGE DEVICE AND ENCRYPTION AND DECRYPTION METHOD THEREOF - An encryption and decryption device for a portable storage device and an encryption and decryption method thereof are provided. The encryption and decryption device includes a storage element, a control element and an encryption and decryption circuit. The control element receives a password, saves the password to the storage element and provides an encryption and decryption command. The encryption and decryption circuit is electrically connected to a portable storage device, receives the encryption and decryption command, reads the password stored in the storage element according to the encryption and decryption command, and encrypts or decrypts data stored in the portable storage device by utilizing the password according to whether the data have been encrypted. After the data are encrypted or decrypted, the encryption and decryption circuit clears the password in the storage element. | 07-24-2014 |
| 20140189189 | COMPUTER ARBITRATION SYSTEM, BANDWIDTH, ALLOCATION APPARATUS, AND METHOD THEREOF - The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth arbitration module is used to select one downstream device from the high bandwidth downstream device group for allowing uplink. The low bandwidth arbitration module is used to select one downstream device from the low bandwidth downstream device group for allowing uplink. The multiplexer selects the one of the access requests from the high bandwidth arbitration module or the low bandwidth arbitration module for allowing to uplink the access request to an upstream device. The access transmission times of the high bandwidth arbitration module and the low bandwidth arbitration module are counted respectively by a counting circuit. | 07-03-2014 |
| 20140181584 | DEBUGGING SYSTEM OF INTEGRATED CIRCUIT AND DEBUGGING METHOD THEREOF - A debugging method of an integrated circuit is disclosed. The debugging method is applied to an integrated circuit and a debugging system. The debugging method includes the following steps: selecting an error event of the integrated circuit; selecting a plurality of observing signals of the integrated circuit; storing values of the observing signals at a time point and embedding values of the observing signals in an observing packet to output the observing packet when the error event happens at the time point; outputting the observing packet and a plurality of data packets of the integrated circuit sequentially according to a priority value table; encoding the observing packet to output a plurality of output signals; and outputting the output signals via a transmission interface of the debugging system. | 06-26-2014 |
| 20130268746 | SYSTEM-ON-CHIP AND BOOTING METHOD THEREOF - A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process. | 10-10-2013 |
| 20130234668 | UNIVERSAL SERIAL BUS APPARATUS AND POWER SUPPLY METHOD THEREOF - A power supply method for an universal serial bus apparatus is provided. The USB apparatus includes an upstream port module and a plurality of downstream port modules. The power supply method comprises the following steps: setting a maximum charging port number for the downstream port modules according to the connection configuration between the upstream port module and a host, and the condition of power supply from an external power supply; detecting the coupling condition of the electronic apparatuses to the downstream port modules so as to customize a specific charging specification for one of the electronic apparatuses; respectively providing a plurality of power to the electronic apparatuses according to the specific charging specification and the maximum charging port number. Thus, the electronic apparatuses enable to be charged with maximum charging currents and operate normally under the USB specification without being affected. | 09-12-2013 |
| 20130232285 | CONTROL METHOD OF FLOW CONTROL SCHEME AND CONTROL MODULE THEREOF - A control method of flow control scheme and a control module thereof are provided. The provided control method includes setting a value of the transaction packets and outputting data to an external device according to the value of the transaction packets. When a not-ready transaction packet is received, the value of the transaction packets is reduced and the data is transmitted according to the value of the transaction packets. | 09-05-2013 |
| 20130191661 | EXTERNAL ELECTRONIC DEVICE - An external electronic device connected to an electronic device which includes a first transmission interface is provided. The external electronic device includes a power control module, a data control module, a second transmission interface and a switch module. The power control module receives an external power. The second transmission interface corresponds to the first transmission interface. The switch module controls the second transmission interface to electrically connect to the power control module or the data control module, and thus the external electronic device enters a power mode or a transfer mode. | 07-25-2013 |
| 20130185549 | ELECTRONIC DEVICE AND BIOS UPDATING DEVICE THEREOF - An electronic device and a basic input/output system (BIOS) updating device thereof are provided. The electronic device includes a central processing unit (CPU), a chipset, a first interface circuit and a second interface circuit. The chipset is coupled to the CPU. The first interface circuit is coupled to a first memory and a second memory. The first memory includes a first BIOS file and the second memory includes a second BIOS file. The second interface circuit is coupled to the first interface circuit and an external storage device. When the external storage device includes a third BIOS file, a target memory is selected from the first memory and second memory according to a first rule and the target memory is updated using the third BIOS file. Thus, BIOS firmware of the electronic device can be safely updated. | 07-18-2013 |
| 20130089122 | METHOD FOR ADAPTIVELY DRIVING DATA TRANSMISSION AND COMMUNICATION DEVICE USING THE SAME - A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter. | 04-11-2013 |
| 20130043848 | REFERENCE CURRENT GENERATION CIRCUIT - A reference current generation circuit is provided, in which a current generated according to a bandgap voltage is not directly used as a reference current, but the current generated according to the bandgap voltage is used to adjust an output reference current. In this way, the reference voltage is generated without using an external resistor, so as to effectively decrease the production cost. | 02-21-2013 |
| 20120284498 | FLASH DEVICE AND ASSOCIATED BOOTING METHOD - A flash device and a booting method thereof are provided. The booting method includes following steps: executing a basic boot program stored in a read only memory (ROM) of a flash memory micro-controller; reading a specific flash memory configuration parameter and a revision program from a flash memory; loading a main program stored in the flash memory; and executing the revision program and loading the main program stored in the flash memory when the main program fails to be loaded. | 11-08-2012 |
| 20120191885 | METHOD FOR CONFIGURING CHARGING PORTS AND CONTROLLER APPLYING THE SAME - A method for configuring charging ports and a controller applying the same are disclosed. The method includes recording a maximum permission value and a permitted value, and comparing the maximum permission value and the permitted value to determine whether the interface port can be used as a charging port when a device is connected to an interface port. | 07-26-2012 |
| 20100169555 | METHOD OF WRITING DATA INTO FLASH MEMORY BASED ON FILE SYSTEM - A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position. | 07-01-2010 |
| 20100153755 | VID PROCESSOR, VOLTAGE GENERATING CIRCUIT AND GENERATING METHOD - A VID processor includes a plurality of buffers, comparators, multiplexers and a core processing unit. The buffer may store a plurality of parameter values and a plurality of offset values. The buffers storing the parameter values may be coupled to the corresponding comparators, and other buffers may be coupled to the corresponding multiplexers. The comparator may compare the VID with the parameter values in the coupled buffer and output a selecting signal to the corresponding multiplexer according to the comparison outcome. Thus, the multiplexer may select and output one of the offset values to the core processing unit from the coupled buffer to allow the core processing unit to adjust the VID according to the output of the multiplexer. | 06-17-2010 |
| 20100153754 | METHOD FOR TRANSFORMING VOLTAGE IDENTIFICATION CODE OF A MICROPROCESSOR - The disclosure is related to a method for transforming voltage identification codes of a microprocessor. The method comprises the steps of: receiving a first voltage identification code of a first voltage regulation standard, wherein the first voltage identification code is in correspondence with a first voltage; and transforming the first voltage identification code into a second voltage identification code of a second voltage regulation standard, wherein the second voltage identification code is in correspondence with a second voltage, and the second voltage is the same as the first voltage. | 06-17-2010 |
| 20100149002 | METHOD FOR CONVERTING VOLTAGE IDENTIFICATION CODE AND COMPUTER SYSTEM - The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range. | 06-17-2010 |
| 20100077248 | CLOCK GENERATING DEVICE, METHOD THEREOF AND COMPUTER SYSTEM USING THE SAME BACKGROUND OF THE INVENTION - A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned. | 03-25-2010 |
| 20090248965 | HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size. | 10-01-2009 |
| 20090241195 | DEVICE AND METHOD FOR PREVENTING VIRUS INFECTION OF HARD DISK - A device and a method for preventing virus infection of a hard disk are provided. The virus infection preventing device includes a storage media, a read-only memory, a control circuit and a switch. The virus infection preventing method includes steps of generating either a first signal or a second signal by a switch, and receiving a write command. If the write command allows data to be written into a boot sector of the hard disk and the first signal is generated by the switch, the write command is aborted. Whereas, if the write command allows data to be written into the boot sector of the hard disk and the second signal is generated by the switch, the write command is executed. | 09-24-2009 |
| 20090210758 | METHOD FOR REDUCING DATA ERROR WHEN FLASH MEMORY STORAGE DEVICE USING COPY BACK COMMAND - A method for a flash memory storage device to use a copy back command includes the following steps. The method includes the step of copying a data in a first block of a flash memory to a buffer outside the flash memory, checking if the data in the buffer is correct, and copying the data in the first block of the flash memory to a second block in the flash memory when the data in the buffer is correct. | 08-20-2009 |
| 20090172264 | SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS - A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory. | 07-02-2009 |
