| ARM Limited Patent applications |
| Patent application number | Title | Published |
|---|
| 20160100172 | DATA PROCESSING SYSTEMS - A data processing system comprises a video processor ( | 04-07-2016 |
| 20160098814 | DATA PROCESSING SYSTEMS - A video processing system comprises a video processor and an output buffer. When a new frame is to be written to the output buffer, the video processing system determines ( | 04-07-2016 |
| 20160042491 | DATA PROCESSING SYSTEMS - A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer | 02-11-2016 |
| 20160026202 | SWITCHING REGULATOR OVERLOAD DETECTOR - A method, apparatus, and device provide for the detection of the adequacy of the current sourcing capability of a power source. The current sourcing capability of the power source is dynamically detected by sampling comparison values obtained during one or more sampling sub-windows and determining a sample density of comparison values. In response to the sample density of comparison values crossing a selectable density threshold, an insufficient-supply indication is generated. | 01-28-2016 |
| 20160005140 | GRAPHICS PROCESSING - A graphics processing pipeline ( | 01-07-2016 |
| 20150356953 | DISPLAY CONTROLLER - A display controller comprises an input stage | 12-10-2015 |
| 20150349760 | DATA AND CLOCK SIGNAL VOLTAGES WITHIN AN INTEGRATED CIRCUIT - An integrated circuit | 12-03-2015 |
| 20150339852 | GRAPHICS PROCESSING SYSTEMS - When rendering a region of a three-dimensional object represented by a base set of polygon vertices in a graphics processing pipeline, a first processing stage uses meta-information representative of the surface relief of the region of the three-dimensional object to determine whether to generate a set of additional polygon vertices over the region of the three-dimensional object, and generates the additional set of polygon vertices (when this is deemed necessary). A second processing stage then uses information representative of the surface relief of the region of the three-dimensional object to modify the positions of one or more of the polygon vertices, before the vertices are assembled into primitives that are then rasterised and rendered. | 11-26-2015 |
| 20150317763 | GRAPHICS PROCESSING SYSTEMS - A tile based graphics processing pipeline comprises a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a processing stage | 11-05-2015 |
| 20150310791 | METHOD OF AND APPARATUS FOR PROCESSING DATA FOR A DISPLAY - A data processing system | 10-29-2015 |
| 20150302545 | GRAPHICS PROCESSING SYSTEMS - A graphics processing system includes a graphics processor and a memory for storing data to be used by and generated by the graphics processor. In a first rendering pass, the graphics processor generates an array of graphics data and stores the generated array of graphics data in the memory. The array of graphics data generated in the first rendering pass is used in a subsequent rendering pass. In the first rendering pass, the graphics processor determines one or more regions of the array of graphics data that have a particular characteristic, and generates information indicative of the one or more regions. In the subsequent rendering pass, the graphics processor uses the information indicative of the one or more regions to control the reading of the array of graphics data when it is to be used in the subsequent rendering pass. | 10-22-2015 |
| 20150302193 | PARALLEL SNOOP AND HAZARD CHECKING WITH INTERCONNECT CIRCUITRY - A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction. | 10-22-2015 |
| 20150293776 | DATA PROCESSING SYSTEMS - A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. An accelerator provides a shared resource for a plurality of the applications and has one or more input/output interfaces for the submission of tasks to the accelerator from an application. A hypervisor manages the allocation of the input/output interfaces to the one or more operating systems and a hypervisor interface enables communication between the hypervisor and the accelerator. The system is capable of being configured such that an operating system that has been allocated an input/output interface is capable of communicating with the accelerator via the input/output interface independently of the hypervisor. A memory management unit is capable of providing an isolated region of a memory for use by the operating system whilst the operating system retains its allocated input/output interface. | 10-15-2015 |
| 20150293775 | DATA PROCESSING SYSTEMS - A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor. | 10-15-2015 |
| 20150293774 | DATA PROCESSING SYSTEMS - A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialise one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface. | 10-15-2015 |
| 20150269982 | WORDLINE PULSE DURATION ADAPTATION IN A DATA STORAGE APPARATUS - Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells. | 09-24-2015 |
| 20150269981 | PREDICTING SATURATION IN A SHIFT OPERATION - Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results. | 09-24-2015 |
| 20150269773 | GRAPHICS PROCESSING SYSTEMS - A set of primitives is divided into plural sub-sets of primitives, and a tree representation for representing the set of primitives in which each leaf node of the tree represents one of the sub-sets, and each parent node of the tree represents a sub-set of primitives corresponding to the combination of the sub-sets of primitives of all of its child nodes, is generated. For each node of the tree representation data indicating: the sub-set of primitives that the node represents; the vertices that are used by the primitives in the sub-set of primitives that the node represents; and the volume of space that the sub-set of primitives that the node represents falls within, is determined. The tree representation is then used to determine a set of primitives and a set of vertices to be processed when processing the set of primitives for the output frame. | 09-24-2015 |
| 20150261700 | INTERRUPT SIGNAL ARBITRATION - An interrupt controller includes a priority level arbitrator ( | 09-17-2015 |
| 20150261542 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING DATA PROCESSING OPERATION WITH A CONDITIONAL PROCESSING STEP - A data processing apparatus has a pipeline for performing a processing operation involving a conditional step which is required only if at least one input operand satisfies a predetermined condition. Control circuitry detects whether the condition is satisfied. If not, then the pipeline is controlled to perform the operation bypassing the conditional step to generate the output operand a first number of cycles later than a start cycle in which the operation starts, and the output operand is forwarded over a forwarding path. If the condition is satisfied, then the pipeline performs the operation including the conditional step to generate the output operand a second number of cycles later than the start cycle, where the second number is greater than the first number. The output operand is written to a destination register the same number of cycles later than the start cycle regardless of whether the condition is satisfied. | 09-17-2015 |
| 20150261498 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A SHIFT FUNCTION ON A BINARY NUMBER - A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number. Once the count value is available from the count determination circuitry, fine shifting circuitry then performs a further shift operation on the intermediate binary number, based on the count value output by the count determination circuitry, in order to produce the result binary number. This provides an efficient mechanism for performing a shift function on a binary number, whilst still capturing the count value from the count determination circuitry. | 09-17-2015 |
| 20150254066 | DATA PROCESSING APPARATUS AND METHOD FOR MULTIPLYING FLOATING POINT OPERANDS - A data processing apparatus and method are provided for multiplying first and second normalised floating point operands in order to generate a result, each normalised floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalised version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalised floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalised result significand. Thereafter, the normalised result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, whilst correctly rounding the result in situations where the result is subnormal. | 09-10-2015 |
| 20150248138 | STORAGE CIRCUITRY AND METHOD FOR PROPAGATING DATA VALUES ACROSS A CLOCK BOUNDARY - A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronisation circuitry then receives the write pointer and synchronises the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer. However, for a read operation to be performed, it is necessary that the synchronised write pointer indication indicates that there is a data value written into the storage structure that is available to be read. Early update circuitry is configured, for a write operation, to alter the write pointer indication provided to the write pointer synchronisation circuitry a number of clock cycles of the first clock domain before the write operation is performed. That number of clock cycles is chosen dependent on the difference in clock speed between the first clock domain and the second clock domain, and the predetermined number of clock cycles of the second clock domain taken by the write pointer synchronisation circuitry to synchronise the write pointer indication to the second clock domain. Such an approach enables at least a part of the latency of the write pointer synchronisation circuitry to be hidden, thereby improving performance of the storage circuitry. | 09-03-2015 |
| 20150244371 | LEVEL CONVERSION CIRCUIT AND METHOD - A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path. | 08-27-2015 |
| 20150242331 | CONTROLLING ACCESS TO A MEMORY - A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state. After power-up, a power-on-reset signal causes the memory status value to indicate the enabled state. In response to the assertion from a received control signal a memory kill signal is generated by the memory protection device which causes the memory status value to switch to its disabled state and the memory status value then cannot be changed back to the enabled state without a power reset. The memory status value being in the disabled state causes enable signal generation circuitry of the memory to openly be able to generate its read enable signal and write enable signal in a disabled state, thus preventing access to the memory. | 08-27-2015 |
| 20150242319 | INVALIDATING STORED ADDRESS TRANSLATIONS - A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs. | 08-27-2015 |
| 20150235384 | METHOD OF AND APPARATUS FOR ENCODING AND DECODING DATA - Each block of texture data elements is encoded as a block of texture data that includes: data indicating how to generate a set of data values to be used to generate data values for a set of the texture data elements that the block represents; data indicating a set of integer values to be used to generate the set of data values to be used to generate data values for a set of the texture data elements that the block represents; data indicating a set of index values indicating how to use the generated set of data values to generate data values for texture data elements of the set of texture data elements that the generated set of data values is to be used for; and data indicating the indexing scheme that has been used for the block. | 08-20-2015 |
| 20150228050 | Method Of And Apparatus For Encoding And Decoding Data - When encoding a texture map | 08-13-2015 |
| 20150227367 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SEGMENTED OPERATIONS - A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved. | 08-13-2015 |
| 20150226800 | MEASUREMENT CIRCUITRY AND METHOD FOR MEASURING A CLOCK NODE TO OUTPUT NODE DELAY OF A FLIP-FLOP - A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop. | 08-13-2015 |
| 20150213177 | COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR GENERATING A LAYOUT OF A CELL DEFINING A CIRCUIT COMPONENT - The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology. | 07-30-2015 |
| 20150212972 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SCAN OPERATIONS - A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store configured to store vector operands, and processing circuitry configured to perform operations on vector operands retrieved from said vector register store. Further, control circuitry is configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand. The control circuitry is responsive to the vector scan instruction to partition the N vector elements of the specified vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry to perform a partitioned scan operation yielding the same result as the defined scan operation. The processing circuitry is configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the sequence contained within each group to produce intermediate results for each group, and to perform a computation operation to combine the intermediate results into a final result vector operand containing a sequence of result vector elements. The partitioned scan operation approach of the present invention enables a balance to be achieved between energy consumption and performance. | 07-30-2015 |
| 20150200651 | MASTER-SLAVE FLIP-FLOP CIRCUIT AND METHOD OF OPERATING THE MASTER-SLAVE FLIP-FLOP CIRCUIT - A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop. | 07-16-2015 |
| 20150193969 | GRAPHICS PROCESSING - A graphics processor includes a vertex shader | 07-09-2015 |
| 20150162918 | DIGITAL OUTPUT CLOCK GENERATION - An on-chip clock signal generation apparatus is provided which is configured to generate an output clock signal to be passed off-chip in association with an output data signal. The apparatus comprises: an input configured to receive an input clock signal and clock phase generation circuitry configured to generate a plurality of candidate clock signals in dependence on the input clock signal. The candidate clock signals are phase-shifted with respect to one another. Selection circuitry is configured to select and output one of the candidate clock signals as the output clock signal in dependence on at least one selection signal. All components of the apparatus are embodied as digital components. | 06-11-2015 |
| 20150149809 | SYNCHRONOUS BRIDGE CIRCUITRY AND A METHOD OF TRANSFERRING DATA USING ASYNCHRONOUS BRIDGE CIRCUITRY - Asynchronous bridge circuitry provides data communication between source circuitry | 05-28-2015 |
| 20150138901 | MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST - Within a memory | 05-21-2015 |
| 20150137864 | CIRCUIT DELAY MONITORING APPARATUS AND METHOD - A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period. | 05-21-2015 |
| 20150134933 | ADAPTIVE PREFETCHING IN A DATA PROCESSING APPARATUS - A data processing apparatus and method of data processing are disclosed. An instruction execution unit executes a sequence of program instructions, wherein execution of at least some of the program instructions initiates memory access requests to retrieve data values from a memory. A prefetch unit prefetches data values from the memory for storage in a cache unit before they are requested by the instruction execution unit. The prefetch unit is configured to perform a miss response comprising increasing a number of the future data values which it prefetches, when a memory access request specifies a pending data value which is already subject to prefetching but is not yet stored in the cache unit. The prefetch unit is also configured, in response to an inhibition condition being met, to temporarily inhibit the miss response for an inhibition period. | 05-14-2015 |
| 20150130390 | ELECTRONICALLY CONTROLLED UNIVERSAL MOTOR - An electric motor apparatus comprising: a stator component and a rotor component rotationally mounted coaxially with and within the stator component. The stator component and the rotor component each comprise windings configured to generate an electromagnetic field from an electric current. The electric motor further comprises an intermediate screening component rotationally mounted between the stator component and the rotor component and configured to provide at least some magnetic screening between the rotor component and the stator component. The intermediate screening component comprises at least some magnetically active sections configured such that changing magnetic fields generated by changing electric currents in the windings on either the rotor component or the stator component generate a force on the magnetically active sections causing the intermediate screening component to rotate; and control circuitry for independently controlling power supplied to the windings on the rotor component and the stator component in dependence upon a desired output rotational speed. | 05-14-2015 |
| 20150128144 | DATA PROCESSING APPARATUS AND METHOD FOR PROCESSING A PLURALITY OF THREADS - A data processing apparatus has processing circuitry for processing threads each having thread state data. The threads may be processed in thread groups, with each thread group comprising a number of threads processed in parallel with a common program executed for each thread. Several thread state storage regions are provided with fixed number of thread state entries for storing thread state data for a corresponding thread. At least two of the storage regions have different fixed numbers of entries. The processing circuitry processes as the same thread group threads having thread state data stored in the same storage region and processes threads having thread state data stored in different storage regions as different thread groups. | 05-07-2015 |
| 20150121038 | PREFETCH STRATEGY CONTROL - A single instruction multiple thread (SIMT) processor | 04-30-2015 |
| 20150121019 | DATA PROCESSING DEVICE AND METHOD FOR INTERLEAVED STORAGE OF DATA ELEMENTS - A data processing device | 04-30-2015 |
| 20150121014 | DATA PROCESSING METHOD AND APPARATUS FOR PREFETCHING - A data processing device includes processing circuitry | 04-30-2015 |
| 20150117119 | MEMORY CIRCUITRY WITH WRITE ASSIST - Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage. | 04-30-2015 |
| 20150100768 | SCHEDULING PROGRAM INSTRUCTIONS WITH A RUNNER-UP EXECUTION POSITION - A single instruction multiple thread (SIMT) processor | 04-09-2015 |
| 20150091609 | INTEGRATED CIRCUIT WITH SIGNAL ASSIST CIRCUITRY AND METHOD OF OPERATING THE CIRCUIT - An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption. | 04-02-2015 |
| 20150085586 | MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE - A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells. | 03-26-2015 |
| 20150084983 | METHOD AND APPARATUS FOR GENERATING AN OUTPUT SURFACE FROM ONE OR MORE INPUT SURFACES IN DATA PROCESSING SYSTEMS - In a data processing system, an output surface, such as frame to be displayed, is generated as a plurality of respective regions with each respective region of the output surface being generated from a respective region or regions of one or more input surfaces. When a new version of the output surface is to be generated | 03-26-2015 |
| 20150084982 | METHOD AND APPARATUS FOR GENERATING AN OUTPUT SURFACE FROM ONE OR MORE INPUT SURFACES IN DATA PROCESSING SYSTEMS - In a data processing system, an output surface, such as frame to be displayed, is generated as a plurality of respective regions with each respective region of the output surface being generated from a respective region or regions of one or more input surfaces. When a new version of the output surface is to be generated | 03-26-2015 |
| 20150070372 | IMAGE PROCESSING APPARATUS AND A METHOD OF STORING ENCODED DATA BLOCKS GENERATED BY SUCH AN IMAGE PROCESSING APPARATUS - An image processing apparatus and method including an encoder circuitry for generating encoded data blocks from input data blocks of an image, and write circuitry for storing the encoded data blocks to memory for subsequent access by decoding circuitry. For each input data block, identifier generation circuitry generates an identifier value that is dependent on the input data block. A lookup storage stores predetermined information relating to at least one encoded data block and stored within the lookup storage in association with the identifier value for the corresponding input data block. For a current input data block, a check is performed to determine whether a match exists between the identifier value generated for the current input data block and an identifier value stored in the lookup storage. In a match, the predetermined information is used by the write circuitry when performing the required write operation. | 03-12-2015 |
| 20150049568 | MEMORY ACCESS CONTROL IN A MEMORY DEVICE - A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed. | 02-19-2015 |
| 20150049563 | MEMORY DEVICE AND METHOD OF PERFORMING ACCESS OPERATIONS WITHIN SUCH A MEMORY DEVICE - A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal. | 02-19-2015 |
| 20150039968 | ERROR CODE MANAGEMENT IN SYSTEMS PERMITTING PARTIAL WRITES | 02-05-2015 |
| 20150039665 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION - A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N| 02-05-2015 | |
| 20150032970 | PERFORMANCE OF ACCESSES FROM MULTIPLE PROCESSORS TO A SAME MEMORY LOCATION - A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item. | 01-29-2015 |
| 20150032969 | COHERENCY CONTROL MESSAGE FLOW - A coherent memory system includes a plurality of level 1 cache memories | 01-29-2015 |
| 20150012713 | DATA PROCESSING APPARATUS HAVING FIRST AND SECOND PROTOCOL DOMAINS, AND METHOD FOR THE DATA PROCESSING APPARATUS - A data processing apparatus ( | 01-08-2015 |
| 20150009772 | MEMORY HAVING POWER SAVING MODE - A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode. | 01-08-2015 |
| 20140373171 | SECURITY PROTECTION OF SOFTWARE LIBRARIES IN A DATA PROCESSING APPARATUS - A processing apparatus | 12-18-2014 |
| 20140372738 | PROVIDING A TRUSTWORTHY INDICATION OF THE CURRENT STATE OF A MULTI-PROCESSOR DATA PROCESSING APPARATUS - A data processing apparatus formed on an integrated circuit comprising: a plurality of processors; power control circuitry configured to control power up and power down of the processors; a read only memory for storing boot up software for booting up each of the processors. The power control circuitry is configured to respond to receipt of a check state request, to control one of the processors that is currently powered down to power up and to access the boot up software. The boot up software accessed in response to the check state request controls the processor to perform a measurement indicative of a current state of the data processing apparatus and to output a value indicative of the measurement. | 12-18-2014 |
| 20140372646 | RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION - A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices. | 12-18-2014 |
| 20140368521 | GRAPHICS PROCESSING SYSTEMS - A tile-based graphics processing pipeline comprising a rasteriser | 12-18-2014 |
| 20140365751 | OPERAND GENERATION IN AT LEAST ONE PROCESSING PIPELINE - A data processing apparatus has at least one processing pipeline having first, second and third pipeline stages. The first pipeline stage detects whether a stream of instructions to be processed includes a predetermined instruction sequence comprising first and second instructions for performing first and second operand generation operations, where the second operand generation operation is dependent on an outcome of the first. In response to detecting this instruction sequence, the first pipeline stage generates a modified stream of instructions in which at least the second instruction is replaced with a third instruction for performing a combined operand generation operation having the same effect as the first and second operand generation operations. As the third instruction can be scheduled independently of the first instruction, processing performance of the pipeline can be improved. | 12-11-2014 |
| 20140351472 | METHOD AND APPARATUS FOR INTERRUPT HANDLING - A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level. | 11-27-2014 |
| 20140351359 | DATA PROCESSING APPARATUS AND METHOD FOR COMMUNICATING BETWEEN A MASTER DEVICE AND AN ASYCHRONOUS SLAVE DEVICE VIA AN INTERFACE - A data processing apparatus and method provide communication between a master device operating from a master clock signal and a slave device operating from a slave clock signal asynchronous to the master clock signal. An interface transfers packets between the master device and the slave device. A slave clock replica generator associated with the master device generates a slave clock replica that controls timing of transmission of packets by the master device over the interface. A sync request transfer is issued over the interface and has a property identifiable by the slave device irrespective of whether the sync request transfer is synchronised with the slave clock signal. In response, the slave device issues a sync response transfer indicative of at least a frequency of the slave clock signal, and the slave clock replica generator determines at least the frequency of the slave clock replica from that sync transfer. | 11-27-2014 |
| 20140340122 | CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON - An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage. | 11-20-2014 |
| 20140337396 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A TRANSFORM BETWEEN SPATIAL AND FREQUENCY DOMAINS WHEN PROCESSING VIDEO DATA - A data processing apparatus and method are provided for performing a transform between spatial and frequency domains when processing video data. The data processing apparatus comprises transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values representing the transform of the N input values between the spatial and frequency domains. In doing this, the transform circuitry employs a base circuitry that is configured to receive M internal input values generated by the transform circuitry, where M is greater than or equal to 4, and to perform a base operation equivalent to matrix multiplication of the M internal input values by a Hankel matrix, which is a square matrix with constant skew diagonals, where each element of the array identifies a coefficient, performance of the base operation generating M internal output values for returning to the transform circuitry. The transform circuitry is arranged during performance of the sequence of operations to generate from the N input values multiple sets of the M internal input values, to provide each set of M internal input values to the base circuitry in order to cause multiple sets of the M internal output values to be produced, and to derive the N output values from the multiple sets of M internal output values. It has been found that such an approach is scalable to accommodate varying sizes of N, results in a significant reduction in the number of multiplications required in order to perform the transform between the spatial and frequency domains of the N input values, and produces a bit exact result. | 11-13-2014 |
| 20140331028 | IDENTIFICATION OF MISSING CALL AND RETURN INSTRUCTIONS FOR MANAGEMENT OF A RETURN ADDRESS STACK - A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack. | 11-06-2014 |
| 20140327688 | GRAPHICS PROCESSING SYSTEMS - A tile-based graphics processing pipeline comprising a rasteriser | 11-06-2014 |
| 20140327671 | GRAPHICS PROCESSING SYSTEMS - A tile-based graphics processing pipeline | 11-06-2014 |
| 20140317390 | RETURN ADDRESS PREDICTION - A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed. | 10-23-2014 |
| 20140317384 | DATA PROCESSING APPARATUS AND METHOD FOR PRE-DECODING INSTRUCTIONS TO BE EXECUTED BY PROCESSING CIRCUITRY - A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line. Each data cache line stores at least one data value and the associated information. Pre-decode circuitry is associated with the unified cache and performs a first pre-decode operation on a received instruction for that instruction cache line in order to generate a corresponding partially pre-decoded instruction for storing in the instruction cache line. Further pre-decode circuitry is associated with the further cache, and, when a partially pre-decoded instruction is routed to the further cache, performs a further pre-decode operation on the partially pre-decoded instruction to generate a corresponding pre-decoded instruction for storage in the further cache. | 10-23-2014 |
| 20140312956 | POST FABRICATION TUNING OF AN INTEGRATED CIRCUIT - An integrated circuit | 10-23-2014 |
| 20140307514 | MEMORY CONTROLLER USING A DATA STROBE SIGNAL AND METHOD OF CALIBRATING DATA STROBE SIGNAL IN A MEMORY CONTROLLER - A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process comprises a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive. | 10-16-2014 |
| 20140293718 | MEMORY CONTROLLER AND METHOD OF CALIBRATING A MEMORY CONTROLLER - A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value. | 10-02-2014 |
| 20140286096 | MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH A MEMORY DEVICE - A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level. | 09-25-2014 |
| 20140283117 | PROTECTION UNIT AND METHOD FOR CONTROLLING ACCESS BY PLURAL PROCESSES TO A STORAGE UNIT - A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased. | 09-18-2014 |
| 20140281180 | DATA COHERENCY MANAGEMENT - A data processing system | 09-18-2014 |
| 20140267283 | METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA - To encode a texture to be used in a graphics processing system, the texture is first downscaled to generate a lower resolution representation of the texture | 09-18-2014 |
| 20140267256 | HIDDEN SURFACE REMOVAL IN GRAPHICS PROCESSING SYSTEMS - In a graphics processing pipeline | 09-18-2014 |
| 20140258622 | PREFETCHING OF DATA AND INSTRUCTIONS IN A DATA PROCESSING APPARATUS - A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests. | 09-11-2014 |
| 20140250278 | INTEGRATED LEVEL SHIFTING LATCH CIRCUIT AND METHOD OF OPERATION OF SUCH A LATCH CIRCUIT - An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry. | 09-04-2014 |
| 20140237300 | DATA PROCESSING APPARATUS AND TRACE UNIT - A data processing apparatus has processing circuitry for executing program instructions and trace circuitry for generating trace data indicating processing activities of the processing circuitry. The trace circuitry may detect a lockup state of the processing circuitry in which the processing circuitry does not make forward progress of execution of the program instructions. In response to detecting the lockup state, the trace circuitry may include in the trace data a lockup identifier indicating that the lockup state has occurred. | 08-21-2014 |
| 20140237281 | DATA PROCESSING SYSTEM - A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units. | 08-21-2014 |
| 20140223229 | DATA PROCESSING APPARATUS AND METHOD FOR ANALYSING TRANSIENT FAULTS OCCURRING WITHIN STORAGE ELEMENTS OF THE DATA PROCESSING APPARATUS - A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus. | 08-07-2014 |
| 20140218089 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 08-07-2014 |
| 20140215189 | DATA PROCESSING APPARATUS AND METHOD FOR CONTROLLING USE OF AN ISSUE QUEUE - An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks. | 07-31-2014 |
| 20140210840 | METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA - When encoding an array of texture data elements to be used in a graphics processing system, the array of texture data elements is divided into a plurality of non-rectangular sub-sets of texture data elements, and each non-rectangular sub-set of texture data elements that the texture has been divided into is then encoded to generate an encoded texture data block representing that non-rectangular sub-set of the texture data elements, to thereby provide a set of encoded texture data blocks representing the texture. | 07-31-2014 |
| 20140201447 | DATA PROCESSING APPARATUS AND METHOD FOR HANDLING PERFORMANCE OF A CACHE MAINTENANCE OPERATION - A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation. | 07-17-2014 |
| 20140195787 | TRACKING SPECULATIVE EXECUTION OF INSTRUCTIONS FOR A REGISTER RENAMING DATA STORE - First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations. | 07-10-2014 |
| 20140195786 | TRACING SPECULATIVELY EXECUTED INSTRUCTIONS - A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry. | 07-10-2014 |
| 20140193081 | METHODS OF AND APPARATUS FOR ENCODING AND DECODING DATA - When encoding a set of texture data elements | 07-10-2014 |
| 20140181581 | ERROR RECOVERY WITHIN INTEGRATED CIRCUIT - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 06-26-2014 |
| 20140181568 | INTERFACE FOR CONTROLLING THE PHASE ALIGNMENT OF CLOCK SIGNALS FOR A RECIPIENT DEVICE - Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration. | 06-26-2014 |
| 20140181485 | STICKY BIT UPDATE WITHIN A SPECULATIVE EXECUTION PROCESSING ENVIRONMENT - A data processing apparatus | 06-26-2014 |
| 20140181478 | DYNAMIC WRITE PORT RE-ARBITRATION - Within a processing pipeline | 06-26-2014 |
| 20140181416 | RESOURCE MANAGEMENT WITHIN A LOAD STORE UNIT - A load store pipeline | 06-26-2014 |
| 20140177377 | DATA SIGNAL RECEIVER AND METHOD OF CALIBRATING A DATA SIGNAL RECEIVER - A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal. The method comprises the steps of: receiving, on each bit of the multi-bit data signal, a sample of a predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative start timing value indicative of a start of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative end timing value indicative of an end of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a mid-point timing value halfway between the relative start timing value and the relative end timing value; applying a bit timing delay to each bit of the multi-bit data signal such that the mid-point timing values are aligned; and applying a strobe timing delay to the associated data strobe signal to align the associated data strobe signal with the aligned mid-point timing values. | 06-26-2014 |
| 20140177359 | METHOD AND APPARATUS FOR ALIGNING A CLOCK SIGNAL AND A DATA STROBE SIGNAL IN A MEMORY SYSTEM - A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided. The method comprising the steps of: putting the memory into a write levelling mode; incrementing an alignment delay applied to the data strobe signal until a transition point occurs at which a response of the memory to issuance of the data strobe signal transitions to an inverse state; performing an oversampling of the response of the memory over a selected interval following said transition point; repeating the steps of incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of the oversampling is in the inverse state; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of the clock signal, the identified clock cycle responsible for the transition point; and applying the selected alignment delay to the data strobe signal and applying a clock cycle selection to a data path in the system to match the identified clock cycle. | 06-26-2014 |
| 20140176584 | REDUCING ENERGY AND INCREASING SPEED BY AN INSTRUCTION SUBSTITUTING SUBSEQUENT INSTRUCTIONS WITH SPECIFIC FUNCTION INSTRUCTION - A data processing system is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst | 06-26-2014 |
| 20140173214 | Retention priority based cache replacement policy - A data processing system includes a cache memory | 06-19-2014 |
| 20140156930 | CACHING OF VIRTUAL TO PHYSICAL ADDRESS TRANSLATIONS - A data processing apparatus comprising: at least one initiator device for issuing transactions, a hierarchical memory system comprising a plurality of caches and a memory and memory access control circuitry. The initiator device identifies storage locations using virtual addresses and the memory system stores data using physical addresses, the memory access control circuitry is configured to control virtual address to physical address translations. The plurality of caches, comprise a first cache and a second cache. The first cache is configured to store a plurality of address translations of virtual to physical addresses that the initiator device has requested. The second cache is configured to store a plurality of address translations of virtual to physical addresses that it is predicted that the initiator device will subsequently request. The first and second cache are arranged in parallel with each other such that the first and second caches can be accessed during a same access cycle. | 06-05-2014 |
| 20140152684 | METHODS OF AND APPARATUS FOR USING TEXTURES IN GRAPHICS PROCESSING SYSTEMS - A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch. | 06-05-2014 |
| 20140152683 | METHODS OF AND APPARATUS FOR USING TEXTURES IN GRAPHICS PROCESSING SYSTEMS - A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail ( | 06-05-2014 |
| 20140149653 | VARIABLE MAPPING OF MEMORY ACCESSES TO REGIONS WITHIN A MEMORY - An apparatus for processing data | 05-29-2014 |
| 20140143633 | APPARATUS AND METHOD FOR CORRECTING ERRORS IN DATA ACCESSED FROM A MEMORY DEVICE - An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected. | 05-22-2014 |
| 20140143522 | PREFETCHING BASED UPON RETURN ADDRESSES - An apparatus for processing data includes signature generation circuitry | 05-22-2014 |
| 20140143291 | STORAGE CIRCUIT WITH RANDOM NUMBER GENERATION MODE - A storage circuit | 05-22-2014 |
| 20140139534 | METHOD OF AND APPARATUS FOR PROCESSING GRAPHICS - A primitive listing and sorting arrangement for a tile-based graphics rendering system in which primitive lists can be prepared for at least two different sets of sub-regions of the render target area. Two or more alternative solutions for listing the primitive for rendering using the sub-regions of at least two of the at least two different sets of sub-regions of the render target area that primitive lists can be prepared for are determined (S | 05-22-2014 |
| 20140139277 | CALIBRATION OF DELAY CHAINS - A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator. | 05-22-2014 |
| 20140125392 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 05-08-2014 |
| 20140122849 | APPARATUS AND METHOD FOR HANDLING EXCEPTION EVENTS - Processing circuitry | 05-01-2014 |
| 20140122846 | BRANCH TARGET ADDRESS CACHE USING HASHED FETCH ADDRESSES - An integrated circuit | 05-01-2014 |
| 20140122760 | COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS - A global interrupt number space | 05-01-2014 |
| 20140115554 | METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE - A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler. | 04-24-2014 |
| 20140115377 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 04-24-2014 |
| 20140115376 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 04-24-2014 |
| 20140108691 | HANDLING INTERRUPTS IN A MULTI-PROCESSOR SYSTEM - A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request. | 04-17-2014 |
| 20140101491 | TRACING OF A DATA PROCESSING APPARATUS - A trace unit, diagnostic apparatus and data processing apparatus are provided for tracing of conditional instructions. The data processing apparatus generates instruction observed indicators indicating execution of conditional instructions and result output indicators indicating output by the data processing apparatus of results of executing respective conditional instructions. The instruction observed indicators and result output indicators are received by a trace unit that is configured to output conditional instruction trace data items and independently output conditional result trace data items enabling separate trace analysis of conditional instructions and corresponding conditional results by a diagnostic apparatus. The instruction observed indicator is received at the trace unit in a first processing cycle of the data processing apparatus whilst result output indicator is received at in a second different processing cycle. | 04-10-2014 |
| 20140082239 | ARBITRATION CIRCUITRY AND METHOD - Arbitration circuitry | 03-20-2014 |
| 20140082215 | ARBITRATING BETWEEN DATA PATHS IN A BUFFERLESS FREE FLOWING INTERCONNECT - An interconnect comprising paths configured to transmit data packets between nodes on a network. The nodes comprise ports for inputting and outputting the data packets to the interconnect. At least two of the paths each have at least a portion configured such that a data packet addressed for output at one of the nodes on one of the paths and not being accepted at the node will continue along the path and on travelling further will return to the node. The at least two paths are balanced paths such that a data packet not accepted at the one of the nodes will return to the node a same predetermined number of clock cycles later whichever of the balanced paths the data packet is traveling along. The one of the nodes comprises an arbiter that is configured to prioritise one of the balanced data paths for output, the arbiter being configured to ensure that a priority changes after the predetermined number of clock cycles, such that a data packet on any of the balanced paths not being accepted for output at the node on a first attempt is guaranteed to have priority on a subsequent return to the node. | 03-20-2014 |
| 20140082121 | MODELLING DEPENDENCIES IN DATA TRAFFIC - A method of modifying timings of data traffic in a test system by introducing dependencies that would arise in response to data requiring access to a resource. The resource receives the data traffic from at least one initiator and is connected via an interconnect to at least one recipient, the resource comprises a buffer for storing pending data related to an access to the resource that cannot currently complete. The method comprises the steps of:
| 03-20-2014 |
| 20140079074 | SELECTING BETWEEN CONTENDING DATA PACKETS TO LIMIT LATENCY DIFFERENCES BETWEEN SOURCES - An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected. | 03-20-2014 |
| 20140075581 | SECURE MECHANISM TO SWITCH BETWEEN DIFFERENT DOMAINS OF OPERATION IN A DATA PROCESSOR - A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction. | 03-13-2014 |
| 20140068371 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 03-06-2014 |
| 20140052933 | WRITE TRANSACTION MANAGEMENT WITHIN A MEMORY INTERCONNECT - A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialisation circuitry stalls any transaction requests to the write line of data until the first write transaction. | 02-20-2014 |
| 20140052921 | STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION - A data processing system includes a plurality of transaction masters ( | 02-20-2014 |
| 20140047148 | DATA PROCESSING APPARATUS AND A METHOD FOR SETTING PRIORITY LEVELS FOR TRANSACTIONS - A data processing apparatus and method for setting priority levels for transactions has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry applies an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource. Adaptive priority circuitry is associated with at least one of the sources and monitors throughput indication data for previously issued transactions from the associated source. For each new transaction from the associated source, the circuitry sets the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. The adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels. | 02-13-2014 |
| 20140043071 | SELF-INITIALIZING ON-CHIP DATA PROCESSING APPARATUS AND METHOD OF SELF-INITIALIZING AN ON-CHIP DATA PROCESSING APPARATUS - An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency. | 02-13-2014 |
| 20140040529 | TRANSLATION TABLE CONTROL - Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables | 02-06-2014 |
| 20140040516 | BARRIER TRANSACTIONS IN INTERCONNECTS - Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained. | 02-06-2014 |
| 20140040334 | DATA PROCESSING APPARATUS AND METHOD FOR REDUCING THE SIZE OF A LOOKUP TABLE - A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2 | 02-06-2014 |
| 20140035661 | AN INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING LOAD ON THE OUTPUT FROM ON-CHIP VOLTAGE GENERATION CIRCUITRY - An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled. | 02-06-2014 |
| 20140032808 | INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT - A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state. | 01-30-2014 |
| 20140025902 | HANDLING COLLISIONS BETWEEN ACCESSES IN MULTIPORT MEMORIES - A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port. | 01-23-2014 |
| 20140022835 | CONTROLLING THE VOLTAGE LEVEL ON THE WORD LINE TO MAINTAIN PERFORMANCE AND REDUCE ACCESS DISTURBS - A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line to a voltage source; and feedback circuitry configured to feedback a change in voltage on the access control line to the access switching circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line in response to the feedback circuitry providing a feedback signal indicating that the access control line voltage has attained a predetermined value. | 01-23-2014 |
| 20140022264 | GRAPHICS PROCESSING UNIT AND METHOD FOR PERFORMING TESSELLATION OPERATIONS - A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex. | 01-23-2014 |
| 20140021999 | LEVEL SHIFTING CIRCUITRY - Level shifting circuitry is provided for generating an output signal in response to an input signal. The level shifting circuitry includes a pulldown path for pulling the output signal to a lower output voltage level in response to a first transition of the input signal and a pullup path for pulling the output signal to a higher output voltage level in response to a second transition of the input signal. Pullup control circuitry places the pullup path in a non-conductive state in response to the output signal being pulled to the higher output voltage level. A keeper path keeps the output signal at the higher output voltage level while the pullup path is non-conductive until the pulldown path pulls the output signal low. A maximum drive current of the pulldown path is greater than a maximum drive current of the keeper path. | 01-23-2014 |
| 20140019734 | DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 01-16-2014 |
| 20140016419 | MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE - A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted. | 01-16-2014 |
| 20140015562 | PERFORMANCE CHARACTERISTIC MONITORING CIRCUIT AND METHOD - A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay. | 01-16-2014 |
| 20140013178 | ERROR RECOVERY WITHIN INTEGRATED CIRCUIT - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 01-09-2014 |
| 20140013020 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus has performance monitoring circuitry for generating performance monitoring data. The performance monitoring circuitry includes a first event counter for counting occurrences of a first event and a second event counter for counting occurrences of a second event. A performance monitoring interrupt signal is indicated if, when the number of first events counted by the first event counter reaches a first threshold value, the number of second events by the second event counter meets an interrupt triggering condition. | 01-09-2014 |
| 20140002156 | DUTY CYCLE CORRECTION WITHIN AN INTEGRATED CIRCUIT | 01-02-2014 |
| 20130346698 | DATA PROCESSING APPARATUS AND METHOD FOR REDUCING STORAGE REQUIREMENTS FOR TEMPORARY STORAGE OF DATA - A data processing apparatus and method, the apparatus including processing circuitry for executing a sequence of instructions, each instruction having an associated memory address and the sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region. Instruction cache control circuitry is arranged to store within a selected cache line of a data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage. Control state circuitry maintains a record of the chosen cache line in which said data of a predetermined data type has been written, so that upon receipt of a request for that data it can then be provided from the instruction cache. | 12-26-2013 |
| 20130339686 | PROCESSING APPARATUS, TRACE UNIT AND DIAGNOSTIC APPARATUS - A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit | 12-19-2013 |
| 20130339412 | DATA PROCESSING APPARATUS AND METHOD - Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle. | 12-19-2013 |
| 20130335128 | SEQUENTIAL LATCHING DEVICE WITH ELEMENTS TO INCREASE HOLD TIMES ON THE DIAGNOSTIC DATA PATH - A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode. | 12-19-2013 |
| 20130328533 | LEAKAGE CURRENT REDUCTION IN AN INTEGRATED CIRCUIT - An integrated circuit is provided with operational mode header transistors which connect a virtual power rail to a VDD power supply. A controller circuit, responsive to a sensed voltage signal from a voltage sensor which reads the virtual rail voltage VVDD, generates a control signal which controls the operational mode transistors. The control signal is derived from an interface voltage power supply that provides higher voltage VDD IO than the VDD power supply and thus able to overdrive the operational mode transistors via either a gate bias voltage or a bulk bias voltage. The amount of leakage through the operational mode transistors is controlled in a closed loop feedback arrangement so as to maintain a predetermined target value or range for the virtual rail voltage. The operational mode transistor may also be controlled to support dynamic voltage and frequency scaling. | 12-12-2013 |
| 20130318270 | ARBITRATION CIRCUITY AND METHOD FOR ARBITRATING BETWEEN A PLURALITY OF REQUESTS FOR ACCESS TO A SHARED RESOURCE - Arbitration circuitry for arbitrating between a plurality W of requests R for access to a shared resource. Included are state bits storage storing I state bits Q and generating 2I output bits comprising the true and compliment values of each stored state bit and routing circuitry for generating a set of mask signals M from the output bits. Grant circuitry receives the set of mask signals and the plurality of requests, and grants access to the shared resource to an asserted request having regard to the priority ordering encoded by the set of mask signals. State bit update circuitry is responsive to a trigger condition to perform an update causing a change in the priority ordering encoded by the set of mask signals. The routing circuitry provides a pattern of connections such that each mask signal in the set is directly connected to one of said output bits. | 11-28-2013 |
| 20130314429 | ADAPTIVE FRAME BUFFER COMPRESSION - Image data is subject to compression and decompression when it is respectively written to and read from a frame buffer. If a portion of the image data is identified as static (subject to less than a threshold amount of change for greater than a threshold time), then compression control parameters used for compression of that portion of the image are adjusted so as to increase the compression ratio achieved, hold the degree of lossiness substantially constant and increase the energy consumed while compressing that portion. The increased energy consumption during this high compression ratio compression is likely compensated for by a reduction in energy subsequently consumed when writing that frame-buffer image data to the frame buffer and reading that frame-buffer image data multiple times from the frame buffer. The compression characteristics varied may be to increase the block size used in the compression. Other variations in compression applied may be to change from single-pass compression to multi-pass compression, switch compression on and off altogether, or reorder the data when it has been compressed so as to match the order it will be read and so achieve support for longer read burst. | 11-28-2013 |
| 20130311725 | DATA PROCESSING APPARATUS AND METHOD FOR TRANSFERRING WORKLOAD BETWEEN SOURCE AND DESTINATION PROCESSING CIRCUITRY - In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry. | 11-21-2013 |
| 20130308407 | CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DISTURBS IN SEMICONDUCTOR MEMORIES - A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level. | 11-21-2013 |
| 20130305255 | CONTROLLING PRIORITY LEVELS OF PENDING THREADS AWAITING PROCESSING - A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline. | 11-14-2013 |
| 20130304991 | DATA PROCESSING APPARATUS HAVING CACHE AND TRANSLATION LOOKASIDE BUFFER - A data processing apparatus has a cache and a translation look aside buffer (TLB). A way table is provided for identifying which of a plurality of cache ways stores require data. Each way table entry corresponds to one of the TLB entries of the TLB and identifies, for each memory location of the page associated with the corresponding TLB entry, which cache way stores the data associated with that memory location. Also, the cache may be capable of servicing M access requests in the same processing cycle. An arbiter may select pending access requests for servicing by the cache in a way that ensures that the selected pending access requests specify a maximum of N different virtual page addresses, where N| 11-14-2013 | |
| 20130304785 | APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION - A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value. | 11-14-2013 |
| 20130290635 | PROVISION OF ACCESS CONTROL DATA WITHIN A DATA PROCESSING SYSTEM - A data processing system ( | 10-31-2013 |
| 20130283115 | DATA PROCESSING APPARATUS USING IMPLICIT DATA STORAGE AND A METHOD OF IMPLICIT DATA STORAGE - A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code. | 10-24-2013 |
| 20130276096 | MANAGEMENT OF DATA PROCESSING SECURITY IN A SECONDARY PROCESSOR - A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain. | 10-17-2013 |
| 20130275701 | MANAGEMENT OF DATA PROCESSING SECURITY IN A SECONDARY PROCESSOR - A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor. | 10-17-2013 |
| 20130268930 | PERFORMANCE ISOLATION WITHIN DATA PROCESSING SYSTEMS SUPPORTING DISTRIBUTED MAINTENANCE OPERATIONS - A data processing system | 10-10-2013 |
| 20130268705 | APPARATUS AND METHOD FOR PROVIDING A BIDIRECTIONAL COMMUNICATIONS LINK BETWEEN A MASTER DEVICE AND A SLAVE DEVICE - A bidirectional communications link between a master device and a slave device includes first endpoint circuitry coupled to the master device generating forward data packets, second endpoint circuitry coupled to the slave device for receiving reverse data packets, and bidirectional communication circuitry for transferring forward data packets from the first endpoint circuitry to the second endpoint circuitry and reverse data packets from the second endpoint circuitry to the first endpoint circuitry. In response to a power down condition requiring a power down of at least one of the first endpoint circuitry and the second endpoint circuitry, performance of said power down is deferred until both said outstanding forward credit signal and said outstanding reverse credit signal have been de-asserted. | 10-10-2013 |
| 20130258760 | HANDLING OF WRITE OPERATIONS WITHIN A MEMORY DEVICE - A memory device includes an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array. The memory cells in each row are activated via a word line signal on the corresponding word line, and the memory cells in each column are coupled to an associated bit line pair via which data is written into an activated memory cell of the column during a write operation and data is read from the activated memory cell of the column during a read operation. A dummy column of dummy memory cells is provided and includes a plurality of loading dummy memory cells for providing a load to the at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line. | 10-03-2013 |
| 20130256908 | INTER-DIE CONNECTION WITHIN AN INTEGRATED CIRCUIT FORMED OF A STACK OF CIRCUIT DIES - An integrated circuit is formed of a plurality of circuit dies | 10-03-2013 |
| 20130251006 | DATA PACKET FLOW CONTROL ACROSS AN ASYNCHRONOUS CLOCK DOMAIN BOUNDARY - A system-on-chip integrated circuit | 09-26-2013 |
| 20130247060 | APPARATUS AND METHOD FOR PROCESSING THREADS REQUIRING RESOURCES - A data processing apparatus has processing circuitry for processing threads using resources accessible to the processing circuitry. Thread handling circuitry handles pending threads which are waiting for resources required for processing. When a request is made for a resource which is not available, a lock is set to ensure that once the resource becomes available, the resource remains available until the lock is removed. This prevents other threads reallocating the resource. When a subsequent pending thread requests access to the same locked unavailable resource, the lock is transferred to that subsequent thread so that the latest thread accessing that resource is considered the lock owning thread. The lock is removed once the lock owning thread is ready for processing. | 09-19-2013 |
| 20130246984 | PROPRIETARY CIRCUIT LAYOUT IDENTIFICATION - A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found. | 09-19-2013 |
| 20130246496 | FLOATING-POINT VECTOR NORMALISATION - When performing vector normalisation upon floating point values, an approximate reciprocal value generating instruction is used to generate an approximate reciprocal value with a mantissa of one and an exponent given by a bitwise inversion of the exponent field of the input floating point number. A modified number of multiplication instruction is used which performs a multiplication giving the standard IEEE 754 results other than when a signed zero is multiplied by a signed infinity which results a signed predetermined substitute value, such as 2. The normalisation operation may be performed by calculating a scaling value in dependence upon the vector floating point value using the approximate reciprocal value generating instruction. Each of the input components may then be scaled using the modify multiplication instruction to generate a scaled vector floating point value formed of a plurality of scaled components. The magnitude of the scaled vector floating point value can then be calculated and each of the individual scaled components divided by this magnitude to generate a normalised vector floating point value. The scaling value may be set to 2, where C is an integer value selected such that the sum of the squares of the plurality of scale components is less than a predetermined limit value. | 09-19-2013 |
| 20130227330 | ANALYSING TIMING PATHS FOR CIRCUITS FORMED OF STANDARD CELLS - A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterisation data for the cell. The correcting steps includes providing further characterisation data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times. | 08-29-2013 |
| 20130227186 | TRANSACTION ROUTING DEVICE AND METHOD FOR ROUTING TRANSACTIONS IN AN INTEGRATED CIRCUIT - A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit. | 08-29-2013 |
| 20130219149 | OPERAND SPECIAL CASE HANDLING FOR MULTI-LANE PROCESSING - A single instruction multiple data processing pipeline | 08-22-2013 |
| 20130219004 | COMMUNICATION USING INTEGRATED CIRCUIT INTERCONNECT CIRCUITRY - An integrated circuit comprising multiple master units ( | 08-22-2013 |
| 20130212700 | EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN - A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data. | 08-15-2013 |
| 20130205413 | DATA PROCESSING APPARATUS AND METHOD USING SECURE DOMAIN AND LESS SECURE DOMAIN - A data processing apparatus | 08-08-2013 |
| 20130205403 | MAINTAINING SECURE DATA ISOLATED FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN DOMAINS - A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level. | 08-08-2013 |
| 20130205389 | DATA PROCESSING APPARATUS AND METHOD FOR PROTECTING SECURE DATA AND PROGRAM CODE FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN SECURE AND LESS SECURE DOMAINS - A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call. | 08-08-2013 |
| 20130205125 | EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN - Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving. | 08-08-2013 |
| 20130205080 | APPARATUS AND METHOD FOR CONTROLLING REFRESHING OF DATA IN A DRAM - An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle. | 08-08-2013 |
| 20130202008 | MONITORING CIRCUIT AND METHOD - A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature. | 08-08-2013 |
| 20130182484 | WORD LINE AND POWER CONDUCTOR WITHIN A METAL LAYER OF A MEMORY CELL - A memory cell | 07-18-2013 |
| 20130169350 | SENSING SUPPLY VOLTAGE SWINGS WITHIN AN INTEGRATED CIRCUIT - An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range. | 07-04-2013 |
| 20130166980 | ERROR RECOVERY IN A DATA PROCESSING APPARATUS - A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry. | 06-27-2013 |
| 20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 06-27-2013 |
| 20130166516 | APPARATUS AND METHOD FOR COMPARING A FIRST VECTOR OF DATA ELEMENTS AND A SECOND VECTOR OF DATA ELEMENTS - A data processing apparatus includes a comparison unit configured to perform an element comparison process performing a comparison of a first data element at a first index in the first vector with a second data element at a second index in the second vector. A hazard vector generation unit is configured to populate a hazard vector at an index determined by the first index with a value determined by the second index. The comparison unit performs the element comparison process by iteratively comparing data elements of the first vector with each element of a subset of the second vector. It then determines the subset of the second vector as those data elements at indices in the second vector which are less than a current index of the first vector and which are greater than previously determined values of the second index for which the match condition was true. | 06-27-2013 |
| 20130159776 | DATA PROCESSING APPARATUS AND METHOD FOR IDENTIFYING DEBUG EVENTS - A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state whilst the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state whilst the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state. | 06-20-2013 |
| 20130159747 | DATA PROCESSING APPARATUS AND METHOD FOR MAINTAINING A TIME COUNT VALUE - A counting circuit for a data processing apparatus has a normal mode in which a main counter increments the time count value in response to edges of a main clock signal, and a power saving mode in which the main clock signal is disabled and a further clock counter counts elapsed edges of a further clock signal having a lower frequency than the main clock signal. On switching to power saving mode, a reference time count value of the main counter is captured at a timing triggered by an edge of the further clock signal. On switching back to normal mode, an expected time count value from the main counter is calculated based on the captured reference value and the counted number of elapsed edges during the power saving mode, and the main counter is restarted at a timing triggered by another edge of the further clock signal. | 06-20-2013 |
| 20130155797 | USING A PRECHARGE CHARACTERISTICS OF A NODE TO VALIDATE A PREVIOUS DATA/SIGNAL VALUE REPRESENTED BY A DISCHARGE OF SAID NODE - An integrated circuit precharges a node | 06-20-2013 |
| 20130155103 | INTERMEDIATE VALUE STORAGE WITHIN A GRAPHICS PROCESSING APPARATUS - A tile-based graphics processor includes tile processing circuitry that has both a tile buffer and a per-pixel general purpose data store. The per-pixel general purpose data store is read accessible and write accessible by the tile processing circuitry to store intermediate values. These intermediate values are generated by the tile processing circuitry and then consumed by the tile processing circuitry to generate the output values for the tile being processed. | 06-20-2013 |
| 20130151891 | LIMITING CERTAIN PROCESSING ACTIVITIES AS ERROR RATE PROBABILITY RISES - A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behaviour of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry. | 06-13-2013 |
| 20130151819 | RECOVERING FROM EXCEPTIONS AND TIMING ERRORS - A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit. | 06-13-2013 |
| 20130151576 | APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE - Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value, and masking circuitry for applying the mask to the sum value to generate the integral floating-point value. | 06-13-2013 |
| 20130148443 | MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE - A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted. | 06-13-2013 |
| 20130145129 | REGISTER RENAMING DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING REGISTER RENAMING - A data processing apparatus and method are provided. A processor performs data processing operations in response to data processing instructions which reference logical registers. A set of physical registers stores data values which are subjected to the data processing operations. A tag storage stores for each physical register a tag value indicative of one of the logical registers. The processor references the tag storage to perform the data processing operations. A tag value exchanger performs a tag switch exchanging two tag values in the tag storage when the processor executes a predetermined instruction which references two logical registers and for which a choice of which two physical registers are mapped to which of the two logical registers will have no effect on an outcome of the data processing operations. The tag value exchanger performs the tag switch with respect to the tag values indicative of the two logical registers. | 06-06-2013 |
| 20130145127 | ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS - A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption. | 06-06-2013 |
| 20130145126 | REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS - A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file | 06-06-2013 |
| 20130141445 | METHODS OF AND APPARATUS FOR PROCESSING COMPUTER GRAPHICS - When carrying out a second, higher level of anti-aliasing such as 8× MSAA, in a graphics processing pipeline | 06-06-2013 |
| 20130132737 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 05-23-2013 |
| 20130124820 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING MEMORY TRANSACTIONS WITHIN SUCH A DATA PROCESSING APPARATUS - A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing. | 05-16-2013 |
| 20130124767 | INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT - A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state. | 05-16-2013 |
