| ANALOG DEVICES, INC. Patent applications |
| Patent application number | Title | Published |
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| 20160142049 | POWER SUPPLY CIRCUITS FOR GATE DRIVERS - An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state. The isolated power supply circuit can include a control circuit to regulate the power provided to maintain or increase the supply voltage while the gate driver circuit drives the transistor in an on state. The power supply circuit can also include the cyclic charging power supply circuit to receive a second voltage in the second isolated system and provide the supply voltage to the gate driver circuit. The cyclic charging power supply circuit can include one or more of a bootstrap power supply circuit or a charge pump power supply circuit. | 05-19-2016 |
| 20160126724 | SIGNAL ISOLATOR SYSTEM WITH PROTECTION FOR COMMON MODE TRANSIENTS - An isolator system has an isolator that generates differential isolator signals and a receiver that generates digital data representative of signals received from the isolator. The system also may include an RC filter coupled between the isolator and the receiver. During operation, the filter may distribute transient signals across various circuit paths in the isolator, only some of which are coupled to the receiver inputs. Over time, the filter may attenuate transient contributions at the receiver inputs. In this manner, the filter may limit effects of these common mode transients. | 05-05-2016 |
| 20160116576 | ACTIVE COMPENSATION FOR PHASE ALIGNMENT ERRORS IN TIME-OF-FLIGHT CAMERAS - Methods, apparatuses, and systems can be provided to implement active feedback to electrically sense or monitor the illumination and shutter pulses and adjust them actively to maintain the desired phase relationship/difference between the pulses. By maintaining the desired phase difference, the distance calculation can be made more accurate, even when conditions of the time-of-flight camera varies (e.g., temperature, aging, etc.). Advantageously, active compensation can correct for errors ‘on-the-fly’, eliminating detailed characterization and manual adjustment during operation. | 04-28-2016 |
| 20160099821 | POWER LINE CARRIER/COMMUNICATIONS WITH IMPROVED IMMUNITY FOR TRANSIENTS AND ELECTROMAGNETIC INTERFERENCES - Power line carriers (PLCs) are susceptible to transients and electromagnetic interference (EMI) on the power line. To address transients and EMI on the power line, an improved power PLC involves transmitting a signal over the power line using a controlled current source, where the current source is modulated by the signal. The current source output is designed to be independent of the voltage on the power line and the load, and thus, is less susceptible to transients and EMI on the power line. The system architecture of the improved PLC also allows for simple, predictable, and flexible termination. In an example implementation in the automotive industry, the improved high frequency PLC may provide a low cost replacement for existing communication interfaces. The improved PLC may consolidate system in-vehicle communication, reduce in-vehicle wiring, provide system flexibility, and decrease vehicle weight and system cost. | 04-07-2016 |
| 20160099208 | STACKED CONDUCTOR STRUCTURE AND METHODS FOR MANUFACTURE OF SAME - A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers. | 04-07-2016 |
| 20160097846 | Systems and Methods for Ultrasound Beamforming - A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers. | 04-07-2016 |
| 20160094253 | RELAXED DIGITIZATION SYSTEM LINEARIZATION - An approach to linearization relaxes the requirements on the digitization of the analog output signal while maintaining the benefits of a high sampling rate of the output signal. The digitization approach extracts sufficient information to characterize the output signal over a wide bandwidth without necessarily determining sufficient information to fully represent the output signal, for example, without sampling the output signal at the Nyquist sampling rate with a sufficient precision to accurately represent the signal. | 03-31-2016 |
| 20160080182 | DEMODULATION OF ON-OFF-KEY MODULATED SIGNALS IN SIGNAL ISOLATOR SYSTEMS - A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states. | 03-17-2016 |
| 20160079513 | DOPED PIEZOELECTRIC RESONATOR - Mechanical resonators including doped piezoelectric active layers are described. The piezoelectric active layer(s) of the mechanical resonator may be doped with a dopant type and concentration suitable to increase the electromechanical coupling coefficient of the active layer. The increase in electromechanical coupling coefficient may all for improved performance and smaller size mechanical resonators than feasible without using the doping. | 03-17-2016 |
| 20160071526 | ACOUSTIC SOURCE TRACKING AND SELECTION - The present disclosure relates generally to improving acoustic source tracking and selection and, more particularly, to techniques for acoustic source tracking and selection using motion or position information. Embodiments of the present disclosure include systems designed to select and track acoustic sources. In one embodiment, the system may be realized as an integrated circuit including a microphone array, motion sensing circuitry, position sensing circuitry, analog-to-digital converter (ADC) circuitry configured to convert analog audio signals from the microphone array into digital audio signals for further processing, and a digital signal processor (DSP) or other circuitry for processing the digital audio signals based on motion data and other sensor data. Sensor data may be correlated to the analog or digital audio signals to improve source separation or other audio processing. | 03-10-2016 |
| 20160041941 | TWO-WIRE COMMUNICATION SYSTEMS AND APPLICATIONS - Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal. | 02-11-2016 |
| 20160035914 | FILTER COATING DESIGN FOR OPTICAL SENSORS - A silicon-based sensor with an integrated multilayer metal-dielectric filter coating for providing a UV transmission curve of interest is disclosed. The sensor includes a silicon-based photodiode and a filter coating integrated with the silicon-based photodiode and comprising a plurality of filter pairs stacked over the silicon-based photodiode. Each filter pair comprises a dielectric layer and a metal layer. The dielectric layers and the metal layers of the plurality of filter pairs are stacked in an alternating fashion. A thickness of the metal layer in at least one filter pair is different from a thickness of the metal layer in at least one other filter pair. A thickness of the dielectric layer in at least one filter pair is different from a thickness of the dielectric layer in at least one other filter pair. | 02-04-2016 |
| 20160034417 | DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS - Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device. | 02-04-2016 |
| 20160034416 | PERIPHERAL DEVICE DIAGNOSTICS AND CONTROL OVER A TWO-WIRE COMMUNICATION BUS - Disclosed herein are systems and techniques for peripheral device diagnostics and control over a two-wire communication bus. For example, in some embodiments, a slave device may include circuitry to receive a synchronization control frame from an upstream device, receive audio data from the upstream device subsequent to receipt of the synchronization control frame, provide a synchronization response frame toward the upstream device, and provide first data representative of an operational characteristic of an audio device coupled to the slave device subsequent to provision of the synchronization response frame; circuitry to derive timing information from the synchronization control frame; and circuitry to provide the audio data to the audio device, and receive, from a sensor coupled to the slave device, second data representative of the operational characteristic of the audio device. | 02-04-2016 |
| 20160029968 | TRACKING SLOW VARYING FREQUENCY IN A NOISY ENVIRONMENT AND APPLICATIONS IN HEALTHCARE - Heart rate monitors are plagued by noisy sensor data, which makes it difficult for the monitors to output a consistently accurate heart rate reading. To address the issue of noise, some monitors blindly discard sensor data which are too noisy, and stop producing heart rate readings. In some cases, if the monitors do not discard the noisy sensor data, the noisy sensor data can cause irregular heart rate readings. As a result, noisy data can lead to inaccurate heart rate readings or no heart rate readings at all. The present disclosure describes an improved technique for qualifying an input signal, i.e., determining whether a portion of the input signal is likely to result in an accurate heart rate reading, by assessing whether the frequency information of the input signal resembles a heartbeat. The resulting improved heart rate monitor is robust in tracking the heart rate in a noisy environment. | 02-04-2016 |
| 20160028355 | DYNAMIC CURRENT SOURCE FOR AMPLIFIER INTEGRATOR STAGES - An amplifier system may include a current source, an impedance element responsive to a current change, and a feedback controller generating a control signal based on impedance element response. Current source may supply current to a pair of output elements, one of which being controlled by an integrator, and a portion of the integrator. Impedance element may have terminals coupled to inputs of the output elements and may be configured to experience a change in voltage based on a change in current supplied to its input. Feedback controller may have a pair of inputs coupled to the terminals of impedance element and an output to control the current source based on a detected change in voltage across the impedance element. Current source may be varied based on the control signal to maintain a constant current supplied to the input of the impedance elements. | 01-28-2016 |
| 20160026216 | CAPACITIVE SENSORS FOR GRIP SENSING AND FINGER TRACKING - Mobile devices are increasing aware of the environment surrounding the mobile devices. In many applications, it is useful for the mobile device to be able to sense different types of hand grips and/or where fingers are positioned with respect to the mobile device. The present disclosure describes a capacitive sensing apparatus particularly suitable for sensing hand grips and/or finger tracking along edges of a mobile device. The capacitive sensing apparatus comprises strips arranged along two lines, and the respective lengths and spacing are designed to allow optimal response behavior for sensing hand grips and/or tracking fingers. | 01-28-2016 |
| 20160025777 | CIRCUIT ARCHITECTURE FOR MODE SWITCH - Present disclosure relates to a current detection module capable of differentiating and quantifying contribution to a current signal generated by a sensor in response to stimulation by a certain target source from contributions from sources other than the target source (ambient sources). As long as the contribution from the target source comprises a pulsed signal, the module synchronizes itself to the pulse(s) so that there is a predetermined phase relationship between the pulse(s) and functions carried out by various stages of the module. The module may be re-used to also detect and quantify contributions from ambient sources by presenting these contributions to the module as pulses that trigger synchronization of the module. To that end, a detection system disclosed herein is based on the use of such current detection module and allows mode switching where, depending on the selected mode of operation, the module is configured to perform different measurements. | 01-28-2016 |
| 20150381146 | CHARGE SHARING TIME DOMAIN FILTER - An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output. | 12-31-2015 |
| 20150381128 | HYBRID TRANSLINEAR AMPLIFIER - A hybrid, translinear amplifier has at least one gain stage including first and second gain transistors, at least a first load transistor electrically coupled to the first gain transistor and at least a second load transistor electrically coupled to the second gain transistor, and load resistors electrically coupled to the load transistors. A hybrid, translinear amplifier with selectable gain has a first hybrid, translinear amplifier cell having at least first and second load transistors, each load transistor having a load resistor, at least one additional hybrid, translinear amplifier cell having at least third, fourth, fifth and sixth load transistors, each load transistor having a load resistor, at least two switches electrically coupled to the amplifier cells to allow selection of one of the amplifier cells, and a differential output signal having a gain corresponding to a selected amplifier cell. | 12-31-2015 |
| 20150378939 | MEMORY MECHANISM FOR PROVIDING SEMAPHORE FUNCTIONALITY IN MULTI-MASTER PROCESSING ENVIRONMENT - A memory mechanism for providing semaphore functionality in a multi-master processing environment is disclosed. An exemplary memory unit includes a memory controller that manages access to a shared memory. The memory controller includes a semaphore context monitor associated with each master having access to the shared memory. A semaphore context monitor associated with a semaphore-capable master is activated by the semaphore-capable master (for example, by exclusive request signal(s) received by memory controller from semaphore-capable master). A semaphore context monitor associated with a non-semaphore-capable master is activated by the memory controller (for example, by exclusive request signal(s) generated by the memory controller). The memory controller can include a semaphore address command mechanism configured to derive a semaphore command from a memory access request received from the non-semaphore-capable master and activate the semaphore context monitor when the semaphore command specifies exclusive access. | 12-31-2015 |
| 20150372682 | SAMPLED ANALOG LOOP FILTER FOR PHASE LOCKED LOOPS - An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter. | 12-24-2015 |
| 20150365055 | REDUCED-POWER DISSIPATION FOR CIRCUITS HANDLING DIFFERENTIAL OR PSEUDO-DIFFERENTIAL SIGNALS - In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current i | 12-17-2015 |
| 20150355989 | SAFETY NODE IN INTERCONNECT DATA BUSES - In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall. | 12-10-2015 |
| 20150341003 | DIFFERENTIAL CURRENT AMPLIFIER - A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power. | 11-26-2015 |
| 20150338865 | HIGH-SPEED MULTIPHASE PRECISION CLAMPING CIRCUIT - The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations. | 11-26-2015 |
| 20150333712 | FOUR-STAGE CIRCUIT ARCHITECTURE FOR DETECTING PULSED SIGNALS - An electrical circuit includes a sensor configured to generate a current signal comprising a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from sources other than the target source, a trans-impedance amplifier that amplifies the current signal and generate a low noise signal, and a high pass filter that converts the low noise signal into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive and negative amplitudes. The circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The circuit further includes at least one analog-to-digital converter that receives the integrated values. | 11-19-2015 |
| 20150318190 | BAW Gyroscope with Bottom Electrode - A bulk acoustic wave gyroscope has a primary member in a member plane, and an electrode layer in an electrode plane spaced from the member plane. The electrode layer has a first portion that is electrically isolated from a second portion. The first portion, however, is mechanically coupled with the second portion and faces the primary member (e.g., to actuate or sense movement of the primary member). For support, the second portion of the electrode is directly coupled with structure in the member plane. | 11-05-2015 |
| 20150312663 | SOURCE SEPARATION USING A CIRCULAR MODEL - An approach to separating multiple sources exploits the observation that each source is associated with a linear-circular phase characteristic in which the relative phase between pairs of microphones follows a linear (modulo) pattern. In some examples, a modified RANSAC (Random Sample Consensus) approach is used to identify the frequency/phase samples that are attributed to each source. In some examples, either in combination with the modified RANSAC approach or using other approaches, a wrapped variable representation is used to represent a probability density of phase, thereby avoiding a need to “unwrap” phase in applying probabilistic techniques to estimating delay between sources. | 10-29-2015 |
| 20150311895 | HIGH PERFORMANCE RECONFIGURABLE VOLTAGE BUFFERS - In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high performance (linearity) and reduce power consumption. In addition, they are reconfigurable to optimize the performance and power consumption depending on the input frequency range. | 10-29-2015 |
| 20150311872 | APPARATUS AND METHODS FOR AMPLIFIER INPUT PROTECTION - Apparatus and methods for amplifier input protection are provided. In certain implementations, an amplifier input protection circuit includes a first JFET electrically connected between a first input and a first output, and a second JFET electrically connected between a second input and a second output. Additionally, a first clamp is electrically connected to the first output, and a second clamp is electrically connected to the second output. A first current mirror mirrors a current through the first clamp, and provides the mirrored current to a third JFET electrically connected between the first JFET's source and gate. Additionally, a second current mirror that mirrors a current through the second clamp, and provides the mirrored current to a fourth JFET that is electrically connected between a source and gate of the second JFET. Configuring the protection circuit in this manner can provide the benefits of both low noise and low fault current. | 10-29-2015 |
| 20150309526 | REFERENCE BUFFER WITH WIDE TRIM RANGE - Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an analog signal into its digital representation by comparing analog input signals against one or more voltage references provided by those circuits. In many applications, the speed and accuracy of such voltage references are very important. The speed of the voltage references is related to the physical properties of the devices in the circuit. The accuracy of the voltage reference is directly related to the circuit's ability to trim the full-scale voltage output. The present disclosure describes a fast and efficient reference buffer with a wide trim range which is particular suitable for submicron processes and high speed applications. The reference buffer comprises a plurality of diode-connected transistors, which can be selected to turn on or off using a controller to provide a wide trim range. | 10-29-2015 |
| 20150301968 | METHODS FOR DISCOVERY, CONFIGURATION, AND COORDINATING DATA COMMUNICATIONS BETWEEN MASTER AND SLAVE DEVICES IN A COMMUNICATION SYSTEM - Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices. | 10-22-2015 |
| 20150288379 | CANCELLATION OF FEEDBACK DIGITAL-TO-ANALOG CONVERTER ERRORS IN MULTI-STAGE DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS - The present disclosure describes a mechanism to digitally correct for the static mismatch of the digital-to-analog converter (DAC) in at least the first-stage of a multi-stage noise shaping (MASH) analog-to-digital converter (ADC). The correction is applicable to continuous-time implementations, and is especially attractive for high-speed applications. | 10-08-2015 |
| 20150288336 | APPARATUS AND METHODS FOR MULTI-CHANNEL AUTOZERO AND CHOPPER AMPLIFIERS - Apparatus and methods for multi-channel autozero and chopper amplifiers are provided herein. In certain configurations, an amplifier includes at least three channels that operate using multiple phases, including at least a non-inverting chop phase, an inverting chop phase, and an autozero phase. The amplifier further includes an autozero and chopping timing control circuit, which at least partially interleaves or staggers timing of the channels' phases. For example, in certain configurations, when one or more of the channels are being autozeroed at a certain time instance, at least some of the remaining channels operate in the non-inverting chop phase or the inverting chop phase. | 10-08-2015 |
| 20150270818 | GAIN CALIBRATION - Apparatus and methods calibrate one or more gain ranges for errors. A system can identify offset error and amplification error that occurs when the system transitions from amplifying an input signal by a first gain factor to amplifying the input signal by a second gain factor. To identify the amplification error, the system can compare the slope of the data signal in a source or reference gain range with the slope of the data signal in the destination gain range. To identify the offset error, the system can compare the amplitude of the data signal in a destination gain range with an expected value in the destination gain range. | 09-24-2015 |
| 20150269396 | SYSTEM AND METHOD FOR SECURITY-AWARE MASTER - A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access. | 09-24-2015 |
| 20150257663 | LOW FREQUENCY NOISE IMPROVEMENT IN PLETHYSMOGRAPHY MEASUREMENT SYSTEMS - A plethysmography (“PPG”) measurement system may include at least one source of PPG radiation and at least one auxiliary sensor for detection of PPG radiation. The radiation source emits a portion of the PPG radiation toward a subject and another portion along an optical path for direct communication between the PPG radiation source and the auxiliary sensor. The auxiliary sensor may develop a profile against which measurements from primary PPG sensors, which receive light returning from the subject, may be compared. From this comparison, new PPG signals may be generated that exhibit lower noise than the PPG signals output by PPG sensors. These noise mitigation techniques may be used advantageously by a PPG system to generate more accurate measurements and also to reduce power consumption by the radiation sources. | 09-17-2015 |
| 20150256170 | CIRCUITS WITH FLOATING BIAS - Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well. | 09-10-2015 |
| 20150256169 | APPARATUS AND METHODS FOR INPUT BIAS CURRENT REDUCTION - Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal. | 09-10-2015 |
| 20150254078 | PRE-FETCH UNIT FOR MICROPROCESSORS USING WIDE, SLOW MEMORY - In an example embodiment, a circuit is provided that includes a pre-fetch unit configured to pre-fetch instructions and data from a flash used by a microprocessor and decode the instructions and data without storing and accessing an address history, wherein the pre-fetcher is aware of the microprocessor's instruction set and performs parallel direct decode of each instruction accessed from the flash. In an example embodiment, method for pre-fetching instructions from a flash to a microprocessor is provided that includes reading a line of program code from the flash, assigning the instructions or data in the line to a thread in a hopper maintained in a cache, decoding the instructions to detect branches, and initiating a fetch from the flash if the target instruction is not found in one of the hoppers in the cache, building and maintaining predicted threads of instructions most likely to be executed by the microprocessor. | 09-10-2015 |
| 20150237183 | GRIP DETECTION AND CAPACITIVE GESTURE SYSTEM FOR MOBILE DEVICES - Apparatus and methods are disclosed related to managing characteristics of a mobile device based upon capacitive detection of materials proximate the mobile device, a capacitive gesture system that can allow the same gestures be used in arbitrary locations within range of a mobile device. One such method includes receiving a first capacitive sensor measurement with a first capacitive sensor of the mobile device. The method further includes determining a value indicative of a material adjacent to the mobile device based on a correspondence between the first capacitive sensor measurement and stored values corresponding to different materials. The method further includes sending instructions to adjust a characteristic of the mobile device based on the determined value indicative of the material adjacent to the mobile device. In certain examples, gesture sensing can be performed using capacitive measurements from the capacitive sensors. | 08-20-2015 |
| 20150236739 | APPARATUS AND METHODS FOR WIDE BANDWIDTH ANALOG-TO-DIGITAL CONVERSION OF QUADRATURE RECEIVE SIGNALS - Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone. | 08-20-2015 |
| 20150227162 | REDUNDANT CLOCK SWITCHOVER - Aspects of this disclosure relate to reference switchover. In one embodiment, an apparatus includes a phase error detector, a phase alignment detector, and a selection circuit. The phase error detector is configured to generate an indication of a relative phase difference between a first reference clock signal and a second reference clock signal. The phase alignment detector is configured to receive the indication of the relative phase difference and determine when the relative phase difference satisfies a preset threshold. The selection circuit is configured to transition from providing the first reference clock signal as a clock system reference signal to providing the second reference clock signal as the clock system reference signal responsive to the phase alignment detector detecting that the relative phase difference satisfies the preset threshold. | 08-13-2015 |
| 20150220100 | CURRENT SOURCE CALIBRATION TRACKING TEMPERATURE AND BIAS CURRENT - In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures. | 08-06-2015 |
| 20150214973 | MULTI-INPUT ANALOG-TO-DIGITAL CONVERTER - In an example, there is disclosed a multiple-input analog-to-digital converter configured to receive a plurality of analog inputs and to output one or more digital outputs. In one embodiment, two input analog signals are received. The two analog signals may be mixed in a combiner, which provides them to a pipeline ADC. In another embodiment, the combiner may time multiplex the two analog input signals and provide two separate outputs signals. Advantageously, the multiple-input ADC of the present Specification may be realized with a single ADC pipeline. | 07-30-2015 |
| 20150180501 | COMPLEMENTARY SWITCHES IN CURRENT SWITCHING DIGITAL TO ANALOG CONVERTERS - The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches. | 06-25-2015 |
| 20150180455 | APPARATUS AND METHODS FOR MULTIPHASE OSCILLATORS - Apparatus and methods for multiphase oscillators are provided. In certain implementations, an oscillator system includes a first multiphase oscillator and a second multiphase oscillator that are phase and frequency-locked. Additionally, the first and second multiphase oscillators are phase-locked by an amount of phase shift that provides colocated clock signal phases of relatively wide angular distances, which can be used by the oscillators' amplification circuits. The first and/or second multiphase oscillators include one or more amplification circuits that operate using at least one clock signal phase generated by the first multiphase oscillator and using at least one clock signal phase generated by the second multiphase oscillator. | 06-25-2015 |
| 20150162894 | SYNCHRONOUS CHARGE SHARING FILTER - A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate. | 06-11-2015 |
| 20150155878 | STOCHASTIC ENCODING IN ANALOG TO DIGITAL CONVERSION - A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal. | 06-04-2015 |
| 20150154027 | THREAD OFFSET COUNTER - In an example, there is disclosed a digital signal processor having a register containing a modular integer configured for use as a thread offset counter. In a multi-stage, pipelined loop, which may be implemented in microcode, the main body of the loop has only one repeating stage. On each stage, the operation executed by each thread of the single repeating stage is identified by the sum of a fixed integer and the thread offset counter. After each pass through the loop, the thread offset counter is incremented, thus maintaining pipelined operation of the single repeating stage. | 06-04-2015 |
| 20150145588 | BI-DIRECTIONAL CURRENT SENSOR - A bidirectional current sensor circuit can be configured to generate a scaled version of a load current using a first transistor from a power regulator output stage and a second transistor that can be a mirror or scaled version of the first transistor. A trim circuit can be provided to correct gain errors under current sinking or current sourcing conditions. In an example, the bidirectional current sensor circuit can be configured to detect a polarity or a magnitude of a current signal that is used to operate a thermoelectric device. | 05-28-2015 |
| 20150145537 | CAPACITIVE SENSOR WITH DIFFERENTIAL SHIELD - The present disclosure describes a differential shield capacitive sensor design. The sensor design uses a differential measurement to measure capacitance and a pair of traces are used to differentially reject the response of the sensor traces and balance any parasitic capacitances. In some embodiments, the sensor design includes a differential sensor design on a bottom side of a flex circuit to differentially balance the environment and reject noise coupling to the sensor. The top side of the flex circuit can include a single ended design for proper environment sensing. The spatial arrangement and size of the sensors may vary depending on the application. | 05-28-2015 |
| 20150138678 | APPARATUS AND METHOD FOR PROTECTING RF AND MICROWAVE INTEGRATED CIRCUITS - Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices. | 05-21-2015 |
| 20150137932 | SMALL SIZE AND FULLY INTEGRATED POWER CONVERTER WITH MAGNETICS ON CHIP - An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary. | 05-21-2015 |
| 20150137882 | ANALOG ACTIVE LOW-PASS FILTERS - Apparatus and methods for high-frequency low-pass filtering are disclosed. A first resistor is operatively coupled between a first node and a second node. A second resistor is operatively coupled between the second node and a third node. An amplifier circuit has a first input operatively coupled to the third node and a first output operatively coupled to a fourth node. The first output is configured to provide a first output signal. A first complex impedance network is operatively coupled between the fourth node and the third node. A first feedback path is operatively coupled between the fourth node and the second node. The first feedback path is configured to invert at least a portion of the first output signal. The first feedback path is further configured to provide a first feedback capacitance at the second node. | 05-21-2015 |
| 20150128701 | Method and Apparatus for Detecting Linear and Rotational Movement - A method of detecting motion provides a resonator having a mass, moves the mass in a translational mode, and actuates the mass in a given bulk mode. The mass moves in the translational and given bulk modes at substantially the same time and, accordingly, the resonator is configured to detect linear and rotational movement when moving and actuating the mass in the translational and given bulk modes. The method produces one or more movement signals representing the detected linear and rotational movement. | 05-14-2015 |
| 20150127297 | MULTIUSE OPTICAL SENSOR - One or more electromagnetic radiation sources, such as a light emitting diode, may emit electromagnetic waves into a volume of space. When an object enters the volume of space, the electromagnetic waves may reflect off the object and strike one or more position sensitive detectors after passing through an imaging optical system such as glass, plastic lens, or a pinhole located at known distances from the sources. Mixed signal electronics may process detected signals at the position sensitive detectors to calculate position information as well as total reflected light intensity, which may be used in medical and other applications. A transparent barrier may separate the sources and detectors from the objects entering the volume of space and reflecting emitted waves. Methods and devices are provided. | 05-07-2015 |
| 20150123649 | SAMPLING CONTROL FOR MAXIMUM POWER POINT TRACKING - Apparatus and techniques for controlling measurement of an electrical parameter of an energy source can be used to obtain information for use in enhancing a power transfer efficiency between the energy source and a load. For example, during a first measurement cycle, information indicative of the electrical parameter of the energy source can be obtained using a measurement circuit during a first sampling duration in which the load is decoupled from the energy source. The information indicative of the obtained electrical parameter can be compared to a threshold. In response to the comparing, a different second sampling duration can be determined for use in obtaining information indicative of the electrical parameter during a subsequent measurement cycle. The information indicative of the electrical parameter of the energy source includes information for use in enhancing the power transfer efficiency between the energy source and the load. | 05-07-2015 |
| 20150122024 | Accelerometer with Offset Compensation - An accelerometer has a movable mass suspended above a substrate, and a variable acceleration capacitor supported by the substrate. The movable mass has a mass anchor securing the mass to the substrate, while the acceleration capacitor has both a stationary finger extending from the substrate, and a movable finger extending from the movable mass. The accelerometer also has a variable stress capacitor, which also includes the stress finger, for determining movement of the mass anchor relative to the substrate. | 05-07-2015 |
| 20150117074 | AUTO-TUNING CURRENT LOOP COMPENSATION FOR POWER FACTOR CORRECTION CONTROLLER - An apparatus comprises a power converter circuit and a controller. The power converter circuit includes an inductor, a switching circuit, and a digital control loop circuit having an adjustable transfer function, wherein the transfer function includes a zero variable and a signal gain variable. The controller includes a tuning module configured to set a value for the zero variable, set the signal gain variable to a first gain value, determine a control error for the first gain value setting, wherein the control error is a difference between a reference current and a load current at a circuit load, iteratively update the gain value of the signal gain variable and determine the control error for the updated gain value, and set an operating gain value of the signal gain variable to the gain value corresponding to a minimum control error. | 04-30-2015 |
| 20150116882 | APPARATUS AND METHOD FOR TIME-DELAYED THERMAL OVERLOAD PROTECTION - Apparatus and methods for time-delayed thermal overload protection are provided. In one aspect, an integrated circuit includes a primary circuit disposed in a primary circuit region on a substrate, and a thermal protection circuit disposed in a thermal protection circuit region on the substrate and in thermal communication with the primary circuit. The thermal protection circuit includes a temperature sensing circuit configured to sense a temperature of the thermal protection circuit region and to activate a temperature warning signal when the temperature exceeds a temperature threshold level. The thermal protection circuit additionally includes a time delay circuit configured to activate a shut off signal to disable at least a portion of the primary circuit when the temperature warning signal is active for a duration exceeding a time delay. | 04-30-2015 |
| 20150115376 | MEMS Device with Outgassing Shield - A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap. | 04-30-2015 |
| 20150101854 | MINIATURE PLANAR TRANSFORMER - An inductive device may include a pair of half-shell magnetically-conductive housings joined together and defining an enclosed cavity between them. The inductive device may also include primary and secondary windings provided spatially within the cavity providing magnetic coupling between them. The windings may be electrically insulated from each other and terminals of the primary and secondary windings may traverse to an exterior of the inductive device. | 04-16-2015 |
| 20150097637 | PROGRAMMABLE FILTER - In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance. | 04-09-2015 |
| 20150097253 | Sealed MEMS Devices with Multiple Chamber Pressures - A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure). | 04-09-2015 |
| 20150091744 | ACCURACY ENHANCEMENT TECHNIQUES FOR ADCs - Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error. | 04-02-2015 |
| 20150091549 | MICROWAVE VOLTMETER USING FULLY-LINEARIZED DIODE DETECTOR - A radio frequency diode detector has a set of diodes having a differential voltage output, and a current source electrically coupled to the ring of diodes, the current source coupled to provide a forward bias current. This is followed by nonlinear signal processing to create an overall linear detector suitable for use in microwave power measurement. | 04-02-2015 |
| 20150084924 | POSITION DETERMINATION TECHNIQUES IN RESISTIVE TOUCH SCREEN APPLICATIONS - Systems and methods to determine locations for dual touch operations performed on a four-wire resistive touch screen. The systems and methods may include measuring signals from pairs of electrodes on each of a first and second resistive sheet of the resistive touch screen in two phases of operation. The systems and methods may further include determining touch screen segment resistances from the signal measurements. The systems and methods may determine locations corresponding to the dual touch operations from the resistances. The systems and methods may also determine locations from the signal measurements. | 03-26-2015 |
| 20150078501 | LOCK DETECTOR FOR PHASE-LOCKED LOOP - A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal. | 03-19-2015 |
| 20150077183 | CURRENT-FEEDBACK OPERATIONAL AMPLIFIER - An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier. | 03-19-2015 |
| 20150076628 | MULTI-PORT DEVICE PACKAGE - An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening. | 03-19-2015 |
| 20150076557 | SIGNAL IO PROTECTION DEVICES REFERENCED TO SINGLE POWER SUPPLY AND METHODS OF FORMING THE SAME - Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation. | 03-19-2015 |
| 20150070806 | HIGH VOLTAGE TOLERANT SUPPLY CLAMP - Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event. | 03-12-2015 |
| 20150061776 | HIGH SPEED AMPLIFIER - A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may biase the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit. | 03-05-2015 |
| 20150061768 | HIGH SPEED AMPLIFIER - A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase. | 03-05-2015 |
| 20150054559 | DC RESTORATION FOR SYNCHRONIZATION SIGNALS - In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal. | 02-26-2015 |
| 20150054491 | SYSTEM AND METHOD FOR DETECTING A FUNDAMENTAL FREQUENCY OF AN ELECTRIC POWER SYSTEM - A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal. | 02-26-2015 |
| 20150049666 | MULTI-CARRIER BASE STATION RECEIVER - Embodiments of the present invention may provide a receiver. The receiver may include an RF section and a quadrature mixture, coupled to the RF section, to downconvert a first group of wireless signals directly to baseband frequency quadrature signals and to downconvert a second group of wireless signals to intermediate frequency quadrature signals. The receiver may also include a pair of analog-to-digital converters (ADCs) to convert the downconverted quadrature signals to corresponding digital quadrature signals. Further, the receiver may include a digital section having two paths to perform signal processing on the digital baseband frequency quadrature signals and to downconvert the digital intermediate frequency signals to baseband cancelling a third order harmonic distortion therein. The receiver may be provided on a monolithically integrated circuit. | 02-19-2015 |
| 20150048961 | HIGH OUTPUT POWER DIGITAL-TO-ANALOG CONVERTER SYSTEM - The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more). | 02-19-2015 |
| 20150048892 | LOW-NOISE CURRENT SOURCE - In one example embodiment, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture. | 02-19-2015 |
| 20150044522 | BATTERY STACK WITH LEAPFROGGING PROTOCOL - Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage. | 02-12-2015 |
| 20150044521 | BATTERY CELL WITH DISCRETION TO DRIVE LOADS WITHIN BATTERY STACK - Embodiments of the present invention are directed to improved battery packaging designs. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. Moreover, the design may allow for more efficient charging/discharging of the cells that are most ready to accept/supply current. | 02-12-2015 |
| 20150044515 | BATTERY PACK WITH LOCALLY CONTROLLED DISCONNECT SAFEGUARDS - Embodiments of the present invention are directed to an improved battery packaging design. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. | 02-12-2015 |
| 20150042283 | BATTERY STACK WITH DISTRIBUTED CONTROL OF CELLS DRIVING EVENTS - Embodiments of the present invention relate to a battery stack controller system. The system may include a plurality of battery cell stages with cell controller systems (as described above with respect to the first embodiment). The system may also include a stack controller to send charge/discharge commands to the battery stack via a communication network. The stack controller may send the commands to the battery stack based on the requirements of a load or the state of the battery cell stages. The battery cell stages may either comply with the commands or send the commands to neighboring cells via the communication network. | 02-12-2015 |
| 20150035564 | POWER SUPPLY MONITOR - An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold. | 02-05-2015 |
| 20150030102 | WIDEBAND QUADRATURE ERROR CORRECTION - A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. In a first state, the QEC controller calibrates the loopback receiver to remove quadrature imbalance in the loopback receiver. In a second state, a communication pathway is provided between the transmitter and the loopback receiver, and the QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter. | 01-29-2015 |
| 20150028835 | AREA-EFFICIENT FREQUENCY COMPENSATION - A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor. | 01-29-2015 |
| 20150028499 | Apparatus and Method for Forming Alignment Features for Back Side Processing of a Wafer - A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer. | 01-29-2015 |
| 20150028213 | System and Method For LIDAR Signal Conditioning - Various embodiments provide systems and methods that allow a LIDAR system to sense nearby objects with relatively low-cost elements, and fewer elements than traditional LIDAR systems by sampling an infrared pulse at a high sample rate and storing the samples in the analog domain. The samples may then be digitized at a rate slower than the sample rate. | 01-29-2015 |
| 20150016471 | CONFIGURABLE QUAD BYTE FRAMER - A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed. | 01-15-2015 |
| 20150015337 | MODULAR APPROACH FOR REDUCING FLICKER NOISE OF MOSFETS - In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc. | 01-15-2015 |
| 20150015239 | APPARATUS AND METHOD FOR REAL TIME HARMONIC SPECTRAL ANALYZER - In one embodiment, a measuring device may comprise two oscillators. The first oscillator may generate a local reference signal in a frequency detector to detect a fundamental frequency of the AC. The second oscillator may generate two substantially mutually orthogonal sinusoid signals having the selected frequency. The measuring device further may comprise a first group of multipliers that mixes the two sinusoid signals with a current and a voltage data signal of the AC respectively, a group of low-pass filters for removing high frequency components from the multiplication products, a second group of multipliers for mixing the filtered multiplication produces respectively, and a plurality of adders each to sum together a pair of multiplication products of the second group of multipliers. | 01-15-2015 |
| 20150009050 | DIFFERENTIAL DECODER - In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal. | 01-08-2015 |
| 20150008960 | DIGITAL PHASE DETECTOR - According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase. | 01-08-2015 |
| 20140375985 | OPTICAL ANGLE MEASUREMENT - An optical detector may include an epitaxial layer having a continuous surface provided on a surface of a substrate. Two or more electrodes may be arranged at different positions in the epitaxial layer so that the electron-hole pairs generated in the epitaxial layer from incident light passing through the aperture and reaching the epitaxial layer have a varying probability of being collected by each of the electrodes as the angle of the incident light changes. The electrodes may be arranged at different depths in the epitaxial layer. The epitaxial layer may be continuous and have a continuous aperture-facing surface between each of the electrodes associated with a particular aperture to ensure that more light passing through the aperture is absorbable in the epitaxial layer and subsequently detectable by the electrodes. This may result in improved light detection capabilities. | 12-25-2014 |
| 20140375978 | OPTICAL TIME-OF-FLIGHT SYSTEM - Time-of-flight technology may be combined with optical detection technology identifying an angle of a light pulse emitted from a transmitter and reflected off an object based on a proportion of the reflected light pulse detected at each of at least two light sensors. The optical detection technology may include a light detector with two or more light sensors arranged at different orientations with respect to an aperture in the detector so that each sensor is able to detect a different subset of the light passing through the aperture. The effective angle of the light passing through aperture may then be calculated from the proportion of light detected at the each of the sensors. The effective angle information may be combined with a calculated time-of-flight of the light pulse to accurately identify a position of the object relative to the detector in two or three dimensions. | 12-25-2014 |
| 20140374850 | Apparatus and Method for Shielding and Biasing in MEMS Devices Encapsulated by Active Circuitry - One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate. | 12-25-2014 |
| 20140374570 | GAIN-RANGING CHARGE AMPLIFIER - The system may include a pixel array, a selector, a sampler, and a converter. The pixel array may generate output signals that representing radiation incident upon the pixel array. The selector may select one of the output signals. The sampler may sample the selected output signal. The converter may generate a digital signal based upon the selected output signal. The sampler may include a charge integrator that compensates for parasitic capacitance of the selector by selecting a first feedback capacitance to obtain a first sample, and after obtaining the first sample, selecting a second feedback capacitance to obtain a second sample. The first feedback capacitance may be greater than the second feedback capacitance. | 12-25-2014 |
| 20140356989 | METHOD OF MANUFACTURING MEMS DEVICES WITH RELIABLE HERMETIC SEAL - Manufactured capped MEMS device wafers are tested for hermeticity on a vacuum prober at differing pressures or on a wafer prober at differing temperatures. Resonant frequency testing is conducted. Leaking MEMS devices are distinguished from the remaining MEMS devices on the basis of quality factor (“Q”) measurements obtained from the resonant frequency testing. | 12-04-2014 |
| 20140344545 | PARALLEL ATOMIC INCREMENT - Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value. | 11-20-2014 |
| 20140341257 | TEMPERATURE SENSOR SYSTEM AND METHOD - A temperature sensing system can include first and second temperature sensing circuits and a digitizing encoder. The first and second temperature sensing circuits can include respective devices with semiconductor junction areas. Temperature information can be determined from one or more characteristic signals measured from the temperature sensing circuits. A feedback circuit can be configured to provide one or more offset signals to the digitizing encoder. The one or more offset signals can correspond to components or characteristics of the first and second temperature sensing circuits. In an example, at least one of the first and second temperature sensing circuits can include an adjustable load circuit for use with the other of the first and second temperature sensing circuits. | 11-20-2014 |
| 20140340302 | INTEGRATED GESTURE SENSOR MODULE - An integrated gesture sensor module includes an optical sensor die, an application-specific integrated circuit (ASIC) die, and an optical emitter die disposed in a single package. The optical sensor die and ASIC die can be disposed in a first cavity of the package, and the optical emitter die can be disposed in a second cavity of the package. The second cavity can be conical or step-shaped so that the opening defining the cavity increases with distance from the upper surface of the optical emitter die. The upper surface of the optical emitter die may be higher than the upper surface of the optical sensor die. An optical barrier positioned between the first and second cavities can include a portion of a pre-molded, laminate, or ceramic package, molding compound, and/or metallized vias. | 11-20-2014 |
| 20140340149 | METHOD FOR LOW POWER LOW NOISE INPUT BIAS CURRENT COMPENSATION - Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation. | 11-20-2014 |
| 20140340140 | PHASED-ARRAY CHARGE PUMP SUPPLY - A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal. | 11-20-2014 |
| 20140333463 | SPLIT-PATH DATA ACQUISITION SIGNAL CHAIN - The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal. | 11-13-2014 |
| 20140332947 | PACKAGES AND METHODS FOR PACKAGING - Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin. | 11-13-2014 |
| 20140323844 | CIRCUIT ARCHITECTURE FOR PHOTODIODES - An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values. | 10-30-2014 |
| 20140313065 | CLOCK SIGNAL ERROR CORRECTION IN A DIGITAL-TO-ANALOG CONVERTER - In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core. | 10-23-2014 |
| 20140292249 | CONTROL TECHNIQUES FOR MOTOR DRIVEN SYSTEMS - Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive D | 10-02-2014 |
| 20140285167 | AUTO-TUNING SWITCHING REGULATOR - In an example, a system and method are disclosed for providing a single control law that is operable to regulate both small-signal, steady-state operation, and large-signal transients of a switching regulator. The control law is based on detecting a zero-crossing of capacitor current, and projecting in advance a turning point for either ramping up or ramping down capacitor voltage at a target voltage. Certain embodiments may realize the control function in high-speed analog components, although certain other embodiments may implement the same or a similar control law in a digital controller. | 09-25-2014 |
| 20140281654 | SYNCHRONIZING DATA TRANSFER FROM A CORE TO A PHYSICAL INTERFACE - In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input. | 09-18-2014 |
| 20140280421 | FFT ACCELERATOR - An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points. | 09-18-2014 |
| 20140273902 | QUADRATURE ERROR CORRECTION USING POLYNOMINAL MODELS IN TONE CALIBRATION - One example embodiment provides a system, apparatus, and method for using polynomial models in tone calibration for quadrature error correction in I/Q receivers. In one example embodiment, method for calibrating an I/Q receiver is provided and includes receiving a first mismatch parameter indicating a mismatch between I and Q channels of the I/Q receiver; and estimating a second mismatch parameter from the first mismatch parameter using a polynomial model. | 09-18-2014 |
| 20140270002 | SYSTEM AND METHOD QUADRATURE ERROR DETECTION AND CORRECTION - In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD). | 09-18-2014 |
| 20140270001 | QUADRATURE ERROR DETECTION AND CORRECTION - In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD). | 09-18-2014 |
| 20140269988 | RADIO FREQUENCY DOMAIN DIGITAL PRE-DISTORTION - Digital pre-distortion (DPD) systems are often used to improve the linearity of a power amplifier in transmitters. These DPD systems are typically implemented in baseband (prior to modulation). However, ever increasing signal bandwidth requirements limits the practicality of DPD systems implemented in baseband. A DPD system in the radio frequency (RF) domain (as opposed to in baseband) can solve this problem and further improve a DPD system's ability to correct for distortions. The RF domain DPD system is upstream from a digital-to-analog converter, and performs DPD after a baseband signal is up-sampled into the RF domain (after the modulation process). When compared against a baseband DPD system, the RF domain DPD system can handle significantly wider bandwidth, and has an improved ability to linearize a wide variety of distortions present in the spectrum. | 09-18-2014 |
| 20140269979 | ALL DIGITAL ZERO-VOLTAGE SWITCHING - Power efficiency is an important design requirement of power amplifiers. To improve power efficiency, a solution proposed in this present disclosure includes an all-digital zero-voltage switching apparatus for directly driving a switching power amplifier through a desired current pulse shape. The apparatus includes a digital engine and a digital-to-analog converter (DAC). The digital engine processes baseband data and generates a digital output. The digital output of the digital engine drives the DAC to generate a digitally controlled current output having that desired current pulse shape. The digitally controlled current output is used to directly drive the switch power amplifier to improve power efficiency. The digitally controlled current output comprising digitally generated current pulses is controlled accurately by the digital engine and the DAC, and thus allows the switching power amplifier to operate optimally with higher power efficiency than conventional power amplifiers. | 09-18-2014 |
| 20140269866 | APPARATUS AND METHODS FOR LOSS OF SIGNAL DETECTION - Apparatus and methods for loss of signal detection are provided. In one embodiment, a detection circuit for monitoring an input includes a small signal boost circuit, a rectifier circuit, a low-pass filter, and one or more comparators. The small signal boost circuit can generate an amplified signal by providing a first amount of gain to an input signal when the input signal is relatively small, but can saturate and provide reduced gain without external gain control adjustment when the input signal does not have a relatively small magnitude. The rectifier circuit can rectify the boosted signal to generate a rectified signal, and the low-pass filter can filter the rectified signal to generate a filtered signal. The one or more comparators can compare the filtered signal to one or more decision threshold voltages to determine the presence or absence of the input signal on the input. | 09-18-2014 |
| 20140269863 | TRANSMITTER LO LEAKAGE CALIBRATION SCHEME USING LOOPBACK CIRCUITRY - A method and apparatus for estimating and compensating TX LO leakage using circuitry on a loopback path connecting the transmitter and receiver are provided. The TX LO leakage may be estimated by measuring the DC signal on the receiver, measuring the phase difference between the received LO signal and the receiver LO signal, and filtering LO harmonics that may arise from the use of non-linear mixers. The DC signal on the receiver may be measured by opening and closing the loopback path, or changing the gain of the loopback path, or flipping the phase of looped back TX signal. The method may be used in an initialization or tracking calibration scheme. | 09-18-2014 |
| 20140266847 | BACKGROUND CALIBRATION OF ADC REFERENCE VOLTAGE DUE TO INPUT SIGNAL DEPENDENCY - Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion. | 09-18-2014 |
| 20140266844 | METHOD AND DEVICE FOR IMPROVING CONVERGENCE TIME IN CORRELATION-BASED ALGORITHMS - A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals. | 09-18-2014 |
| 20140266566 | COMPOSITE RESISTORS - A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor. | 09-18-2014 |
| 20140266481 | OSCILLATOR WITH PRIMARY AND SECONDARY LC CIRCUITS - One aspect of this disclosure is an apparatus including an oscillator that includes a secondary LC circuit to increase a tuning range of the oscillator and/or to reduce a phase noise of the oscillator. Another aspect of this disclosure is an apparatus that includes oscillator with a primary LC circuit and a secondary LC circuit. This oscillator can operate in a primary oscillation mode or a secondary oscillation mode, depending on whether oscillation is set by the primary LC circuit or the secondary LC circuit. | 09-18-2014 |
| 20140266476 | EXTENDED RANGE RING OSCILLATOR USING SCALABLE FEEDBACK - A clock system including a ring oscillator having a plurality of cascaded inverters, each of the cascaded inverters having a pair of inputs coupled to outputs of a respectively adjacent inverter stage and having a pair of outputs coupled to inputs of another respectively adjacent inverter stage, each inverter stage having a common mode control circuit provided therein, and a feedback controller adapted to transmit a control signal to the common mode control circuit of at least one of the inverters. | 09-18-2014 |
| 20140266441 | THREE STAGE AMPLIFIER - A cascaded amplifier including a pre-amplifier stage having a pair of first transistors, each of the first transistors having a first gate terminal coupled to a first input voltage, a trans-conductive (gm) amplifier stage having a pair of second transistors, each of the second transistors having a second gate terminal coupled to a drain terminal of one of the first transistors, and an integrator amplifier stage having a pair of third transistors, each of the third transistors having a third gate terminal coupled to a drain node of one of the second transistors, each of the third transistors having their drain terminals coupled to an output voltage. | 09-18-2014 |
| 20140266437 | ACTIVE CASCODE CIRCUIT USING BACKGATE CONTROL - An example embodiment of an active cascode circuit has a control circuit for control of the gate to source voltage (VGS) of at least one transistor in the active cascode circuit. The embodiment may be configured so that control of the VGS also controls the voltage Vin on the input. Vin may be adjusted without altering the device geometry or changing the drain current. This allows for better control and optimization of available headroom for the input voltage in low voltage designs and also results in higher active cascode circuit bandwidth and/or higher output impedance (Rout) for a given power level. | 09-18-2014 |
| 20140266376 | ACTIVE CLOCK TREE FOR DATA CONVERTERS - A multi-stage clock distribution circuit for an integrated circuit is provided. The clock distribution circuit may route a common clock signal to a plurality of clock receiver circuits. Each stage in the distribution circuit may include a plurality of buffers. Outputs of at least some, perhaps all, of the buffers may be connected to each other by an interconnect. The interconnect may align clock signals that are output by the interconnected buffers and thereby encourage synchronization of those clock signals. Other stages of the clock distribution signal may be connected as well. | 09-18-2014 |
| 20140266373 | INTEGRATED DELAYED CLOCK FOR HIGH SPEED ISOLATED SPI COMMUNICATION - A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier. | 09-18-2014 |
| 20140266358 | LOW-DISTORTION PROGRAMMABLE CAPACITOR ARRAY - In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system. | 09-18-2014 |
| 20140266332 | ISOLATOR-BASED TRANSMISSION SYSTEM WITH SIDE ISOLATOR CHANNEL FOR REFRESH SIGNALS - A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1 | 09-18-2014 |
| 20140265578 | FINE TIMING ADJUSTMENT METHOD - Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage. | 09-18-2014 |
| 20140264881 | METHODS AND STRUCTURES TO FACILITATE THROUGH-SILICON VIAS - In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch. | 09-18-2014 |
| 20140264520 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR PROTECTION FROM DAMAGE TO GATE DIELECTRIC - An integrated circuit device comprises a common-gated dual-oxide MOSFET including a protective device and a MOSFET. A common gate electrode serves as a gate electrode of the protective device and as a gate of the MOSFET. The protective device comprises a first gate dielectric having a first thickness over a first channel region and the MOSFET comprises a second gate dielectric thicker than the first gate dielectric over a second channel region. During a plasma process, a first current can flow through the first dielectric that is higher than a second current through the second dielectric. | 09-18-2014 |
| 20140262464 | LATERALLY COUPLED ISOLATOR DEVICES - A laterally coupled isolator includes a pair of isolator traces provided in a common dielectric layer and separated by a distance that defines the isolation strength of the system. Circuit designers can vary the lateral distance to tailor isolation rating to suit individual design needs. A second embodiment includes a semiconductor substrate, provided below the isolator traces that includes a communication circuit electrically coupled to one of the isolator devices | 09-18-2014 |
| 20140260611 | XY-Axis Gyroscopes with Electrode Configuration for Detecting Quadrature Errors and Out-of-Plane Sense Modes - Various embodiments include feedback circuits for tuning the drive modes of a shell-type gyroscope, while other embodiments include separate circuits for tuning the sense mode of a shell-type gyroscope to reduce or avoid quadrature errors. Still other embodiments include circuits to excite the sense modes (i.e., the out-of-plane modes) of a gyroscope without requiring the application of a rotation to the gyroscope, to ensure that the sense modes are aligned with the sense electrodes. | 09-18-2014 |
| 20140260515 | System and Method for Run-Time Hermeticity Detection of a Capped MEMS Device - Determining if a hermetically sealed MEMs device loses hermeticity during operation. In one embodiment, the MEMs device is an accelerometer. A test signal having an associated frequency above an operational frequency range for the accelerometer is provided to the accelerometer at an input during operation of the accelerometer for sensing an acceleration. The output signal of the accelerometer is filtered at least above the operational frequency range of the accelerometer producing a test output signal. The test output signal is then compared to a predetermined threshold to determine if the amplitude of the test output signal differs from the threshold. If the amplitude of the test output signal differs from the predetermined threshold, an error signal is produced indicating that hermeticity of the accelerometer has been lost. | 09-18-2014 |
| 20140254835 | Packaged Microphone System with a Permanent Magnet - A microphone structure has a lid forming an interior chamber. The lid includes a permanent magnet for forming a permanent magnetic field. The microphone structure includes an aperture for permitting acoustic access to the interior of the chamber and thus, the MEMS microphone. The MEMS microphone structure includes a substrate mechanically coupled to an electrically conductive diaphragm. The electrically conductive diaphragm has a first side defining a plane and the diaphragm moves through a range of motion perpendicular the plane of the first side. The permanent magnetic field is perpendicular to the direction of motion of the diaphragm and linear within the range of motion, such that a current will be generated and sensed by sensors within an electric circuit loop that includes the diaphragm. | 09-11-2014 |
| 20140253353 | APPARATUS AND METHOD FOR REDUCING SAMPLING CIRCUIT TIMING MISMATCH - An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels. | 09-11-2014 |
| 20140251011 | Tilt Mode Accelerometer with improved Offset and Noise Performance - A single-axis tilt-mode microelectromechanical accelerometer structure. The structure includes a substrate having a top surface defined by a first end and a second end. Coupled to the substrate is a first asymmetrically-shaped mass suspended above the substrate pivotable about a first pivot point on the substrate between the first end and the second end and a second asymmetrically-shaped mass suspended above the substrate pivotable about a second pivot point on the substrate between the first end and the second end. The structure also includes a first set of electrodes positioned on the substrate and below the first asymmetrically-shaped mass and a second set of electrodes positioned on the substrate and below the second asymmetrically-shaped mass. | 09-11-2014 |
| 20140250041 | DISTRIBUTED FACTOR GRAPH SYSTEM - In a data processing system, a method for implementing a factor graph having variable nodes and function nodes connected to each other by edges includes implementing a first function node and a on a first computer system, the first computer system being in network communication with a second computer system; establishing a network connection to each of a plurality of processing systems; receiving, at the first function node, soft data from a variable node implemented on one of the processing systems, the soft data including an estimate of a value and information representative of an extent to which the estimate is believed to correspond to a correct value; and transmitting, from the first function node to the one of the processing systems, soft data representing an updated estimate of the value. | 09-04-2014 |
| 20140247095 | FREQUENCY TEMPERATURE OFFSET COMPENSATION - One embodiment relates to a method of compensating for crystal frequency variation over temperature. An example method includes obtaining an indication of temperature, computing a temperature compensation value based on the indication of temperature and a piecewise linear temperature compensation approximation, and compensating for a temperature offset in a crystal reference signal by adjusting a division ratio of a fractional divider in a phase-locked loop. The piecewise linear temperature compensation approximation can represent an approximation of frequency error in a crystal reference signal originating from a crystal over temperature. The piecewise linear temperature compensation approximation can be, for example, a linear approximation, a quadratic approximation, or a cubic approximation. | 09-04-2014 |
| 20140233773 | CHARGE SHARING ANALOG COMPUTATION CIRCUITRY AND APPLICATIONS - In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters. | 08-21-2014 |
| 20140232460 | DIFFERENTIAL CHARGE REDUCTION - One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled. | 08-21-2014 |
| 20140232435 | ANALOG MINIMUM OR MAXIMUM VOLTAGE SELECTOR CIRCUIT - A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell. | 08-21-2014 |
| 20140223439 | SUPERSCALAR CONTROL FOR A PROBABILITY COMPUTER - A method of executing operations in parallel in a probability processing system includes providing a probability processor for executing said operations; and providing a scheduler for identifying, from said operations, those operations that can be executed in parallel. Providing the scheduler includes compiling code written in a probability programming language, that includes both modeling instructions and instructions for scheduling. | 08-07-2014 |
| 20140220723 | Methods and Structures for Using Diamond in the Production of MEMS - A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released. | 08-07-2014 |
| 20140218153 | STEP UP OR STEP DOWN MICRO-TRANSFORMER WITH TIGHT MAGNETIC COUPLING - A system and method for manufacturing of a micro-transformer providing direct electrical isolation between a primary winding and a secondary winding while featuring tight magnetic coupling for a large possible step-up or step-down ratio. The micro-transformer may be implemented in an integrated circuit, and may include a magnetic core. A high stepping ratio, e.g. approximately 50 to 100, may be achieved by connecting multiple symmetric primary windings in parallel and multiple symmetric secondary windings in series, or vice-versa. A plurality of windings may be stacked vertically. The micro-transformer may be of particular utility in wireless sensor networks, thermal and vibrational energy harvesters, power converters, and signal isolators. | 08-07-2014 |
| 20140217566 | DOUBLE-SIDED PACKAGE - Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die. | 08-07-2014 |
| 20140217521 | MEMS Device With Stress Relief Structures - An encapsulated MEMS device includes stress-relief trenches in a region of its substrate that surrounds the movable micromachined structures and that is covered by a cap, such that the trenches are fluidly exposed to a cavity between the substrate and the cap. A method of fabricating a MEMS device includes fabricating stress-relief trenches through a substrate and fabricating movable micromachined structures, and capping the device prior art encapsulating the device. | 08-07-2014 |
| 20140210546 | TUNING CIRCUITRY AND METHOD FOR ACTIVE FILTERS - Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency. | 07-31-2014 |
| 20140210538 | MULTIPLE RAMP VARIABLE ATTENUATOR - The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch. | 07-31-2014 |
| 20140208849 | Teeter Totter Accelerometer with Unbalanced Mass - A balanced teeter-totter accelerometer has a mass suspended above a substrate, the mass having an axis of rotation that is parallel to the substrate and substantially geometrically centered with respect to the shape of the mass. A physical acceleration in a direction perpendicular to the substrate causes the mass to rotate about the axis of rotation. The rotation is sensed by measuring a change in capacitance of electrodes on the substrate. The accelerometer may be calibrated using the same sensing electrodes. | 07-31-2014 |
| 20140203422 | Microchip with Blocking Apparatus and Method of Fabricating Microchip - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 07-24-2014 |
| 20140197531 | COMPACT DEVICE PACKAGE - Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements. | 07-17-2014 |
| 20140195581 | FIXED POINT DIVISION CIRCUIT UTILIZING FLOATING POINT ARCHITECTURE - A system, method, and computer program product for dividing two binary numbers. The divider implements a fixed point division function using a floating point normalization architecture to yield the closest initial quotient approximation. The divider normalizes the input dividend and divisor to a range of [0.5, 1.0) by scaling each by necessary factors of two. The normalized inputs are submitted to a divider core that may be optimized for dividing inputs of such limited ranges. The divider core output is then rescaled by an appropriate factor of two, appropriately signed, and loaded into saturating registers for output in various formats. The divider core progressively outputs quotient bits in decreasing order of significance until a predetermined level of precision is reached, typically fewer bits than in a complete quotient, for faster output. One embodiment generates the six most significant quotient bits in one clock cycle. | 07-10-2014 |
| 20140193090 | APPARATUS AND METHODS FOR REDUCING COMMON-MODE NOISE IN AN IMAGING SYSTEM - Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels. | 07-10-2014 |
| 20140191800 | MULTIPLE WINDING TRANSFORMER COUPLED AMPLIFIER - An integrated circuit includes a radio frequency (RF) amplifier having a trifilar transformer coupled to a gain device in two negative feedback paths. The trifilar transformer includes a first winding, a second winding and a third winding, a first dielectric core is disposed between the first winding and the second winding, and a second dielectric core is disposed between the second winding and the third winding. A first winding ratio between the first winding and the second winding combined with a second winding ratio between the second winding and the third winding affects a total gain of the RF amplifier. In a specific embodiment, the gain device is a transistor, the first winding is coupled to a base of the transistor, the second winding is coupled to a collector of the transistor, and the third winding is coupled to an emitter of the transistor. | 07-10-2014 |
| 20140191783 | PIN DRIVER CIRCUIT WITH IMPROVED SWING FIDELITY - A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output. | 07-10-2014 |
| 20140190543 | WAFER SCALE THERMOELECTRIC ENERGY HARVESTER - An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements. | 07-10-2014 |
| 20140176571 | BLOCK-BASED SIGNAL PROCESSING - Signal flows for data-processing applications may be implemented so as to enable each processing node in the flow when it contains a sufficient amount of input data at its input buffer. In various embodiments, such signal flows can be graphically defined in a GUI tool which, thereafter, auto-generates suitable code for implementing the signal flow. | 06-26-2014 |
| 20140176356 | APPARATUS AND METHODS FOR VOLTAGE COMPARISON - Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator. | 06-26-2014 |
| 20140176232 | CARTESIAN FEEDBACK LOOP TRANSMITTER WITH IMPROVED LOOP FILTER - A filter may include multiple circuit sub-systems, where one circuit sub-system may have an output connected to an input of another circuit sub-system. Each circuit sub-system may include an amplifier with an output connected to the output of the circuit sub-system. Each circuit sub-system may include a first network connecting an input of the circuit sub-system to a first reference input of the amplifier, and a second network connecting the output of the amplifier to the first reference input of the amplifier. The filter may include a link network connecting the output of one circuit sub-system to an input of another circuit sub-system. | 06-26-2014 |
| 20140175600 | VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer. | 06-26-2014 |
| 20140175524 | VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer. | 06-26-2014 |
| 20140167106 | INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME - Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures. | 06-19-2014 |
| 20140167105 | DEVICES FOR MONOLITHIC DATA CONVERSION INTERFACE PROTECTION AND METHODS OF FORMING THE SAME - Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation. | 06-19-2014 |
| 20140167104 | INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME - Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures. | 06-19-2014 |
| 20140159813 | ENHANCED TRANSCONDUCTANCE CIRCUIT - A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs. | 06-12-2014 |
| 20140159805 | SUB-GATE DELAY ADJUSTMENT USING DIGITAL LOCKED-LOOP - A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal. | 06-12-2014 |
| 20140159226 | COMPACT SENSOR MODULE - Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die. | 06-12-2014 |
| 20140153834 | HOUGH TRANSFORM FOR CIRCLES - The Hough transform for circles can be implemented in a manner that avoids random access to the Hough accumulator array by successively identifying center candidates in each line of the image based on edge pixels in corresponding lines voting on the line of interest. | 06-05-2014 |
| 20140152680 | SYSTEM AND METHOD FOR EFFICIENT RESOURCE MANAGEMENT OF A SIGNAL FLOW PROGRAMMED DIGITAL SIGNAL PROCESSOR CODE - A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence. | 06-05-2014 |
| 20140152480 | ENHANCED SECOND ORDER NOISE SHAPED SEGMENTATION AND DYNAMIC ELEMENT MATCHING TECHNIQUE - A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements. | 06-05-2014 |
| 20140152280 | APPARATUS AND METHOD FOR DISTRIBUTING POWER-UP POWER DISSIPATION - A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods. | 06-05-2014 |
| 20140151557 | PHOTONIC SENSOR AND A METHOD OF MANUFACTURING SUCH A SENSOR - A photonic sensor, comprising: a platform, a temperature sensor on the platform; and a structure formed on or as part of the platform. | 06-05-2014 |
| 20140145867 | SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS - Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node. | 05-29-2014 |
| 20140145785 | APPARATUS AND METHODS FOR EQUALIZATION - Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal. | 05-29-2014 |
| 20140145781 | APPARATUS AND METHODS FOR ULTRASOUND TRANSMIT SWITCHING - Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit. | 05-29-2014 |
| 20140144240 | APPARATUS AND METHODS FOR ULTRASOUND PROBES - Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal's voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal. | 05-29-2014 |
| 20140138735 | JUNCTION-ISOLATED BLOCKING VOLTAGE DEVICES WITH INTEGRATED PROTECTION STRUCTURES AND METHODS OF FORMING THE SAME - Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well. | 05-22-2014 |
| 20140137069 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
| 20140137068 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
| 20140137067 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
| 20140133055 | ACTIVE DETECTION AND PROTECTION OF SENSITIVE CIRCUITS AGAINST TRANSIENT ELECTRICAL STRESS EVENTS - Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit can generate a first activation signal in response to a transient electrical stress event across a first node and a second node. A blocking circuit is configured to bias the base of a first driver bipolar transistor to slow down discharge of accumulated base charge of a first driver bipolar transistor, which permits the first driver bipolar transistor to remain activated for a longer period of time than had the base of the first driver bipolar transistor been biased to the same voltage as the emitter of the first bipolar transistor. Shut-off circuitry can be included in some embodiments to prevent a discharge circuit from activating during normal operating conditions. | 05-15-2014 |
| 20140132325 | CONTROL CIRCUIT FOR USE WITH A FOUR TERMINAL SENSOR, AND MEASUREMENT SYSTEM INCLUDING SUCH A CONTROL CIRCUIT - A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1. | 05-15-2014 |
| 20140131850 | MICROCHIP WITH BLOCKING APPARATUS AND METHOD OF FABRICATING MICROCHIP - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 05-15-2014 |
| 20140125407 | BANDWIDTH LIMITING FOR AMPLIFIERS - An apparatus for limiting the bandwidth of an amplifier provides for the design of an input impedance, a feedback impedance, and a load impedance such that the load impedance is proportional to the sum of the input impedance and feedback impedance. A sampling circuit has a load impedance including a resistor and capacitor in series to reduce the effective amplifier transconductance, which decreases bandwidth without increasing noise density or making this circuit more difficult to drive than a conventional circuit. | 05-08-2014 |
| 20140119082 | ISOLATED DIGITAL TRANSMISSION WITH IMPROVED EMI IMMUNITY - Embodiments of the present invention may provide a circuit. The circuit may include a primary side, a secondary side, and an isolated energy transfer device electrically isolating the primary side and the secondary side. The primary side may include a first energy storage device coupled to a power source, a control system coupled to the first energy storage device for power, a second energy storage device, and a coupling system, coupled to the control system, to selectively couple the second energy storage device to the power source in a first phase and to selectively couple the second energy storage device to the primary side of the isolated energy transfer device during a second phase. | 05-01-2014 |
| 20140117473 | PACKAGES AND METHODS FOR PACKAGING - A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing. | 05-01-2014 |
| 20140115873 | MICRO-ELECTRO-MECHANICAL SWITCH BEAM CONSTRUCTION WITH MINIMIZED BEAM DISTORTION AND METHOD FOR CONSTRUCTING - Disclosed is a micro-electro-mechanical switch, including a substrate having a gate connection, a source connection, a drain connection and a switch structure, coupled to the substrate. The switch structure includes a beam member, an anchor and a hinge. The beam member having a length sufficient to overhang both the gate connection and the drain connection. The anchor coupling the switch structure to the substrate, the anchor having a width. The hinge coupling the beam member to the anchor at a respective position along the anchor's length, the hinge to flex in response to a charge differential established between the gate and the beam member. The switch structure having gaps between the substrate and the anchor in regions proximate to the hinges. | 05-01-2014 |
| 20140115278 | MEMORY ARCHITECTURE - According to one example embodiment, an arbiter is disclosed to mediate memory access requests from a plurality of processing elements. If two or more processing elements try to access data within the same word in a single memory bank, the arbiter permits some or all of the processing elements to access the word. If two or more processing elements try to access different data words in the same memory bank, the lowest-ordered processing element is granted access and the others are stalled. | 04-24-2014 |
| 20140115224 | MEMORY INTERCONNECT NETWORK ARCHITECTURE FOR VECTOR PROCESSOR - The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network. | 04-24-2014 |
| 20140111192 | MAGNETIC FIELD DIRECTION DETECTOR - A magnetic field direction detector for detecting whether a magnetic flux has a component of field from a first side or a second side of a detection axis; the magnetic field direction detector comprising: a first magneto-resistive sensor; and a perturbation generator; wherein the perturbation generator causes an external magnetic field to be perturbed so as to cause the apparent direction of flux to change by an angle θ | 04-24-2014 |
| 20140110825 | Compound Semiconductor Lateral PNP Bipolar Transistors - Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes. | 04-24-2014 |
| 20140105264 | SYSTEM AND METHOD TO CALIBRATE THE FREQUENCY RESPONSE OF AN ELECTRONIC FILTER - A system and method provide for calibrating the frequency response of an electronic filter. The system and method include a radio transmitter with both in-phase and quadrature baseband paths. Each baseband path includes a numerically controlled oscillator (“NCO”), a digital signal path, a digital-to-analog converter (“DAC”), and an analog filter. A low frequency tone is applied from the NCO from one of the baseband path, while a high frequency tone is applied from the NCO in the other baseband path. An analog peak detector at output determines which analog filter has the largest amplitude at the output. The peak detector offset between the two analog filters is offset by stimulating the in-phase and quadrature baseband paths with the respective NCOs to find an amplitude difference between the output signals from the NCOs that makes the output of the analog filters the same. Calibration is then performed on the corner frequency and filter peaking through respective stimulation of the in-phase and quadrature baseband paths. The system and method is advantageous as it allows for very accurate calibration of both the filter corner frequency and peaking during a standard transmission operating mode with little additional hardware required. | 04-17-2014 |
| 20140104000 | FEED-FORWARD CIRCUIT TO PREVENT PHASE INVERSION - An amplifier includes a bootstrap circuit for improving a linearity of the amplifier and a feed-forward circuit for modifying a voltage of the bootstrap circuit in response to a change in an input signal. Modifying the voltage using the feed-forward circuit prevents a phase-inversion condition of the amplifier. | 04-17-2014 |
| 20140103464 | Microphone System with Integrated Passive Device Die - A microphone system has a package forming an interior chamber, and a MEMS microphone secured within the interior chamber. The package forms an aperture for permitting acoustic access to the interior of the chamber and thus, the MEMS microphone. The system also has two dies; namely, the system has a primary circuit die within the interior chamber, and an integrated passive device die electrically connected with the primary circuit die. The primary circuit die is electrically connected with the MEMS microphone and has at least one active circuit element. | 04-17-2014 |
| 20140102195 | Electrode Arrangements for Quadrature Suppression in Inertial Sensors - A substrate for an inertial sensor system includes a plurality of electrode arrangements, each electrode arrangement including an acceleration sensor electrode and a pair of quadrature adjusting electrodes on opposite sides of the acceleration sensor electrode, where each electrode arrangement is capable of being overlaid by a corresponding plate of a shuttle such that the plate completely overlays the acceleration sensor electrode and partially overlays the pair of quadrature adjusting electrodes on opposite sides of the acceleration sensor electrode such that capacitive coupling between the plate and each of the quadrature adjusting electrodes is dependent upon the rotational position of the at least one shuttle while capacitive coupling between the plate and the acceleration sensor electrodes is substantially independent of the rotational position of the at least one shuttle. | 04-17-2014 |
| 20140101477 | POWER SWITCHING IN A TWO-WIRE CONDUCTOR SYSTEM - In an example embodiment, a power switching circuit of an automobile audio bus (A | 04-10-2014 |
