ADVANTEST (SINGAPORE) PTE LTD Patent applications |
Patent application number | Title | Published |
20150193378 | ADAPTIVE VALUE CAPTURE FOR PROCESS MONITORING - A method for analyzing test results. The method includes selecting a first subset of tests from a plurality of tests. Test results are gathered from the plurality of tests in real-time. A first statistical analysis is performed on test results from the first subset of tests. At least one process control rule is initiated as determined by results of the first statistical analysis performed on the test results from the first subset of tests. | 07-09-2015 |
20150180618 | ONLINE DESIGN VALIDATION FOR ELECTRONIC DEVICES - A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design automation tool (EDA). The generated design test pattern and command/instruction is sent directly to an automated test equipment apparatus (ATE) over a UNIX or scripting language based, and/or a network based, communication pipeline. The ATE converts the sent design test pattern to an instance of the test pattern directly executable by the ATE. The ATE apparatus inputs test signals to each of the multiple electronic DUTs based on the executable test pattern. The ATE apparatus then receives, from each of the multiple electronic DUTs, a test result based on the input test signals. The ATE returns the received test result, and a report of an action responsive to the command/instruction to the EDA tool, which may then process the test results and report. | 06-25-2015 |
20150134287 | METHOD AND APPARATUS FOR IMPROVING DIFFERENTIAL DIRECT CURRENT (DC) MEASUREMENT ACCURACY - A method of error correction in automated test equipment (ATE) is presented. The method comprises calibrating the ATE using a calibration board, wherein the calibration board comprises a reference voltage. The calibrating comprises: (a) measuring the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) recording a series of differential voltage measurement values obtained from the measuring in a calibration module; and (c) calculating a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values. The method further comprises obtaining a measured voltage value for a DUT connected to a first channel in the ATE, wherein the first channel is one of the plurality of channels. Finally, the method comprises correcting the measured voltage value using a respective correction factor for said first channel. | 05-14-2015 |
20150084681 | Variable Attenuator - A variable attenuator comprises a series resistance, and an adjustable shunt resistance, wherein the adjustable shunt resistance comprises a series circuit of a fixed resistor and a semiconductor element having an adjustable resistance. | 03-26-2015 |
20150039927 | Device Under Test Data Processing Techniques - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information. | 02-05-2015 |
20150015284 | TRANSMIT/RECEIVE UNIT, AND METHODS AND APPARATUS FOR TRANSMITTING SIGNALS BETWEEN TRANSMIT/RECEIVE UNITS - In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed. | 01-15-2015 |
20140336974 | Reconfigurable Automatic Test Circuit Techniques - A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device. | 11-13-2014 |
20140336958 | Techniques for Determining a Fault Probability of a Location on a Chip - A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination. | 11-13-2014 |
20140002122 | Methods, Apparatus, and Systems for Contacting Semiconductor Dies that are Electrically Coupled to Test Access Interface Positioned in Scribe Lines of a Wafer | 01-02-2014 |
20130311844 | Test Card for Testing One or More Devices Under Test and Tester - A test card for testing one or more devices under test includes a plurality of test resources configured to communicate with the one or more devices under test. The test card further includes a matching circuit configured to receive a test sequence of at least two matching instructions followed by one or more processing instructions. The matching instructions define a group of resources which are to operate in accordance with the processing instructions. The matching circuit is configured to determine based on the at least two matching instructions whether a given test resource out of a plurality of test resources belongs to the group or not and to forward the processing instructions to the given test resource if the given test resource belongs to the group and to not forward the processing instructions to the given test resource if the given test resource does not belong to the group. | 11-21-2013 |
20130285690 | STIFFENER PLATE FOR A PROBECARD AND METHOD - A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include a main body and a plurality of mounting points, wherein at least one of the mounting points is flexibly connected to the main body by one or more laterally extending beams that has a section modulus normal to the lateral direction significantly greater than in the lateral direction. The stiffener assembly allows for differential thermal expansion of various components of the microelectronic contactor assembly while minimizing accompanying dimensional distortion that could interfere with contacting the terminals of semiconductor devices. | 10-31-2013 |
20130186746 | Method and Apparatus for Producing Controlled Stresses and Stress Gradients in Sputtered Films - An enhanced sputtered film processing system and associated method comprises one or more sputter deposition sources each having a sputtering target surface and one or more side shields extending therefrom, to increase the relative collimation of the sputter deposited material, such as about the periphery of the sputtering target surface, toward workpiece substrates. One or more substrates are provided, wherein the substrates have a front surface and an opposing back surface, and may have one or more previously applied layers, such as an adhesion or release layer. The substrates and the deposition targets are controllably moved with respect to each other. The relatively collimated portion of the material sputtered from the sputtering target surface travels beyond the side shields and is deposited on the front surface of the substrates. The increase in relative collimation results in deposited films with desirable properties including but not limited to high levels of both readily controllable compressive stress and mechanical integrity without the use of ion bombardment. | 07-25-2013 |
20130138383 | SOLUTION FOR FULL SPEED, PARALLEL DUT TESTING - A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT. | 05-30-2013 |
20130135002 | TEST ELECTRONICS TO DEVICE UNDER TEST INTERFACES, AND METHODS AND APPARATUS USING SAME - In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes. | 05-30-2013 |