Advanced Inquiry Systems, Inc. Patent applications |
Patent application number | Title | Published |
20140347086 | METHOD AND APPARATUS FOR MULTI-PLANAR EDGE-EXTENDED WAFER TRANSLATOR - An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs. | 11-27-2014 |
20140197858 | MAINTAINING A WAFER/WAFER TRANSLATOR PAIR IN AN ATTACHED STATE FREE OF A GASKET DISPOSED - A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means. | 07-17-2014 |
20140179031 | DESIGNED ASPERITY CONTACTORS, INCLUDING NANOSPIKES, FOR SEMICONDUCTOR TEST USING A PACKAGE, AND ASSOCIATED SYSTEMS AND METHODS - Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package. | 06-26-2014 |
20140176174 | DESIGNED ASPERITY CONTACTORS, INCLUDING NANOSPIKES FOR SEMICONDUCTOR TEST, AND ASSOCIATED SYSTEMS AND METHODS - Nano spike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a translator having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer-side sites are carried by the translator at the wafer side of the translator. The nanospikes can be attached to nanospike sites on a wafer side of a translator. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, the nanospikes can be formed by sputtering over a metal carrier with a photoresist mask. In particular embodiments, the nanospikes have generally conical cross-section. | 06-26-2014 |
20130337587 | METHODS OF ADDING PADS AND ONE OR MORE INTERCONNECT LAYERS TO THE PASSIVATED TOPSIDE OF A WAFER INCLUDING CONNECTIONS TO AT LEAST A PORTION OF THE INTEGRATED CIRCUIT PADS THEREON - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system. | 12-19-2013 |
20130314115 | WAFER TESTING SYSTEM AND ASSOCIATED METHODS OF USE AND MANUFACTURE - A wafer testing system and associated methods of use an manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways. | 11-28-2013 |
20130265071 | TRANSLATORS COUPLEABLE TO OPPOSING SURFACES OF MICROELECTRONIC SUBSTRATES FOR TESTING, AND ASSOCIATED SYSTEMS AND METHODS - Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces. The arrangement further includes a first translator releasably connected to the substrate and positioned in a first region extending outwardly from the first surface, the first translator including first electrical signal paths that access the vias from the first surface, and a second translator releasably connected to the substrate simultaneously with the first translator, the second translator being positioned in a second region extending outwardly from the second surface, the second translator including second electrical signal paths that access the vias from the second surface. | 10-10-2013 |
20130187675 | MAINTAINING A WAFER/WAFER TRANSLATOR PAIR IN AN ATTACHED STATE FREE OF A GASKET DIPOSED - A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means. | 07-25-2013 |
20130021052 | Wafer prober integrated with full-wafer contacter - Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer. | 01-24-2013 |
20120156811 | METHODS OF ADDING PADS AND ONE OR MORE INTERCONNECT LAYERS TO THE PASSIVATED TOPSIDE OF A WAFER INCLUDING CONNECTIONS TO AT LEAST A PORTION OF THE INTEGRATED CIRCUIT PADS THEREON - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system. | 06-21-2012 |
20120149134 | METHODS AND APPARATUS FOR THINNING, TESTING AND SINGULATING A SEMICONDUCTOR WAFER - A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated. | 06-14-2012 |
20120139575 | Method and apparatus for multi-planar edge-extended wafer translator - An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs. | 06-07-2012 |
20120074976 | WAFER TESTING SYSTEMS AND ASSOCIATED METHODS OF USE AND MANUFACTURE - A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways. | 03-29-2012 |