ADESTO TECHNOLOGIES CORPORATION Patent applications |
Patent application number | Title | Published |
20140299832 | NONVOLATILE MEMORY ELEMENTS HAVING CONDUCTIVE STRUCTURES WITH SEMIMETALS AND/OR SEMICONDUCTORS - A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields. | 10-09-2014 |
20140254238 | SENSING DATA IN RESISTIVE SWITCHING MEMORY DEVICES - Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction. | 09-11-2014 |
20140246641 | Resistive Switching Devices Having a Switching Layer And An Intermediate Electrode Layer and Methods of Formation Thereof - In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node. | 09-04-2014 |
20140173154 | NETWORK INTERFACE WITH LOGGING - Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC. | 06-19-2014 |
20140149639 | CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY - Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device. | 05-29-2014 |
20140089560 | MEMORY DEVICES AND METHODS HAVING WRITE DATA PERMUTATION FOR CELL WEAR REDUCTION - A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements. | 03-27-2014 |
20140084232 | Resistive Switching Memory - In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line. | 03-27-2014 |
20140071733 | MULTI-PORT MEMORY DEVICES AND METHODS HAVING PROGRAMMABLE IMPEDANCE ELEMENTS - A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports. | 03-13-2014 |
20140063902 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block. | 03-06-2014 |
20140063901 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements. | 03-06-2014 |
20140003125 | Resistive Devices and Methods of Operation Thereof | 01-02-2014 |
20130344649 | MEMORY ELEMENTS AND METHODS WITH IMPROVED DATA RETENTION AND/OR ENDURANCE - A method can include forming at least one memory layer over a first electrode, the memory layer having at least one element formed therein that oxidizes in the presence of an electric field to form conductive paths within the memory layer; and forming an inhibiting layer within the memory layer that increases an oxidation energy for the at least one element, as compared to the oxidation energy for the at least one element in the memory layer without the inhibiting layer. | 12-26-2013 |
20130301337 | Resistive Devices and Methods of Operation Thereof - In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse. | 11-14-2013 |
20130258753 | MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS - A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation. | 10-03-2013 |
20130214234 | Resistive Switching Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte. | 08-22-2013 |