Patent application number | Description | Published |
20090051010 | IC package sacrificial structures for crack propagation confinement - Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area. | 02-26-2009 |
20090212443 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE HAVING CONFIGURABLE BOND PADS - Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate. | 08-27-2009 |
20090267222 | Low Voltage Drop and High Thermal Performance Ball Grid Array Package - An integrated circuit (IC) package is provided. The IC package includes a substantially planar substrate having a plurality of contact pads on a first surface electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate, an IC die having a first surface mounted to the first surface of the substrate, and a heat sink assembly coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. The IC die is mounted to the first surface of the substrate in a flip chip orientation. | 10-29-2009 |
20100117245 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE HAVING CONFIGURABLE BOND PADS - Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate. | 05-13-2010 |
20120319255 | Thermal Enhanced High Density Flip Chip Package - Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers. | 12-20-2012 |
20130084816 | Wideband Power Efficient High Transmission Power Radio Frequency (RF) Transmitter - Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies. | 04-04-2013 |
20130134596 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 05-30-2013 |
20130235953 | Wideband Power Efficient High Transmission Power Radio Frequency (RF) Transmitter - Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated, In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies. | 09-12-2013 |
20130314120 | WAFER LEVEL PACKAGE RESISTANCE MONITOR SCHEME - An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold. | 11-28-2013 |
20140084462 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 03-27-2014 |
20140087553 | Fabricating a Wafer Level Semiconductor Package Having a Pre-formed Dielectric Layer - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 03-27-2014 |
Patent application number | Description | Published |
20080240655 | Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding - A method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a tuned top clad is described herein. In one example, a dopant concentration within a top cladding material is between 3-6% (wt.). Given a tuned top cladding composition, a width of the waveguide core is pre-selected such that birefringence is minimized, i.e., a zero, or near zero. The desirable width of the waveguide core is determined by calculating the distribution of stress in the top cladding over a change in temperature. From this distribution of stress, a relationship between the polarization dependent wavelength and variable widths of the waveguide in the arrayed waveguide grating are determined. This relationship determines a zero value, or near zero value, of polarization dependent wavelength for a given range of waveguide widths. Accordingly, the width of the waveguide may be selected such that the polarization dependent wavelength is minimized. | 10-02-2008 |
20090009444 | MEMS DEVICES HAVING IMPROVED UNIFORMITY AND METHODS FOR MAKING THEM - Disclosed is a microelectromechanical system (MEMS) device and method of manufacturing the same. In one aspect, MEMS such as an interferometric modulator include one or more elongated interior posts and support rails supporting a deformable reflective layer, where the elongated interior posts are entirely within an interferometric cavity and aligned parallel with the support rails. In another aspect, the interferometric modulator includes one or more elongated etch release holes formed in the deformable reflective layer and aligned parallel with channels formed in the deformable reflective layer defining parallel strips of the deformable reflective layer. | 01-08-2009 |
20090257105 | DEVICE HAVING THIN BLACK MASK AND METHOD OF FABRICATING THE SAME - A thin black mask is created using a single mask process. A dielectric layer is deposited over a substrate. An absorber layer is deposited over the dielectric layer and a reflector layer is deposited over the absorber layer. The absorber layer and the reflector layer are patterned using a single mask process. | 10-15-2009 |
20100079847 | MULTI-THICKNESS LAYERS FOR MEMS AND MASK-SAVING SEQUENCE FOR SAME - In various embodiments described herein, methods for forming a plurality of microelectromechanical systems (MEMS) devices on a substrate are described. The MEMS devices comprise x number of different sacrificial or mechanical structures with x number of different sacrificial structure thicknesses or mechanical structure stiffnesses and wherein the x number of sacrificial or mechanical structures are formed by x-1 depositions and x-1 masks. | 04-01-2010 |
20100202039 | MEMS DEVICES HAVING SUPPORT STRUCTURES WITH SUBSTANTIALLY VERTICAL SIDEWALLS AND METHODS FOR FABRICATING THE SAME - Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the portions of the support structures underlying the movable layer include a convex sidewall. In further embodiments, a portion of the support structure extends through an aperture in the movable layer and over at least a portion of the movable layer. | 08-12-2010 |
20100238572 | DISPLAY DEVICE WITH OPENINGS BETWEEN SUB-PIXELS AND METHOD OF MAKING SAME - An electromechanical systems device includes a plurality of supports disposed over a substrate and a deformable reflective layer disposed over the plurality of supports. The deformable reflective layer includes a plurality of substantially parallel columns extending in a first direction. Each column has one or more slots extending in a second direction generally perpendicular to the first direction. The slots can be created at boundary edges of sub-portions of the columns so as to partially mechanically separate the sub-portions without electrically disconnecting them. A method of fabricating an electromechanical device includes depositing an electrically conductive deformable reflective layer over a substrate, removing one or more portions of the deformable layer to form a plurality of electrically isolated columns, and forming at least one crosswise slot in at least one of the columns. | 09-23-2010 |
20100265563 | ELECTROMECHANICAL DEVICE CONFIGURED TO MINIMIZE STRESS-RELATED DEFORMATION AND METHODS FOR FABRICATING SAME - Embodiments of MEMS devices include a movable layer supported by overlying support structures, and may also include underlying support structures. In one embodiment, the residual stresses within the overlying support structures and the movable layer are substantially equal. In another embodiment, the residual stresses within the overlying support structures and the underlying support structures are substantially equal. In certain embodiments, substantially equal residual stresses are be obtained through the use of layers made from the same materials having the same thicknesses. In further embodiments, substantially equal residual stresses are obtained through the use of support structures and/or movable layers which are mirror images of one another. | 10-21-2010 |
20110169724 | INTERFEROMETRIC PIXEL WITH PATTERNED MECHANICAL LAYER - Interferometric modulators and methods of making the same are disclosed. In one embodiment, an interferometric display includes a sub-pixel having a membrane layer with a void formed therein. The void can be configured to increase the flexibility of the membrane layer. The sub-pixel can further include an optical mask configured to hide the void from a viewer. In another embodiment, an interferometric display can include at least two movable reflectors wherein each movable reflector has a different stiffness but each movable reflector has substantially the same effective coefficient of thermal expansion. | 07-14-2011 |
20110235155 | MECHANICAL LAYER AND METHODS OF SHAPING THE SAME - A method of shaping a mechanical layer is disclosed. In one embodiment, the method comprises depositing a support layer, a sacrificial layer and a mechanical layer over a substrate, and forming a support post from the support layer. A kink is formed adjacent to the support post in the mechanical layer. The kink comprises a rising edge and a falling edge, and the kink can be configured to control the shaping and curvature of the mechanical layer upon removal of the sacrificial layer. | 09-29-2011 |
20110249315 | MECHANICAL LAYER AND METHODS OF FORMING THE SAME - This disclosure provides mechanical layers and methods of forming the same. In one aspect, an electromechanical systems device includes a substrate and a mechanical layer having an actuated position and a relaxed position. The mechanical layer is spaced from the substrate to define a collapsible gap. The gap is in a collapsed condition when the mechanical layer is in the actuated position and in a non-collapsed condition when the mechanical layer is in the relaxed position. The mechanical layer includes a reflective layer, a conductive layer, and a supporting layer. The supporting layer is positioned between the reflective layer and the conductive layer and is configured to support the mechanical layer. | 10-13-2011 |
20120194496 | APPARATUS AND METHOD FOR SUPPORTING A MECHANICAL LAYER - This disclosure provides systems, methods and apparatuses for supporting a mechanical layer. In one aspect, an electromechanical systems device includes a substrate, a mechanical layer, and a post positioned on the substrate for supporting the mechanical layer. The mechanical layer is spaced from the substrate and defines one side of a gap between the mechanical layer and the substrate, and the mechanical layer is movable in the gap between an actuated position and a relaxed position. The post includes a wing portion in contact with a portion of the mechanical layer, the wing portion positioned between the gap and the mechanical layer. The wing portion can include a plurality of layers configured to control the curvature of the mechanical layer. | 08-02-2012 |
20120194897 | BACKSIDE PATTERNING TO FORM SUPPORT POSTS IN AN ELECTROMECHANICAL DEVICE - This disclosure provides systems, methods and apparatus for backside patterning of structures in electromechanical devices. In one aspect, backside patterning of supports in an electromechanical device allows the size of the supports to be reduced, increasing the active region of the electromechanical device. In electromechanical devices having black masks, the black masks may include a partially transmissive aperture aligned with the supports which enable backside patterning of the support through the black mask. The black mask may include an interferometric black mask in which an upper reflective layer has been patterned to form an aperture extending therethrough. | 08-02-2012 |
20120242638 | DIELECTRIC SPACER FOR DISPLAY DEVICES - This disclosure provides systems, methods and apparatus for forming spacers on a substrate and building an electromechanical device over the spacers and the substrate. In one aspect, a raised anchor area is formed over the spacer by adding layers that result in a high point above the substrate. The high point can protect the movable sections of the MEMS device from contact with a backplate. | 09-27-2012 |
20120248478 | PIXEL VIA AND METHODS OF FORMING THE SAME - This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, depositing a mechanical layer over the optical stack, and anchoring the mechanical layer over the optical stack at each corner of each pixel. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via in the dielectric layer electrically connecting the stationary electrode to the black mask, the via disposed at a corner of the first pixel, offset from where the mechanical layer is anchored over the optical stack in an optically non-active area of the first pixel. | 10-04-2012 |
20120249558 | PIXEL VIA AND METHODS OF FORMING THE SAME - This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners and along at least one edge region of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, and depositing a mechanical layer over the optical stack. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via disposed in the dielectric layer and electrically connecting the stationary electrode to the black mask, the via disposed in a position along an edge of the first pixel, spaced offset from the edge of the first pixel in a direction towards the center of the first pixel. | 10-04-2012 |
20120268430 | MECHANICAL LAYER AND METHODS OF MAKING THE SAME - This disclosure provides mechanical layers and methods of forming the same. In one aspect, a method of forming a pixel includes depositing a black mask on a substrate, depositing an optical stack over the black mask, and forming a mechanical layer over the optical stack. The black mask is disposed along at least a portion of a side of the pixel, and the mechanical layer defines a cavity between the mechanical layer and the optical stack. The mechanical layer includes a reflective layer, a dielectric layer, and a cap layer, and the dielectric layer is disposed between the reflective layer and the cap layer. The method further includes forming a notch in the dielectric layer of the mechanical layer along the side of the pixel so as to reduce the overlap of the dielectric layer with the black mask along the side of the pixel. | 10-25-2012 |
20120287138 | ELECTROMECHANICAL DEVICE CONFIGURED TO MINIMIZE STRESS-RELATED DEFORMATION AND METHODS FOR FABRICATING SAME - Embodiments of MEMS devices include a movable layer supported by overlying support structures, and may also include underlying support structures. In one embodiment, the residual stresses within the overlying support structures and the movable layer are substantially equal. In another embodiment, the residual stresses within the overlying support structures and the underlying support structures are substantially equal. In certain embodiments, substantially equal residual stresses are be obtained through the use of layers made from the same materials having the same thicknesses. In further embodiments, substantially equal residual stresses are obtained through the use of support structures and/or movable layers which are mirror images of one another. | 11-15-2012 |
20130057558 | MECHANICAL LAYER AND METHODS OF MAKING THE SAME - This disclosure provides systems, methods and apparatus for controlling a mechanical layer. In one aspect, an electromechanical systems device includes a substrate and a mechanical layer positioned over the substrate to define a gap. The mechanical layer is movable in the gap between an actuated position and a relaxed position, and includes a mirror layer, a cap layer, and a dielectric layer disposed between the mirror layer and the cap layer. The mechanical layer is configured to have a curvature in a direction away from the substrate when the mechanical layer is in the relaxed position. In some implementations, the mechanical layer can be formed to have a positive stress gradient directed toward the substrate that can direct the curvature of the mechanical layer upward when the sacrificial layer is removed. | 03-07-2013 |
20130088498 | ELECTROMECHANICAL SYSTEMS DEVICE WITH NON-UNIFORM GAP UNDER MOVABLE ELEMENT - Systems, methods and apparatus are provided for electromechanical systems devices having a non-uniform gap under a mechanical layer. An electromechanical systems device includes a movable element supported at its edges over a substrate by at least two support structures. The movable element can be spaced from the substrate by a gap having two or more different heights in two or more corresponding distinct regions. The gap has a first height in a first region below the gap, such as an active area of the device, and a second height in a second region adjacent the support structure. In an interferometric modulator implementation, the second region can be encompasses within an anchor region with a black mask. | 04-11-2013 |
20130100145 | ELECTROMECHANICAL SYSTEMS DEVICE - This disclosure provides systems, methods, and apparatus for EMS devices. In one aspect, an EMS device includes at least one movable layer configured to move relative to one or more electrodes. The at least one movable layer can include a first conductive layer, a second conductive layer, and a non-conductive layer disposed between the first conductive layer and the second conductive layer. In some implementations, the movable layer can include at least one conductive via electrically connecting the first conductive layer and the second conductive layer through the non-conductive layer. | 04-25-2013 |
20130113810 | SIDEWALL SPACERS ALONG CONDUCTIVE LINES - Systems, methods and apparatus are provided for electromechanical systems devices having a sidewall spacer along at least one sidewall of a conductive line. An electromechanical systems device can include a sidewall spacer along at least one sidewall of a conductive line under a movable layer. The sidewall spacer can be sloped such that the sidewall spacer has a decreasing width away from a substrate under the movable layer. The conductive line can be configured to route an electrical signal to the electromechanical systems device. In some implementations, a black mask structure of an electromechanical systems device can include the conductive line. | 05-09-2013 |
20140071139 | IMOD PIXEL ARCHITECTURE FOR IMPROVED FILL FACTOR, FRAME RATE AND STICTION PERFORMANCE - Pixels that include display elements that are configured with different structural dimensions corresponding to the color of light they provide are disclosed. In one implementation, a display device includes an array having a plurality of electromechanical pixels disposed on a substrate, each pixel including at least a first display element and a second display element. Each of the first and second display elements interferometrically modulating light by moving a reflective element between a relaxed position spaced apart from the substrate to an actuated position further away from the substrate than the relaxed position by applying a voltage across the reflective element and a stationary electrode. The stationary electrode of each display element is sized to provide actuation of the movable reflective element using the same actuation voltage even though the electrical gap through which the reflective element moves is different within a pixel. | 03-13-2014 |
20140098109 | MOVABLE LAYER DESIGN FOR STRESS CONTROL AND STIFFNESS REDUCTION - Systems, methods and apparatuses reduce stress and/or reduce stiffness in a movable layer of an electromechanical systems (EMS) device. Stress or stiffness can be reduced by including one or more compressive stress layers to compensate for the tensile stress exhibited by other layers of the movable layer. The movable layer can include a dielectric core with a first tensile stress layer and a first compressive stress layer on a first side of the dielectric core, and a second tensile stress layer and a second compressive stress layer on a second side of the dielectric core. | 04-10-2014 |
20140168223 | PIXEL ACTUATION VOLTAGE TUNING - This disclosure provides systems, methods and apparatus for electromechanical systems displays. In one aspect, the display can include a plurality of electromechanical display elements including a first set of electromechanical display elements and a second set of electromechanical display elements. Each electromechanical display element can include a common electrode and a segment electrode. Each of the segment electrodes of the first set of electromechanical display elements can have a first area located under the common electrodes of the first set. Each of the segment electrodes of the second set of electromechanical display elements can have a second area smaller than the first area located under the common electrodes of the second set. In some implementations, an actuation voltage of each electromechanical display element of the first set is approximately the same as an actuation voltage of each electromechanical display element of the second set. | 06-19-2014 |
20140192060 | CONTROLLING MOVABLE LAYER SHAPE FOR ELECTROMECHANICAL SYSTEMS DEVICES - Systems, methods and apparatus are provided for controlling launch effects of movable layers in electromechanical systems (EMS) devices. First and second EMS devices with first and second step creating layers are positioned over a substrate and spaced, by different gaps, from the movable layers of the EMS devices. The movable layers of the first and second EMS devices include steps having different heights and/or different edge spacing from the center of an anchoring region of each EMS device. The different steps can provide different launch effects for different EMS devices, and if the same thickness of sacrificial material is used for the different devices, the different launch effects can be responsible for different gap heights in the unbiased conditions. | 07-10-2014 |
20140210836 | LAYER FOR REDUCED CHARGE MIGRATION BETWEEN MEMS LAYERS - This disclosure provides systems, methods and apparatus for reducing image artifacts that arise when a display is exposed to sunlight over time. Various implementations disclosed herein can be implemented to prevent charge injection from inducing a negative offset voltage shift for display elements in the display. In one aspect, a buffer layer is applied to block electrons from being photoelectrically ejected from a movable reflective layer of a display element and into a stationary optical stack of the display element. | 07-31-2014 |
Patent application number | Description | Published |
20090289348 | SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION - A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces. | 11-26-2009 |
20100080282 | RE-ADAPTION OF EQUALIZER PARAMETER TO CENTER A SAMPLE POINT IN A BAUD-RATE CLOCK AND DATA RECOVERY RECEIVER - An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference. | 04-01-2010 |
20110006395 | HYBRID BUMP CAPACITOR - A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs. | 01-13-2011 |
20110142120 | FLOATING-TAP DECISION FEEDBACK EQUALIZER FOR COMMUNICATION CHANNELS WITH SEVERE REFLECTION - An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively. | 06-16-2011 |
20120257652 | ADJUSTING SAMPLING PHASE IN A BAUD-RATE CDR USING TIMING SKEW - In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase. | 10-11-2012 |
20120262238 | PVT CONSISTENT PLL INCORPORATING MULTIPLE LCVCOS - In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL. | 10-18-2012 |
20130057325 | AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE - Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation. | 03-07-2013 |
20140159807 | MULTIPLE-CLOCK, NOISE-IMMUNE SLICER WITH OFFSET CANCELLATION AND EQUALIZATION INPUTS - A slicer circuit including an input differential is configured to amplify an input reference voltage received at a pair of differential input nodes and provide a differential output voltage at a pair of differential output nodes, and a regeneration latch configured to amplify the differential output voltage. A differential offset compensation voltage is applied to the differential output voltage to provide DC-offset cancellation. A differential equalization voltage is applied to the differential output voltage to provide DFE equalization. A timing scheme employing multiple clocks provides reduced sampling-window width and increased output-signal width. Cross-coupled transistors are used to cancel kickback noise received at the differential output nodes. | 06-12-2014 |
Patent application number | Description | Published |
20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |
20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit. The series of data bits satisfies an LDPC parity equation. | 02-03-2011 |
20110029835 | Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding - Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix including selecting a non-affiliated variable node; identifying a check node of the lowest degree; connecting a first edge of the non-affiliated variable node to the identified check node; and connecting one or more additional edges of the non-affiliated variable node to check nodes in accordance with a quasi-cyclic constraint associated with a circulant is disclosed. | 02-03-2011 |
20110029839 | Systems and Methods for Utilizing Circulant Parity in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant. | 02-03-2011 |
20110311002 | Turbo-Equalization Methods For Iterative Decoders - Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (L | 12-22-2011 |
20120151286 | Cross-Decoding for Non-Volatile Storage - Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used. | 06-14-2012 |
20130139035 | LDPC Erasure Decoding for Flash Memories - A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria. | 05-30-2013 |
20140082459 | MEASURING CELL DAMAGE FOR WEAR LEVELING IN A NON-VOLATILE MEMORY - An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM. | 03-20-2014 |
20140104943 | ACCELERATED SOFT READ FOR MULTI-LEVEL CELL NONVOLATILE MEMORIES - A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page. | 04-17-2014 |
20140136927 | ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE - Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time. | 05-15-2014 |
20140331096 | Cross-Decoding for Non-Volatile Storage - Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used. | 11-06-2014 |
Patent application number | Description | Published |
20120091514 | Semiconductor Junction Diode Device And Method For Manufacturing The Same - A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level. | 04-19-2012 |
20120187496 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced. | 07-26-2012 |
20120187497 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits. | 07-26-2012 |
20120187501 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device. | 07-26-2012 |
20120191392 | METHOD FOR ANALYZING CORRELATIONS AMONG DEVICE ELECTRICAL CHARACTERISTICS AND METHOD FOR OPTIMIZING DEVICE STRUCTURE - A method for analyzing correlations among electrical characteristics of an electronic device and a method for optimizing a structure of the electronic device are disclosed. The electronic device may comprises a plurality of electrical characteristics v | 07-26-2012 |
20120261727 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING LOCAL INTERCONNECT STRUCTURE THEREOF - A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth. | 10-18-2012 |
20120273886 | EMBEDDED SOURCE/DRAIN MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate. | 11-01-2012 |
20120281468 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage V | 11-08-2012 |
20120286337 | FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance. | 11-15-2012 |
20120286373 | GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value. | 11-15-2012 |
20120290998 | DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD - The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation. | 11-15-2012 |
20120309139 | METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR - An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device. | 12-06-2012 |
20130015526 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEAANM Liang; QingqingAACI LagrangevilleAAST NYAACO USAAGP Liang; Qingqing Lagrangeville NY USAANM Zhu; HuilongAACI PoughkeepsieAAST NYAACO USAAGP Zhu; Huilong Poughkeepsie NY USAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA US - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device. | 01-17-2013 |
20130015529 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA USAANM Liang; QingqingAACI LangrangevilleAAST NYAACO USAAGP Liang; Qingqing Langrangeville NY USAANM Ying; HaizhouAACI PoughkeepsieAAST NYAACO USAAGP Ying; Haizhou Poughkeepsie NY US - There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits. | 01-17-2013 |
20130020578 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region. | 01-24-2013 |
20130020618 | SEMICONDUCTOR DEVICE, FORMATION METHOD THEREOF, AND PACKAGE STRUCTURE - A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating. | 01-24-2013 |
20130037859 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application. | 02-14-2013 |
20130045588 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved. | 02-21-2013 |
20130049125 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices. | 02-28-2013 |
20130062708 | SEMICONDUCTOR DEVICE STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING FIN - A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices. | 03-14-2013 |
20130093041 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device. | 04-18-2013 |
20130140624 | Semiconductor Structure and Method for Forming The Semiconductor Structure - The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer. | 06-06-2013 |
20130153913 | Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor - A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. | 06-20-2013 |
20130200456 | Semiconductor Substrate, Integrated Circuit Having the Semiconductor Substrate, and Methods of Manufacturing the Same - The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed. | 08-08-2013 |
20130221329 | Graphene Device - An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc. | 08-29-2013 |
20130221414 | Semiconductor FET and Method for Manufacturing the Same - The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated. | 08-29-2013 |
20130267073 | Method of Manufacturing Fin Field Effect Transistor - The present invention discloses a method of manufacturing a fin field effect transistor, which comprises the steps of forming a plurality of first fin structures on a substrate, which extend along a first direction parallel to the substrate; forming a plurality of second fin structures on a substrate, which extend along a second direction parallel to the substrate and the second direction intersecting with the first direction; selectively removing a part of the second fin structures to form a plurality of gate lines; and selectively removing a part of the first fin structures to form a plurality of substrate lines. In the method of manufacturing a fin field effect transistor according to the present invention, the gate lines and substrate lines are formed simultaneously by first making uniform silicon wing lines and gate wing lines using a limiting photolithography patternizing technique and then performing a centralized cutting of the corresponding specific regions, thereby increasing uniformity and reducing process difficulty and cost. | 10-10-2013 |
20130341713 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer. | 12-26-2013 |
20140027864 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer. | 01-30-2014 |
20140110756 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer. | 04-24-2014 |
20140124847 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer. | 05-08-2014 |
20140302644 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved. | 10-09-2014 |
20140357027 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved. | 12-04-2014 |
20150054073 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate. | 02-26-2015 |
20150054074 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer. | 02-26-2015 |
Patent application number | Description | Published |
20090016422 | SYSTEM FOR AN ADAPTIVE FLOATING TAP DECISION FEEDBACK EQUALIZER - A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. | 01-15-2009 |
20090289348 | SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION - A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces. | 11-26-2009 |
20100046598 | Adaptation Of A Linear Equalizer Using A Virtual Decision Feedback Equalizer (VDFE) - A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer. | 02-25-2010 |
20100177816 | TX BACK CHANNEL ADAPTATION ALGORITHM - Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g., a slicer) as the quantifier input signal to quantify the quantifier input signal to one of multiple digital values. The channel distorted signal may be further adjusted by summing the channel distorted signal with the output of a Decision Feedback Equalizer (DFE) filter to create a DFE corrected signal which then becomes the quantifier input signal. An error signal is determined by finding the difference between the scaled quantifier decision and the quantifier input signal. The pre/post cursor coefficient values that adjust the effects of the pre/post cursor taps of the FIR filter are updated as a function of the error signal and at least two quantifier decision values, and update coefficient values, may be sent over a communications back-channel to the FIR filter. | 07-15-2010 |
20100284686 | PRECURSOR ISI CANCELLATION USING ADAPTATION OF NEGATIVE GAIN LINEAR EQUALIZER - An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols. | 11-11-2010 |
20100329326 | METHODS AND APPARATUS FOR DECISION-FEEDBACK EQUALIZATION WITH OVERSAMPLED PHASE DETECTOR - Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data. | 12-30-2010 |
20110142120 | FLOATING-TAP DECISION FEEDBACK EQUALIZER FOR COMMUNICATION CHANNELS WITH SEVERE REFLECTION - An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively. | 06-16-2011 |
20120057626 | ADAPTATION OF CROSSING LATCH THRESHOLD - An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock and data recovery module due to coupling between the bang-bang clock and data recovery module and the decision feedback equalizer. | 03-08-2012 |
20120155528 | ADAPTATION OF BASELINE WANDER CORRECTION LOOP GAIN SETTINGS - An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit. | 06-21-2012 |
20120155530 | DECOUPLING BANG-BANG CDR AND DFE - An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. A phase detector of the bang-bang clock and data recovery module may be configured to eliminate coupling between the bang-bang clock and data recovery module and the decision feedback equalizer based upon an error signal of the decision feedback equalizer and a predetermined coefficient. | 06-21-2012 |
20120236925 | ADAPTATION OF DELAY LINE FEEDBACK EQUALIZER - An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal. | 09-20-2012 |
20120250753 | CROSSING ISI CANCELLATION - An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal. | 10-04-2012 |
20140023134 | ADAPTATION OF BASELINE WANDER CORRECTION LOOP GAIN SETTINGS - An apparatus includes a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit. | 01-23-2014 |
20140029651 | BACK CHANNEL ADAPTATION USING CHANNEL PULSE RESPONSE - An apparatus having a transmitter is disclosed. The transmitter generally has a filter coupled to a communication channel. The transmitter may be configured to adjust the filter using information based on an estimate of one or more characteristics of the communication channel. | 01-30-2014 |
20140064352 | FEED FORWARD EQUALIZER TAP WEIGHT ADAPTATION BASED ON CHANNEL ESTIMATION - An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel. | 03-06-2014 |
20140064353 | CROSSING ISI CANCELLATION - An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal. | 03-06-2014 |
20140177693 | INFLUENCE CLOCK DATA RECOVERY SETTLING POINT BY APPLYING DECISION FEEDBACK EQUALIZATION TO A CROSSING SAMPLE - An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal. | 06-26-2014 |
20140254655 | ADAPTATION OF EQUALIZER SETTINGS USING ERROR SIGNALS SAMPLED AT SEVERAL DIFFERENT PHASES - An apparatus includes an error sample generating circuit and an adaptation circuit. The error sample generating circuit is generally configured to generate error samples at a plurality of phases. The adaptation circuit may be configured to adjust one or more equalizer settings based upon a data sample and the error samples. | 09-11-2014 |
20140314138 | BACK CHANNEL ADAPTATION FOR TRANSMISSION UNDER PEAK POWER CONSTRAINTS - A method comprises adapting a first tap weight of an equalizer, wherein a second tap weight of the equalizer is based at least in part on the first tap weight. Adapting the first tap weight further comprises computing a gradient from a data signal, an error signal and a channel pulse response sample. Adapting the first tap weight also comprises filtering the gradient with a loop filter and sending information to a transmitter via a back channel. Adapting the first tap weight further comprises configuring the first tap weight based on the information. | 10-23-2014 |
Patent application number | Description | Published |
20100092541 | COMPOSITIONS AND METHODS FOR TREATMENT OF EYE DISORDERS - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 04-15-2010 |
20100093693 | MODULATORS OF CELLULAR ADHESION - The present invention provides compounds having formula (I); | 04-15-2010 |
20100179123 | THIENOPYRIMIDINES USEFUL AS AURORA KINASE INHIBITORS - The present invention provides compounds having the formula: | 07-15-2010 |
20110124625 | Modulators of Cellular Adhesion - The present invention provides compounds having formula (I): | 05-26-2011 |
20110124669 | Modulators of Cellular Adhesion - The present invention provides compounds having formula (I): | 05-26-2011 |
20110165228 | Compositions and Methods for Treatment - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 07-07-2011 |
20110165229 | Compositions and Methods for Treatment - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 07-07-2011 |
20120035154 | Modulators of Cellular Adhesion - The present invention provides compounds having formula (I): | 02-09-2012 |
20140051675 | MODULATORS OF CELLULAR ADHESION - The present invention provides compounds having formula (I): | 02-20-2014 |
20140066476 | MODULATORS OF CELLULAR ADHESION - The present invention provides compounds having formula (I): | 03-06-2014 |
20140073666 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 03-13-2014 |
20140099387 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 04-10-2014 |
20140141062 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 05-22-2014 |
20140161872 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 06-12-2014 |
20140371265 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 12-18-2014 |
20140378506 | COMPOSITIONS AND METHODS FOR TREATMENT - The present invention provides compounds and methods for the treatment of LFA-1 mediated diseases. In particular, LFA-1 antagonists are described herein and these antagonists are used in the treatment of LFA-1 mediated diseases. One aspect of the invention provides for diagnosis of an LFA-1 mediated disease and administration of a LFA-1 antagonist, after the patient is diagnosed with a LFA-1 mediated disease. In some embodiments, the LFA-1 mediated diseases treated are dry eye disorders. Also provided herein are methods for identifying compounds which are LFA-1 antagonists. | 12-25-2014 |
Patent application number | Description | Published |
20090036478 | Substituted hydroxyethyl amine compounds as beta-secretase modulators and methods of use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 02-05-2009 |
20090275602 | Substituted hydroxyethyl amine compounds as beta-secretase modulators and methods of use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 11-05-2009 |
20100120774 | Substituted Pyrano [2,3-b] Pyridinamine compounds as beta-secretase modulators and methods of use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 05-13-2010 |
20100222338 | BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 09-02-2010 |
20100317668 | SUBSTITUTED PYRANO [2,3-B] PYRIDINAMINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 12-16-2010 |
20110118250 | BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 05-19-2011 |
20110251186 | Amino-Oxazines and Amino-Dihydrothiazine Compounds as Beta-Secretase Modulators and Methods of Use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 10-13-2011 |
20110251190 | SPIRO-TETRACYCLIC RING COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and other related conditions. In one embodiment, the compounds have a general Formula I | 10-13-2011 |
20110306587 | UNSATURATED NITROGEN HETEROCYCLIC COMPOUNDS USEFUL AS PDE10 INHIBITORS - Unsaturated nitrogen heterocyclic compounds of formula (I): | 12-15-2011 |
20120220583 | SUBSTITUTED HYDROXYETHYL AMINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase activity and for the treatment of diseases, including Alzheimer's disease (AD) and related CNS conditions, mediated thereby. In one embodiment, the compounds have a general Formula I | 08-30-2012 |
20120329830 | Amino Heteroaryl Compounds as Beta-Secretase Modulators and Methods of Use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I wherein ring A, B | 12-27-2012 |
20130072483 | SUBSTITUTED HYDROXYETHYL AMINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 03-21-2013 |
20130157996 | TRPM8 ANTAGONISTS AND THEIR USE IN TREATMENTS - Compounds of Formula I are useful as antagonists of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 06-20-2013 |
20130158034 | TRPM8 ANTAGONISTS AND THEIR USE IN TREATMENTS - Compounds of Formula I are useful as antagonists of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 06-20-2013 |
20130172343 | Derivatives of 1H-isoindol-3-amine, 1H-iso-aza-indol-3amine, 3,4-dihydroisoquinolin-1-amine, and 1,4-dihydroisoquinolin-3-amine as Beta-secretase Inhibitors - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I: (I). In another embodiment, the compounds have a general Formula II: (II). In another embodiment, the compounds have a general Formula III: (III). Variables A | 07-04-2013 |
20130225552 | HETEROBICYCLIC COMPOUNDS - Heterobicyclic compounds of Formula (I): | 08-29-2013 |
20130338138 | AZETIDINE AND PIPERIDINE COMPOUNDS USEFUL AS PDE10 INHIBITORS - Azetidine and piperidine compounds of formula (I): | 12-19-2013 |
20130338177 | Spiro-Amino-Imidazolone and Spiro-Amino-Dihydro-Pyrimidinone Compounds as Beta-Secretase Modulators and Methods of Use - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula (I), wherein variables A | 12-19-2013 |
20140045828 | AMINO-OXAZINES AND AMINO-DIHYDROTHIAZINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 02-13-2014 |
20140045855 | CHROMAN DERIVATIVES AS TRPM8 INHIBITORS - Chroman compounds and derivatives of Formula I are useful inhibitors of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 02-13-2014 |
20140107109 | AMINO-DIHYDROTHIAZINE AND AMINO-DIOXIDO DIHYDROTHIAZINE COMPOUNDS AS BETA-SECRETASE ANTAGONISTS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 04-17-2014 |
20140148435 | AZETIDINE AND PIPERIDINE COMPOUNDS USEFUL AS PDE10 INHIBITORS - Azetidine and piperidine compounds of formula (I): | 05-29-2014 |
20140171406 | TRPM8 ANTAGONISTS AND THEIR USE IN TREATMENTS - Compounds of Formula I are useful as antagonists of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 06-19-2014 |
20140171639 | TRPM8 ANTAGONISTS AND THEIR USE IN TREATMENTS - Compounds of Formula I are useful as antagonists of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 06-19-2014 |
20140213572 | UNSATURATED NITROGEN HETEROCYCLIC COMPOUNDS USEFUL AS PDE10 INHIBITORS - Unsaturated nitrogen heterocyclic compounds of formula (I): | 07-31-2014 |
20140235642 | TRPM8 ANTAGONISTS AND THEIR USE IN TREATMENTS - Compounds of Formula I are useful as antagonists of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 08-21-2014 |
20140249104 | PERFLUORINATED 5,6-DIHYDRO-4H-1,3-OXAZIN-2-AMINE COMPOUNDS AS BETA-SECRETASE INHIBITORS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 09-04-2014 |
20150031668 | CHROMAN DERIVATIVES AS TRPM8 INHIBITORS - Chroman compounds and derivatives of Formula I are useful inhibitors of TRPM8. Such compounds are useful in treating a number of TRPM8 mediated disorders and conditions and may be used to prepare medicaments and pharmaceutical compositions useful for treating such disorders and conditions. Examples of such disorders include, but are not limited to, migraines and neuropathic pain. Compounds of Formula I have the following structure: | 01-29-2015 |