Patent application number | Description | Published |
20130134381 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current. | 05-30-2013 |
20130145984 | METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT - This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region. | 06-13-2013 |
20130175493 | PHASE CHANGE MEMORY STRUCTURE HAVING LOW-K DIELECTRIC HEAT-INSULATING MATERIAL AND FABRICATION METHOD THEREOF - The present invention discloses a phase change memory structure having low-k dielectric heat-insulating material and fabrication method thereof, wherein the phase change memory cell comprises diode, heating electrode, reversible phase change resistor, top electrode and etc; the heating electrode and reversible phase change resistor are surrounded by low-k dielectric heat-insulating layer; an anti-diffusion dielectric layer is designed between the reversible phase change resistor and the low-k dielectric heat-insulating layer surrounding thereof. The present invention utilizes low-k dielectric material as heat-insulating material, thereby avoiding thermal crosstalk and mutual influence during operation between phase change memory cells, enhancing the reliability of devices, and eliminating the influence of temperature, pressure and etc. on phase change random access memory (PCRAM) data retention during the change from amorphous to polycrystalline states. Furthermore, an anti-diffusion dielectric layer is prepared between the low-k dielectric material and the phase change material, which can be used to prevent the elements of the phase change material from diffusing to low-k dielectric material. The fabrication process of said phase change memory is compatible with standard complementary metal-oxide semiconductor (CMOS) process and the chemical mechanical polishing (CMP) process with low pressure and light corrosion is adopted in polishing. | 07-11-2013 |
20130189799 | METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY - The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory. | 07-25-2013 |
20130292629 | PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF - The present invention provides a phase change memory cell and fabrication method thereof, wherein said phase change memory cell comprises a semiconductor substrate, a first electrode layer, a phase change material layer, a second electrode layer and an extraction electrode, as well as a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process, and wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer and can be used to prevent phase change material layer from over-corrosion during the chemical mechanical polishing process and thus enhance the memory performance and the yield of phase change memory cell. | 11-07-2013 |
20130334469 | AL-SB-TE PHASE CHANGE MATERIAL USED FOR PHASE CHANGE MEMORY AND FABRICATION METHOD THEREOF - The present invention discloses an Al—Sb—Te phase change material used for PCM and fabrication method thereof. Said phase change material, which can be prepared by PVD, CVD, ALD, PLD, EBE, and ED, is a mixture of three elements aluminum (Al), antimony (Sb) and tellurium (Te) with a general formula of Al | 12-19-2013 |
20140078820 | DATA READOUT CIRCUIT OF PHASE CHANGE MEMORY - A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result. Compared with the prior art, the data readout circuit of phase change memory provided by the present invention can effectively enhance the data readout speed, decrease the misreading window between high resistance state and low resistance state, reduce the crosstalk of data readout, and improve the reliability of data readout. | 03-20-2014 |
20140192592 | SB-TE-TI PHASE-CHANGE MEMORY MATERIAL AND TI-SB2TE3 PHASE-CHANGE MEMORY MATERIAL - The present invention relates to an Sb—Te—Ti phase-change thin-film material applicable to a phase-change memory and preparation thereof. The Sb—Te—Ti phase-change memory material of the present invention is formed by doping an Sb—Te phase-change material with Ti, Ti forms bonds with both Sb and Te, and the Sb—Te—Ti phase-change memory material has a chemical formula Sb | 07-10-2014 |
20140291597 | High-speed, High-density, and Low-power consumption Phase-change Memory Unit, and Preparation Method Thereof - The present invention provides a high-speed, high-density, and low-power consumption phase-change memory unit, and a preparation method thereof In the preparation method of the present invention, a transition material layer with an accommodation space is first prepared on a surface of a structure of a formed first electrode, where the accommodation space corresponds to the first electrode; a phase-change material layer is then prepared on a structure of the formed transition material layer, and the phase-change material layer is enabled to be in the accommodation space; and afterwards, a second electrode material layer is prepared on a surface of a structure of the prepared phase-change material layer, so as to prepare a phase-change memory unit; where phase-change material layer and the first electrode are isolated from each other by the transition material layer, and the second electrode material layer is in electrical communication with the phase-change material layer. | 10-02-2014 |