Patent application number | Description | Published |
20090294873 | FIELD EFFECT STRUCTURE AND METHOD INCLUDING SPACER SHAPED METAL GATE WITH ASYMMETRIC SOURCE AND DRAIN REGIONS - A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device, such as a field effect transistor, that includes a spacer shaped metal gate located over a channel within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Within the semiconductor structure, the plurality of source and drain regions is asymmetric with respect to the spacer shaped metal gate. The particular semiconductor structure may be fabricated using a self aligned dummy gate method that uses a portion of a spacer as a self alignment feature when forming the spacer shaped metal gate, which may have a sub-lithographic linewidth. | 12-03-2009 |
20100038789 | CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS - A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer. | 02-18-2010 |
20100237442 | SELECTIVELY SELF-ASSEMBLING OXYGEN DIFFUSION BARRIER - A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric. | 09-23-2010 |
20120189767 | SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES - A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates. | 07-26-2012 |
Patent application number | Description | Published |
20100319962 | SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES - A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates. | 12-23-2010 |
20110100413 | REGENERATION METHOD FOR RESTORING PHOTOVOLTAIC CELL EFFICIENCY - An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5. | 05-05-2011 |
20110162875 | SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION - A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer. | 07-07-2011 |
20110168434 | BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING - Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates. | 07-14-2011 |
20110183520 | Method for Removing Copper Oxide Layer - The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents. | 07-28-2011 |
20110193240 | BONDED STRUCTURE WITH ENHANCED ADHESION STRENGTH - A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates. | 08-11-2011 |
20110215409 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 09-08-2011 |
20130171773 | BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING - Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates. | 07-04-2013 |
20140239458 | BONDED STRUCTURE WITH ENHANCED ADHESION STRENGTH - A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates. | 08-28-2014 |
Patent application number | Description | Published |
20120187420 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 07-26-2012 |
20130062677 | SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY - A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor. | 03-14-2013 |
20140070293 | SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY - A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor. | 03-13-2014 |
Patent application number | Description | Published |
20140203360 | REDUCING CONTACT RESISTANCE BY DIRECT SELF-ASSEMBLING - As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region. | 07-24-2014 |
20140312249 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140315316 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140326047 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140326613 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140370671 | RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME - An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact. | 12-18-2014 |
20150014755 | JANUS COMPLEMENTARY MEMS TRANSISTORS AND CIRCUITS - A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge. | 01-15-2015 |