Patent application number | Description | Published |
20120274384 | SEMICONDUCTOR DEVICE - The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors. | 11-01-2012 |
20130341642 | MOS TRANSISTOR, FABRICATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased. | 12-26-2013 |
20130341726 | MOS TRANSISTOR, FORMATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory. | 12-26-2013 |
20140015136 | IC DEVICE INCLUDING PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - Various embodiments provide semiconductor devices including a package structure and methods of forming the semiconductor devices. In one embodiment, the package structure can include a through-hole at least partially filled by one or more layers of material(s) to form a through-hole interconnect between semiconductor devices in the package structure. The through-hole can be filled by an insulating layer, a diffusion barrier layer, a metal interconnect layer, and/or a protective layer having a total thickness from the sidewall of the through-hole of less than or equal to the radius of the through-hole. | 01-16-2014 |
20140361400 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide electrostatic discharge protection structures and methods for forming the same. An exemplary structure can include a semiconductor chip including a through hole. The structure can further include a through silicon via (TSV) structure disposed within the through hole and passing through the semiconductor chip. The TSV structure can have a first surface and a second surface. The structure can further include a tunneling dielectric layer disposed on the first surface of the TSV structure. The tunneling dielectric layer can have a surface area covering a top view surface area of the TSV structure and a surface portion of the semiconductor chip surrounding the TSV structure. Yet further, the structure can include a metal material discretely dispersed in the tunneling dielectric layer, a first electrode disposed on the tunneling dielectric layer, and a second electrode disposed on the second surface of the TSV structure. | 12-11-2014 |
20150311313 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different. | 10-29-2015 |
20160028376 | INTEGRATED CIRCUIT DEVICE AND REPAIR METHOD THEREOF - The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer. The IC device also includes a repair circuit configured to apply a negative bias voltage to the substrate of the PMOS transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric layer to neutralize holes caused by negative bias temperature instability (NBTI) effect. The repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor when the PMOS transistor is in an ON state. As such, the disclosed IC device repairs defect caused by NBTI effect in the PMOS transistor and prolongs the lifespan of the PMOS transistor. | 01-28-2016 |
20160071797 | EFUSE STRUCTURE WITH STRESSED LAYER - An electrically programmable fuse device includes an anode, a cathode, a fuse link connecting the anode and the cathode, a compressive stress layer on the anode, and a tensile stress layer on the cathode. Because of the compressive stress layer on the anode and a tensile stress layer on the cathode, the programming speed of the electrically programmable fuse device is shorter in relation to conventional electrically programmable fuse devices. | 03-10-2016 |
20160086660 | ELECTROMECHANICAL NONVOLATILE MEMORY - A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including TiN and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line. By having the TiAl bit line and TiN word line, the uniformity of the bit line and word line can be easily controlled to improve the performance of the semiconductor device. | 03-24-2016 |