Patent application number | Description | Published |
20110031997 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse. | 02-10-2011 |
20110084314 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 04-14-2011 |
20110199116 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die. | 08-18-2011 |
20120012895 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 01-19-2012 |
20120129301 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer. | 05-24-2012 |
20120193806 | 3D SEMICONDUCTOR DEVICE - A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias. | 08-02-2012 |
20120194216 | 3D Semiconductor Device - A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer. | 08-02-2012 |
20120194218 | 3D Semiconductor Device - A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer. | 08-02-2012 |
20120196390 | 3D SEMICONDUCTOR DEVICE WITH REDUNDANCY - A method for manufacturing system includes 3D-IC comprising at least first layer of first transistors and second layers of second transistors and, perform a test for the circuit constructed with said first transistors and switch in function constructed with said second transistors to replace function constructed with said first transistors. | 08-02-2012 |
20120273955 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 11-01-2012 |
20120322203 | METHOD TO CONSTRUCT SYSTEMS - A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die. | 12-20-2012 |
20130020707 | NOVEL SEMICONDUCTOR SYSTEM AND DEVICE - A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer. | 01-24-2013 |
20130122672 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented. | 05-16-2013 |
20140059411 | NOVEL COMPUTING SYSTEM - A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier. | 02-27-2014 |