# Yuji Shinohara, Kanagawa JP

## Yuji Shinohara, Kanagawa JP

Patent application number | Description | Published |
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20120106608 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND PROGRAM - A signal processing apparatus is disclosed which includes: a detection section configured such that based on a result of the error correction of a signal generated by a single carrier system, the detection section detects the presence or absence of spectrum inversion in the signal; and a selection section configured such that if the detection section detects the spectrum inversion, the selection section selects the spectrally inverted signal as the signal subject to the error correction, and that if the detection section does not detect the spectrum inversion, then the selection selects the spectrally uninverted signal as the signal subject to the error correction. | 05-03-2012 |

20120320994 | ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY - The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z | 12-20-2012 |

20130166992 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b | 06-27-2013 |

20130227378 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to data processing devices and data process methods that can increase tolerance for data errors. | 08-29-2013 |

20130254617 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder | 09-26-2013 |

20130290816 | DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD - The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data. | 10-31-2013 |

20130297992 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method capable of improving resistance to error of data. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 4/15, 7/15, or 8/15. A parity check matrix of the LDPC code is composed by arrangement of an element of an information matrix determined by a parity check matrix initial value table indicating a position of the element of the information matrix corresponding to an information length corresponding to the code length and the code rate for each 360 columns of the parity check matrix with a period of 360 columns in a column direction. The parity check matrix initial value table is for digital broadcasting for a mobile terminal, for example. This technology may be applied to a case in which LDPC encoding and LDPC decoding are performed. | 11-07-2013 |

20130305113 | DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD - When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for an LDPC codes having coding rates of 7/15, b | 11-14-2013 |

20130311850 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code. | 11-21-2013 |

20140040707 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technology relates to a data processing device and a data processing method that enable tolerance against error of data to be improved. In the case in which an LDPC code having a code length of DVB-S.2 of 16200 bits and an encoding rate of 1/3 is modulated by 16 QAM, if a code bit of 4×2 bits and a (i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y6, y0, y3, y4, y5, y2, y1, and y7, respectively. The present invention can be applied to a transmission system transmitting an LDPC code or the like. | 02-06-2014 |

20140047295 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. | 02-13-2014 |

20140082452 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved. | 03-20-2014 |

20150046765 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |

20150046766 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |