Patent application number | Description | Published |
20120059041 | Methods for Extending Lifespan in Subject - Disclosed is a method for extending lifespan in a subject. By screening for mutations that enhance resistance to multiple stresses, the invention identified multiple alleles of alpha-1, 2-mannosidase I (mas1) which, in addition to promoting stress resistance, also extended longevity. Meanwhile, longevity enhancement of a subject is also observed when either the expression of mas1 or its downstream gene Edm1 is reduced. Furthermore, this invention also found that the down-regulating mas1 and Edm1 may extend longevity by modulating DR (Dietary Restriction). Thus, via molecular biology techniques, the expression of the target genes such as mas1 and Edm1 can be regulated, and the lifespan extension for a subject also can be achieved. | 03-08-2012 |
20120258116 | METHOD FOR INDUCING CANCER CELL APOPTOSIS OR INHIBITING THE CANCER CELL MIGRATION - The present invention is related to a method for inducing the cancer cell apoptosis or inhibiting the cancer cell migration by inhibiting the expression of ribose-5-phosphate isomerase A. | 10-11-2012 |
20130029317 | METHOD FOR EARLY DIAGNOSIS OF LIVER CANCER AND PREDICTION OF METASTASIS - Disclosed is a method for early diagnosis of liver cancer. The method comprises the steps of: (A) providing a sample obtained from a subject; (B) assessing the expression level of four subtypes of α-mannosidase genes consisting of MAN1C1 in the sample; (C) comparing the expression level of α-mannosidase genes in the sample with a normal control; and (D) determining whether the subject having a risk of suffering liver cancer in accordance with the result of step (C); wherein while the MAN1C1 expression level of the sample is lower than that in the normal control, the subject is determined to have a risk of suffering liver cancer. Additionally, while MAN1A1, MAN1A2 and MAN1B1 expression levels in the sample are higher than those in control group, the subject is determined to suffer from liver cancer and has a risk of metastasis. | 01-31-2013 |
20140099647 | METHOD FOR EARLY DIAGNOSIS OF LIVER CANCER - Disclosed is a method for early diagnosis of liver cancer. The method comprises the steps of:(A) providing a sample obtained from a subject; (B) assessing the expression level of four subtypes of α-mannosidase genes consisting of MAN1C1 in the sample; (C) comparing the expression level of α-mannosidase genes in the sample with a normal control; and (D) determining whether the subject having a risk of suffering liver cancer in accordance with the result of step (C); wherein while the MAN1C1 expression level of the sample is lower than that in the normal control, the subject is determined to have a risk of suffering liver cancer. Additionally, while MAN1A1, MAN1A2 and MAN1B1 expression levels in the sample are higher than those in control group, the subject is determined to suffer from liver cancer and has a risk of metastasis. In the future, MAN1C1 can be applied to early diagnosis of liver cancer and metastasis, suppression of liver metastasis, and screening agents for treating liver cancer. | 04-10-2014 |
Patent application number | Description | Published |
20130187555 | Flicker-Free LED Driver Circuit with High Power Factor - A flicker-free LED driver circuit with a high power factor has a rectifying unit connected with an AC power source, an LED module connected in series with the rectifying unit, a capacitor module connected in parallel with the LED module, and a constant current circuit connected in series with the LED module and the capacitor module. When the voltage output by the rectifying unit is smaller than a junction voltage of the LED module, the capacitor module discharges to the LED module so that the LED module does not go out, thereby eliminating the flickering. The input impedance of the rectifying unit can be regarded as a capacitive reactance element connected in parallel with a nonlinear resistive element. The internal resistance of the constant current source approaches infinity. Therefore, the power factor of the flicker-free LED driver circuit approximates 1, achieving a high power factor. | 07-25-2013 |
20130222965 | Arrester - An arrester includes a switch and a lightning detection breaker connected to the switch. The lightning detection breaker includes a metal conducting terminal electrically connected to an earth return, a DC power supply terminal, a ground terminal and an output terminal. When the power supply is under a lightning strike, a potential difference of both the DC power supply terminal and the ground terminal of the lightning detection breaker will go up to several thousands of volts. However, a voltage of the metal conducting terminal will not go up because the metal conducting terminal is electrically connected to the earth return. The switch will automatically become open circuit by the lightning detection breaker, and therefore an electronic device connected to the arrester is protected from damage done by the lightning. | 08-29-2013 |
20130313991 | FLICKER-FREE LINEAR LED DRIVER CIRCUIT WITH HIGH POWER FACTOR - The flicker-free linear LED driver circuit with high power factor has a rectifier unit, an LED unit, a constant current unit, a storage capacitor and a voltage controlled transistor; the rectifier unit is connected to an AC power and converts the AC power into a pulsating DC power; the LED unit is connected to the rectifier unit and has multiple LED sources; the constant current unit is connected in series with the LED unit to form a first power circuit; wherein current flowing in the LED unit is fixed to a constant value by the constant current unit; the storage capacitor is connected to the rectifier unit; the voltage controlled transistor is connected in series with the storage capacitor to form a second power circuit; wherein the voltage controlled transistor limits current flowing in the storage capacitor under a maximum current limit value. | 11-28-2013 |
20140028203 | LED DRIVER CIRCUIT - A high efficiency AC LED driver circuit has a rectifier unit, an LED light string, multiple voltage controlled transistors, a current detection unit, and a power efficiency control unit. The rectifier unit is connected to an AC power and converts the AC power into a pulsating DC power. The LED light string is connected to the rectifier unit and has multiple LED units. The voltage controlled transistors are respectively and electrically connected to each LED unit and form multiple shunt circuits. The current detection unit is electrically connected to the voltage controlled transistors. The power efficiency control unit is electrically connected to the current detection unit, series nodes between the LED units and the control terminals of the voltage controlled transistors; wherein the power efficiency control unit adjusts loop current based on a voltage drop of each LED unit. | 01-30-2014 |
20140055175 | High-Voltage Driver Integratable with an Integrated Circuit - A high-voltage driver integratable with an integrated circuit has a switching transistor, a switching diode, a first resistor, a second resistor, and a control transistor. The anode of the switching diode is connected to the source of the switching transistor. The cathode of the switching diode is connected to the gate of the switching transistor. When the source voltage of the switching transistor is far greater than the cut-in voltage of the switching diode, the switching diode is forward-biased, and the gate-source voltage of the switching transistor is equal to the negative cut-in voltage. Accordingly, high voltage will not be generated across the gate-source junction of the switching transistor, no junction breakdown will occur between the gate and source thereof, and the high-voltage driver can be integrated with an integrated circuit. | 02-27-2014 |
20140062323 | Linear Light-Emitting Diode Driving Circuit with Voltage-Lowering Serial Capacitor - A linear light-emitting diode (LED) driving circuit with voltage-lowering serial capacitor has a rectification unit, an LED unit, a constant current controller, a series and parallel voltage divider and a controller. The controller is built in with a safe voltage threshold, controls the series and parallel voltage divider to be connected in series to the LED unit when an output voltage of the rectification unit exceeds the safe voltage threshold, ensuring that an average voltage across the LED unit and the constant current controller is stable, and controls the series and parallel voltage divider to be parallelly connected across the LED unit and the ground when the output voltage of the rectification unit does not exceed the safe voltage threshold. Accordingly, a safety standard of voltage for LED driving circuit can be secured and users' safety can be ensured. | 03-06-2014 |
20140159592 | LED LIGHT TUBE COMPATIBLE WITH LIGHT FIXTURE HAVING ELECTRONIC BALLAST OR MAGNETIC BALLAST - The LED light tube compatible with a light fixture having an ballast has a translucent tube and an LED light bar mounted in the translucent tube. and having at least one waveform conversion circuit having multiple rectifier diodes and at least one LED light string connected to the at least one waveform conversion circuit, wherein a recovery time of each rectifier diode is under 1 μs; the ballast determines the at least one waveform conversion circuit and the at least one LED light string as low impedance loads, thus, the ballast does not output a high voltage AC power and burn the LED light tube; a recovery time of each rectifier diode is also short such that the LED light tube can endure a high frequency AC power outputted by the ballast. As such, the LED light tube is compatible with the light fixture. | 06-12-2014 |
20140197748 | LED Lighting Tube - The LED lighting tube that is compatible with an electronic ballast has two snubber circuits, a waveform conversion circuit, and at least one LED light string. The snubber circuits are connected to terminals of the LED lighting tube, and input terminals of each snubber circuit are connected to electrode pins of a corresponding terminal, and each snubber circuit has at least one resistor connected in series between the electrode pins of the corresponding terminal. The waveform conversion circuit has multiple rectifier diodes, wherein input terminals of the waveform conversion circuit are respectively connected to output terminals of the snubber circuits, wherein a recovery time of each rectifier diode is under 2.5 us. Two ends of the at least one LED light string are respectively connected to output terminals of the waveform conversion circuit, wherein each one of the at least one LED light string comprises multiple LED units connected in series. | 07-17-2014 |
20140239814 | LIGHT-EMITTING DIODE LAMP COMPATIBLE WITH AN ELECTRONIC BALLAST GENERATING PREHEATING CURRENT - An LED lamp has two preheating current control units respectively connected to a first electrode terminal and a second electrode terminal of the LED lamp, two lamp-side rectification circuits, and an LED light string. Each preheating current control unit has a ballast-side rectification circuit connected to one of the first and second electrode terminals and a load-varying circuit having a resistive load and a control circuit. The resistive load is serially connected to a DC output terminal of the ballast-side rectification circuit through the control circuit. The control circuit adjusts a resistance of the resistive load. Two input terminals of each lamp-side rectification circuit are respectively connected to one of the electrodes of each of the first electrode terminal and the second electrode terminal. The LED light string has two ends respectively connected to the two output terminals of each lamp-side rectification circuit, and has multiple series-connected LED elements. | 08-28-2014 |
Patent application number | Description | Published |
20140019930 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout. | 01-16-2014 |
20140137062 | PATTERN MATCHING BASED PARASITIC EXTRACTION WITH PATTERN REUSE - The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously. | 05-15-2014 |
20140282337 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances. | 09-18-2014 |
20150186579 | SEMICONDUCTOR DEVICE DESIGN METHOD - A method of generating a netlist comprises extracting a first capacitance value between the first set of electrical components inside a defined region using a first extraction technique. The method additionally comprises extracting a second capacitance value between a second set of electrical components comprising at least one electrical component outside the defined region using a second extraction technique different from the first extraction technique. The method also comprises generating the netlist including the first capacitance value and the second capacitance value. The first extraction technique is capable of extracting capacitance values between electrical components arranged in a first quantity of directions with respect to one another and the second extraction technique is capable of extracting capacitance values between electrical components arranged in a second quantity of directions with respect to one another. The first quantity of directions is greater than the second quantity of directions. | 07-02-2015 |