Patent application number | Description | Published |
20090279559 | Method and apparatus for aggregating input data streams - A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor. | 11-12-2009 |
20090290499 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 11-26-2009 |
20100046521 | System and Method for High Speed Packet Transmission - The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane. | 02-25-2010 |
20100061393 | System and Method for High Speed Packet Transmission - The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane. | 03-11-2010 |
20110110237 | Method and Apparatus for Aggregating Input Data Streams - A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor. | 05-12-2011 |
20110182294 | IN-ORDER TRAFFIC AGGREGATION WITH REDUCED BUFFER USAGE - One embodiment provides a system that performs in-order traffic aggregation from a number of low-speed ports to a high-speed port. During operation, the system receives at a low-speed port a packet, stores it in a store-and-forward FIFO associated with the low-speed port, extracts a sequence number associated with the stored packet, and stores the extracted sequence number in a sequence-number FIFO associated with the low-speed port. The system further generates an expected sequence number, which maintains a linear order with respect to sequence numbers associated with previously forwarded packets, and determines whether a front end of the sequence-number FIFO matches the expected sequence number. If so, the system removes the front end of the sequence-number FIFO buffer, retrieves a packet associated with it, forwards the retrieved packet on the high-speed port, and updates the expected sequence number by adding 1 to the packet number of the retrieved packet. | 07-28-2011 |
20110235518 | SOURCE-BASED CONGESTION DETECTION AND CONTROL - Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source. | 09-29-2011 |
20110268108 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 11-03-2011 |
20120166760 | HIGH SPEED COUNTER DESIGN - Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater. | 06-28-2012 |
20120236722 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 09-20-2012 |
20140023086 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 01-23-2014 |
20140133488 | BACKPLANE INTERFACE ADAPTER WITH ERROR CONTROL AND REDUNDANT FABRIC - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 05-15-2014 |
20140153389 | METHOD AND APPARATUS FOR AGGREGATING INPUT DATA STREAMS - A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor. | 06-05-2014 |
20150078211 | SYSTEM AND METHOD FOR HIGH SPEED PACKET TRANSMISSION - The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane. | 03-19-2015 |