Yuan, Taipei
Chih-Chung Yuan, Taipei TW
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20150160129 | METHOD AND APPARATUS FOR IDENTIFYING CVD DIAMOND - Method for identifying CVD diamond comprises (1) placing a clean diamond on a fixed platform; (2) illuminating the diamond with light having various wavelengths; (3) receiving reflected light from the diamond; (4) calculating a reflectance value at each wavelength based on a light intensity at each wavelength of the reflected light, generating a spectral reflectance curve; (5) determining whether the spectral reflectance curve has a sharp trough, then storing the diamond if the spectral reflectance curve thereof does not have the sharp trough, while selecting the diamond for a further identification if the spectral reflectance curve thereof has the sharp trough; and (6) determining whether the sharp trough of the diamond selected from the step (5) is at a wavelength between 227 nm and 233 nm, and identifying the diamond to be the CVD diamond if the sharp trough is at the wavelength between 227 nm and 233 nm. | 06-11-2015 |
Ching-Yao Yuan, Taipei TW
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20130267645 | WEATHER-RESISTANT CROSSLINKED POLYOLEFIN COMPOSITION, POLYOLEFIN SHEET MADE FROM THE SAME AND METHOD FOR MAKING THE SHEET - A weather-resistant crosslinked polyolefin composition is a novel formula containing a comprehensive mixture constituted by crosslinking agent, antistatic agent, TiO | 10-10-2013 |
20150104698 | ALUMINUM FILM PACKAGING MATERIALS USED FOR LITHIUM BATTERIES - A method for lithium aluminum film packaging materials, with water, high temperature and corrosion resistance, the substrate layer, and then layer, aluminum foil layer, anti-corrosion layer, adhesive layer and the inner layer together constitute from the outermost to innermost layer laminate structure in which one side of the aluminum foil layer, or both side surface of the conductive coating material to said coating and curing anticorrosive layer, and the use of fluorine-containing polyurethane resin constituting the laminated rubber layer and the inner layer of corrosion between the adhesive layer, used lithium batteries as plastic film packaging applications, it can promote lithium battery with Merit water resistance, high temperature resistance and corrosion resistance, and enhance the use of lithium batteries in years. | 04-16-2015 |
Chin-Shan Yuan, Taipei TW
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20120198496 | Video Related Tag Generating Apparatus, Video Related Tag Generating Method, Video Interacting Method, Video Interacting System and Video Interacting Apparatus - A video related tag generating apparatus, a video related tag generating method, a video interacting method, a video interacting system and a video interacting apparatus are provided. The video interacting method includes the following steps. A video broadcast program is received via a video signal receiver, and a video related tag is received via a network interface. The video related tag relates to a target object, and the video broadcast program includes a video frame having the target object. A synchronous information, an object position and object information are generated according to the video related tag. A triggering region is generated according to the object position. The triggering region is synchronously overlapped on the video frame according to the synchronous information. A key-press signal is received to select the triggering region, such that the object information is overlapped on the video frame. | 08-02-2012 |
Dalun Yuan, Taipei TW
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20100309702 | DC-TO-AC POWER INVERTER AND METHODS - Embodiments of the invention relate generally to semiconductors for power generation and conversion applications, and more particularly, to devices, integrated circuits, substrates, and methods to convert direct current (“DC”) voltage signals to alternating current (“AC”) voltage signals. In some embodiments, an inverter can include a modulator configured to convert a direct current signal into a first variable signal, and a transformation module configured to step up the first variable signal to form a second variable signal. The transformation module can be configured to generate a first portion of the second variable signal and a second portion of the second variable signal. Further, the inverter can include a waveform generator configured to synchronize the first portion and the second portion of the second variable signal at a frequency to generate an alternating current (“AC”) signal. | 12-09-2010 |
Fu-Te Yuan, Taipei TW
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20110061770 | METHOD FOR ORDERING A DISORDERED ALLOY AND METHOD FOR MAKING A PERPENDICULAR MAGNETIC RECORDING MEDIUM - A method for ordering a disordered alloy includes: simultaneously ion bombarding and annealing a disordered alloy to transform the disordered alloy from a disordered crystalline state to an ordered crystalline state. A method for making a perpendicular magnetic recording medium which includes an ordered alloy layer is also disclosed. | 03-17-2011 |
20120237392 | MAGNETIC MATERIAL - A magnetic material includes a main alloy having a rhombohedral crystal structure and a composition represented by Co | 09-20-2012 |
Hsiang-Yu Yuan, Taipei TW
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20110236885 | Genetic Variants Predicting Warfarin Sensitivity - We discovered that a polymorphism in the promoter of the VKORC1 gene is associated with warfarin sensitivity. This polymorphism can explain both the inter-individual and inter-ethnic differences in warfarin dose requirements. Furthermore, the polymorphism is also associated with promoter activity. Thus, the promoter sequence or activity of the VKORC1 gene of a subject can be used to predict how much warfarin should be prescribed for the subject. Relevant methods and compositions are provided. | 09-29-2011 |
Hsiao-Wei Yuan, Taipei TW
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20150036012 | AUTOMATIC IMAGE-CAPTURING SYSTEM - An automatic image-capturing system is used for capturing an image and transmitting the image to a remote device. The automatic image-capturing system includes a photography module for capturing the image; a storage module for storing the image captured by the photography module; a transmission module for receiving a control instruction sent by the remote device; a master core module for making the photography module to capture the image based on the control instruction, and segmenting the image into a plurality of files and segmenting the files into a plurality of packets to be transmitted to the remote device by the transmission module, and a slave core module for monitoring the operations of the master core module to turn off and restart the master core module when there is an abnormal operation in the master core module. | 02-05-2015 |
Julian Yuan, Taipei TW
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20090209029 | HIGH-DENSITY ION TRANSPORT MEASUREMENT BIOCHIP DEVICES AND METHODS - The present invention includes biochips for the measurement of cellular ion channels and methods of use and manufacture. The biochips of the present invention have enhanced sealing capabilities provided in part by chemically modifying the surface of the biochip surface or substrate or by exposure to an ionized gas. The present invention also includes novel cartridges for biochips. | 08-20-2009 |
Kuo Yuan Yuan, Taipei TW
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20140052397 | INRUSH CURRENT MEASURING DEVICE - An inrush current measuring device is disclosed in the present invention. The device includes a current sensing unit, an analog-to-digital converter, a filter, a microcontroller, and a display unit. The inrush current measuring device of the present invention can determine an inrush current by use of at least five sampling current values and does not need to depend on an observation starting point for detecting current value of the inrush current or a continuous detecting time period to obtain accurate measurement of inrush current. | 02-20-2014 |
Min-Shuch Yuan, Taipei TW
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20100141346 | Phase-Locked Loop with Start-Up Circuit - A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal. | 06-10-2010 |
Min-Shueh Yuan, Taipei TW
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20090295439 | Phase Lock Loop (PLL) with Gain Control - A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. | 12-03-2009 |
20100176777 | Constant Gm Circuit and Methods - Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking a reference current at its output. By providing a feedback loop that controls the voltage controlled resistor, a temperature compensated circuit may be obtained. The temperature dependence of the voltage controlled resistor is positive and the feedback circuitry maintains this resistor at a value that compensates for the negative temperature dependence of the current mirror circuit. The reference current is thus obtained at a predetermined level independent of temperature. A method for providing a reference current is disclosed wherein a voltage dependent resistor is provided supply current to a current mirror, the voltage dependent resistor receiving a feedback voltage from the current mirror and the feedback controlling the resistor so that a temperature independent reference current is obtained. | 07-15-2010 |
20100253303 | VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO - A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed. | 10-07-2010 |
20110080220 | TEMPERATURE COMPENSATED INTEGRATOR - A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures. | 04-07-2011 |
20120262209 | Multi-Phase Clock Generator and Data Transmission Lines - An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals. | 10-18-2012 |
20130038366 | BIST CIRCUIT FOR PHASE MEASUREMENT - A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal. | 02-14-2013 |
20130063181 | METHOD AND APPARATUS FOR SIGNAL PHASE CALIBRATION - A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison. | 03-14-2013 |
20130127433 | METHOD OF OPERATING VOLTAGE REGULATOR - A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating. | 05-23-2013 |
20130187686 | FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD - In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes. | 07-25-2013 |
20130207694 | HIGH SPEED COMMUNICATION INTERFACE WITH AN ADAPTIVE SWING DRIVER TO REDUCE POWER CONSUMPTION - A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator. | 08-15-2013 |
20130342252 | Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation - The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values. | 12-26-2013 |
20140184343 | PHASE LOCK LOOP, VOLTAGE CONTROLLED OSCILLATOR OF THE PHASE LOCK LOOP, AND METHOD OF OPERATING THE VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal. | 07-03-2014 |
20140266114 | METHOD OF OPERATING VOLTAGE REGULATOR - A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit. | 09-18-2014 |
20140282331 | UNIVERSAL DESIGN LAYOUT COMPLIANCE - Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of design rules having design rule constraint values corresponding to a restriction threshold, such as a most restrictive value. The common dummy insertion utility is used to insert dummy polygons into a design layout according to a dummy size constraint and a dummy spacing constraint. The design layout is verified as compliant with the common DRC rule set. Once verified, the design layout can be converted from a universal design layout format to a target metal scheme to create a transformed design layout. In this way, design layouts, formatted according to the universal design layout, can be transformed to other formats. | 09-18-2014 |
20150130522 | PHASE LOCK LOOP, VOLTAGE CONTROLLED OSCILLATOR OF THE PHASE LOCK LOOP, AND METHOD OF OPERATING THE VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control signals. The VCO further includes a voltage-to-current converter comprising a plurality of current sources which are configured to generate a current signal in response to the plurality of compensation control signals. Additionally, the VCO includes a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals. Furthermore, the VCO includes a current controlled oscillator configured to generate an oscillating signal in response to the current signal. | 05-14-2015 |
Sharlene Yuan, Taipei TW
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20130304798 | PREDICTING AND RETRIEVING DATA FOR PRELOADING ON CLIENT DEVICE - Retrieval and local storage of data at mobile devices is managed by employing a scheduling policy based on a prediction policy of a preloader, a pre-render policy, and with respect to a current viewport state to reduce waiting time and mobile device resource usage. Portions of data maintained on a server associated with a client device are retrieved and preloaded into the client device memory to enable a user to view documents seamlessly while navigating through a document without overburdening the client device memory and/or processing capacity based on a prediction. A current viewing position of the document and user navigation on the document via a touch action or gesture are detected and next portion of data to present another portion of the document is predicted. A request manager may retrieve the requested data from the server and pre-rendered so that it is available when requested by the user. | 11-14-2013 |
20130339830 | OPTIMIZED DOCUMENT VIEWS FOR MOBILE DEVICE INTERFACES - Portions of document contents are separated into individually controlled sections on a user interface of a smaller size client device display. A document viewed on a mobile device may include different content portions such as textual content, tables, slides and graphics. Due to a smaller user interface of the mobile device, some portions of the content may extend outside of the user interface and may not all be visible at the same time. The user may use gestures to scroll through and resize the document to view all of the contents. The system may separate each of the different content portions into individual sections and enable the user to control each section separately, such that the user may navigate, resize, and reposition each individual section without affecting the size and position of the remaining sections of the document for optimally viewing the document on the user interface. | 12-19-2013 |
Sheng-Chun Yuan, Taipei TW
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20080320418 | Graphical User Friendly Interface Keypad System For CAD - The present invention offers an improved GUI interface for CAD software to allow users easy access to menus. A user can execute commands and options with little disruption and with minimal hand movement. The keypad is represented on the computer screen and is called a GUFI (Graphical User Friendly Interface) keypad system. The keypad is a menu having a matrix of graphical buttons. A user selects a computer resource with a spatial input device and clicks the proper context button, the GUFI keypad displays only the functions or commands that pertain to the computer resource selected. The unique GUFI keypad system displays functions and commands in an arrayed, not in a pop-up or pull down menu, but in a pattern relating to the keys on the keyboard. Menu items are accessed through a one to one correspondence with the represented keys mapped to similar physically represented keys. | 12-25-2008 |
20110022976 | DYNAMIC USER INTERFACE SYSTEM - A user interface system for operating software on a computer includes a pointing device operable by a user's primary dexterous hand, a keyboard operable by the user's secondary dexterous hand, a matrix of keyboard keys on the keyboard. The matrix may include a first set of functions that are selected from a plurality of functions, and can be programmed to the matrix and displayed on the computer screen as a context menu. The selection of the functions being programmed to the matrix is dynamically linked to a previously executed function. | 01-27-2011 |
Ta Tung Yuan, Taipei TW
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20110097302 | IL-1RA-POLYMER CONJUGATES - This invention relates to protein-polymer conjugates described in the specification. Also disclosed are a method for preparing a protein-polymer conjugate and using such a conjugate in treating various immune disorders. | 04-28-2011 |
Xue Yuan, Taipei TW
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20080310527 | CORRELATION INTERVAL SYNCHRONIZATION APPARATUS AND METHOD - The present invention is directed to a correlation interval synchronization apparatus and method. Correlation is firstly performed on received data, followed by searching peaks in accordance with the output of the correlation. Subsequently, peak intervals are acquired according to the peaks, and the peak interval where the synchronization head position resides is determined. Finally, the synchronization head position is identified within the associated peak interval. | 12-18-2008 |