Patent application number | Description | Published |
20110284818 | Graphene Channel-Based Devices and Methods for Fabrication Thereof - Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. | 11-24-2011 |
20120056161 | GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode. | 03-08-2012 |
20120181505 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 07-19-2012 |
20120181506 | High-Speed Graphene Transistor and Method of Fabrication by Patternable Hard Mask Materials - Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer. | 07-19-2012 |
20120329260 | GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance. | 12-27-2012 |
20130009133 | A GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing. | 01-10-2013 |
20130099204 | CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES - Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance. | 04-25-2013 |
20130119548 | METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY - Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided. | 05-16-2013 |
20130207080 | BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES - A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. | 08-15-2013 |
20130234762 | CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT - A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance. | 09-12-2013 |
20130280427 | Tube Reactor for Chemical Vapor Deposition - An apparatus for performing film deposition, comprises an energy source, a plurality of process tubes, and a gas manifold. The energy source is adapted to direct energy into a cylindrical space. The plurality of process tubes, in turn, pass through this cylindrical space. To perform the film deposition, the gas manifold is operative to introduce a respective gas flow into each of the plurality of process tubes. | 10-24-2013 |
20130299782 | GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES - Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface. | 11-14-2013 |
20130302963 | GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES - Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel. | 11-14-2013 |
20130309402 | INTERDIGITATED SUBSTRATE SUPPORT ASSEMBLY FOR SYNTHESIS OF LARGE AREA THIN FILMS - The invention provides methods and apparatus for supporting a substrate in a chemical vapor deposition reactor, and methods and apparatus for synthesizing large area thin films. The invention provides a substrate support assembly comprising at least two interdigitable substrate support fixtures, each fixture carrying at least one finger-like formation for engaging and positioning the substrate during the deposition process that creates the thin film. When two such fixtures are interdigitated, the substrate may be positioned not only in between and around the finger-like substrate engagement members, but also on the outside of each fixture, thus achieving a many-fold increase in the effective width of the substrate. | 11-21-2013 |
20130320303 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 12-05-2013 |
20140001440 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES | 01-02-2014 |
20140022025 | HIGH FREQUENCY OSCILLATOR CIRCUIT AND METHOD TO OPERATE SAME - A method includes providing an oscillator having a field effect transistor connected with a resonant circuit. The field effect transistor has a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The method further includes biasing the graphene channel via the gate electrode into a negative differential resistance region of operation to cause the oscillator to generate a frequency signal having a resonant frequency f0. There can be an additional step of varying the gate voltage so as to bias the graphene channel into the negative differential resistance region of operation and out of the negative differential resistance region of operation so as to turn on the frequency signal and to turn off the frequency signal, respectively. | 01-23-2014 |
20140022700 | Graphene Composite Electrodes for Energy Storage Devices - Aspects of the invention are directed to a method for forming a graphene composite structure. Initially, an encapsulating film is formed on a substrate. The encapsulating film comprises graphene. Subsequently, a plurality of particles are deposited on the encapsulating film, and then a temporary layer is deposited on the plurality of active particles and the encapsulating film. The substrate is then removed. Lastly, the temporary layer is also removed so as to cause the plurality of particles to form a cluster that is at least partially encapsulated by the encapsulating film. | 01-23-2014 |
20140030636 | CORROSION RESISTANT CURRENT COLLECTOR UTILIZING GRAPHENE FILM PROTECTIVE LAYER - In general, in one aspect, a graphene film is used as a protective layer for current collectors in electrochemical energy conversion and storage devices. The graphene film inhibits passivation or corrosion of the underlying metals of the current collectors without adding additional weight or volume to the devices. The graphene film is highly conductive so the coated current collectors maintain conductivity as high as that of underlying metals. The protective nature of the graphene film enables less corrosion resistant, less costly and/or lighter weight metals to be utilized as current collectors. The graphene film may be formed directly on Cu or Ni current collectors using chemical vapor deposition (CVD) or may be transferred to other types of current collectors after formation. The graphene film coated current collectors may be utilized in batteries, super capacitors, dye-sensitized solar cells, and fuel and electrolytic cells. | 01-30-2014 |
20140045058 | Graphene Hybrid Layer Electrodes for Energy Storage - An article of manufacture comprises an electrically conductive plate and one or more hybrid layers stacked on the electrically conductive plate. Each of the one or more hybrid layers comprises a respective sheet comprising graphene. Each of the one or more hybrid layers also comprises a respective plurality of particles disposed on the respective sheet. Finally, each of the one or more hybrid layers comprises a respective ion conducting film disposed on the respective plurality of particles and the respective sheet. | 02-13-2014 |
20140057113 | Graphene Structures with Enhanced Stability and Composite Materials Formed Therefrom - Aspects of the invention are directed to a method of forming graphene structures. Initially, a cluster of particles is received. The cluster of particles comprises a plurality of particles with each particle in the plurality of particles contacting one or more other particles in the plurality of particles. Subsequently, one or more layers are deposited on the cluster of particles with the one or more layers comprising graphene. The plurality of particles are then etched away without substantially etching the deposited one or more layers. Lastly, the remaining one or more layers are dried. The resultant graphene structures are particularly resistant to the negative effects of aggregation and compaction. | 02-27-2014 |
20140060726 | METHODS FOR TRANSFERRING GRAPHENE FILMS AND THE LIKE BETWEEN SUBSTRATES - Aspects of the invention are directed to a method of forming a thin film adhered to a target substrate. The method comprises the steps of: (i) forming the thin film on a deposition substrate; (ii) depositing a support layer on the thin film; (iii) removing the deposition substrate without substantially removing the thin film and the support layer; (iv) drying the thin film and the support layer while the thin film is only adhered to the support layer; (v) placing the dried thin film and the dried support layer on the target substrate such that the thin film adheres to the target substrate; and (vi) removing the support layer without substantially removing the thin film and the target substrate. | 03-06-2014 |
20140070107 | ULTRA-SENSITIVE RADIATION DOSIMETERS - An apparatus comprises a conducting substrate layer, a dielectric layer formed over the conducting substrate layer, a channel formed over at least a portion of the dielectric layer and first and second source/drain regions formed on respective first and second portions of the channel. The channel comprises a thin-film carbon material. The conducting substrate layer, the dielectric layer, the channel and the first and second source/drain regions are configured such that exposure to radiation causes a change in a threshold voltage of the apparatus. | 03-13-2014 |
20140113416 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES - A method for fabricating a carbon-based semiconductor device. A substrate is provided and source/drain contacts are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts. | 04-24-2014 |
20140190979 | CONTAINER FOR THE TRANSPORT AND TRANSFER OF NANOMATERIALS - Aspects of the invention are directed to a container comprising a tub, a basket, and a lid. The tub is adapted to hold a liquid and comprises a bottom and a tub sidewall having an upper rim defining an opening in the tub. The basket is disposed on the bottom of the tub and comprises a base and a basket sidewall. The base defines a perimeter, and the basket sidewall runs along at least a portion of this perimeter. The lid contacts the upper rim and comprises a filler piece. The filler piece occupies a volume inside the tub between the base and a plane defined by the upper rim. The container is adapted to hold a sensitive film stack without damage or degradation to the film stack. The container is further adapted to facilitate the easy transfer of the film stack to a new substrate. | 07-10-2014 |
20140205902 | Graphene Hybrid Structures for Energy Storage Applications - Aspects of the invention are directed to a method for forming a hybrid structure. Initially, a wire is received and an encapsulating film is deposited on the wire. Subsequently, the wire is selectively removed to leave a hollow tube formed of the encapsulating film. A plurality of active particles are then placed into the hollow tube by immersing the hollow tube in a suspension comprising the plurality of active particles and a liquid. Lastly, the hollow tube and the plurality of active particles therein are removed from the suspension and allowed to dry so as to form a cluster of active particles at least partially encapsulated by the encapsulating film. | 07-24-2014 |
20140291606 | SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES - A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween. | 10-02-2014 |
20150048312 | SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES - A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween. | 02-19-2015 |