Patent application number | Description | Published |
20150214334 | Semiconductor Device and Fabrication Method Thereof - A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance. | 07-30-2015 |
20150243659 | STRUCTURES AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES USING FIN STRUCTURES - A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process. | 08-27-2015 |
20150357472 | QUANTUM WELL FIN-LIKE FIELD EFFECT TRANSISTOR (QWFINFET) HAVING A TWO-SECTION COMBO QW STRUCTURE - The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure. | 12-10-2015 |
20160049301 | Method of Tuning Work Function for A Semiconductor Device - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes forming pre-tuned-work-function (preTWF) layer over a substrate, applying an angular-doping process to the preTWF layer to change a work function of the preTWF layer (referred to as a tuned work function (TWF) layer). The angular-doping process includes injecting a doping species beam to the preTWF layer with a distribution of injecting angle and forming a metal fill layer over the TWF layer. | 02-18-2016 |
20160049516 | Structure of S/D Contact and Method of Making Same - A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers. | 02-18-2016 |
20160079383 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer. | 03-17-2016 |
20160099328 | METHOD OF FORMING NANOWIRES - According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire. | 04-07-2016 |