Patent application number | Description | Published |
20120081860 | PRE-TREATMENT OF MEMORY CARDS FOR INK JET PRINTING - A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface. | 04-05-2012 |
20120146247 | PRE-TREATMENT OF MEMORY CARDS FOR BINDING GLUE AND OTHER CURABLE FLUIDS - A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of a curable fluid such as glue or ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface. | 06-14-2012 |
20130006564 | DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY - A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device. | 01-03-2013 |
20130015589 | CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKSAANM Liao; Chih-ChinAACI Changhua CountyAACO TWAAGP Liao; Chih-Chin Changhua County TWAANM Chiu; Chin-TienAACI Taichung CityAACO TWAAGP Chiu; Chin-Tien Taichung City TWAANM Yu; CheemanAACI FremontAAST CAAACO USAAGP Yu; Cheeman Fremont CA USAANM Upadhyayula; Suresh KumarAACI San JoseAAST CAAACO USAAGP Upadhyayula; Suresh Kumar San Jose CA USAANM Li; Wen ChengAACI Taichung CityAACO TWAAGP Li; Wen Cheng Taichung City TWAANM Lu; ZhongAACI ShanghaiAACO CNAAGP Lu; Zhong Shanghai CN - A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound. | 01-17-2013 |
20140015116 | EMI SHIELDING AND THERMAL DISSIPATION FOR SEMICONDUCTOR DEVICE - A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device. | 01-16-2014 |
20140183727 | WATERFALL WIRE BONDING - A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact. | 07-03-2014 |
20140346686 | METHODS FOR FORMING COLOR IMAGES ON MEMORY DEVICES AND MEMORY DEVICES FORMED THEREBY - A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device. | 11-27-2014 |
20150061157 | HIGH YIELD SEMICONDUCTOR DEVICE - A semiconductor device including two or more die stacks mounted to a substrate. The first die stack is mounted, at least partially encapsulated, and then tested. If the first die stack functions within predefined parameters, a second die stack is mounted on the first die stack, and then the device may undergo a second encapsulation process. Testing the first die stack before mounting the second improves yield by identifying faulty semiconductor die before all die are mounted within the semiconductor device. | 03-05-2015 |
20150115479 | SEMICONDUCTOR DIE LAMINATING DEVICE WITH INDEPENDENT DRIVES - A laminating device ( | 04-30-2015 |
20150214206 | SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CONTROLLER DIE AND METHOD OF MAKING SAME - A semiconductor device includes a substrate ( | 07-30-2015 |
20150221624 | SEMICONDUCTOR DEVICE INCLUDING INDEPENDENT FILM LAYER FOR EMBEDDING AND/OR SPACING SEMICONDUCTOR DIE - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 08-06-2015 |
Patent application number | Description | Published |
20100148855 | Constant Reference Cell Current Generator For Non-Volatile Memories - A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (I | 06-17-2010 |
20100205504 | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process - A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure. | 08-12-2010 |
20100208530 | Two Bits Per Cell Non-Volatile Memory Architecture - A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier. | 08-19-2010 |
Patent application number | Description | Published |
20080213467 | SOLUTION-BASED FABRICATION OF PHOTOVOLTAIC CELL - An ink for forming CIGS photovoltaic cell active layers is disclosed along with methods for making the ink, methods for making the active layers and a solar cell made with the active layer. The ink contains a mixture of nanoparticles of elements of groups IB, IIIA and (optionally) VIA. The particles are in a desired particle size range of between about 1 nm and about 500 nm in diameter, where a majority of the mass of the particles comprises particles ranging in size from no more than about 40% above or below an average particle size or, if the average particle size is less than about 5 nanometers, from no more than about 2 nanometers above or below the average particle size. The use of such ink avoids the need to expose the material to an H | 09-04-2008 |
20100166954 | Nanostructured Layer and Fabrication Methods - Nanostructured layers with 10 nm to 50 nm pores spaced 10-50 nm apart, a method for making such nanostructured layers, optoelectronic devices having such nanostructured layers and uses for such nanostructured layers are disclosed. The nanostructured layer can be formed using precursor sol, which generally includes one or more covalent metal complexes, one or more surfactants, a solvent, one or more optional condensation inhibitors, and (optionally) water. Evaporating the solvent from the precursor sol forms a surfactant-templated film. Covalently crosslinking the surfactant-templated film forms a nanostructured porous layer. Pore size is controlled, e.g., by appropriate solvent concentration, choice of surfactant, use of chelating agents, use of swelling agents or combinations of these. | 07-01-2010 |
20100267189 | SOLUTION-BASED FABRICATION OF PHOTOVOLTAIC CELL - An ink for forming CIGS photovoltaic cell active layers is disclosed along with methods for making the ink, methods for making the active layers and a solar cell made with the active layer. The ink contains a mixture of nanoparticles of elements of groups IB, IIIA and (optionally) VIA. The particles are in a desired particle size range of between about 1 nm and about 500 nm in diameter, where a majority of the mass of the particles comprises particles ranging in size from no more than about 40% above or below an average particle size or, if the average particle size is less than about 5 nanometers, from no more than about 2 nanometers above or below the average particle size. The use of such ink avoids the need to expose the material to an H | 10-21-2010 |
20120307467 | Oxygen-Barrier Packaged Surface Mount Device - An electrical component includes a plurality of core devices arranged within a housing so as to be electrically isolated from one another. For each of the plurality of core devices, a first contact pad and a second contact pad is formed on an outside surface of the housing. The first and second contact pads are electrically connected to a respective core device of the plurality of core devices. | 12-06-2012 |
20130059410 | Solution-Based Fabrication of Photovoltaic Cell - An ink for forming CIGS photovoltaic cell active layers is disclosed along with methods for making the ink, methods for making the active layers and a solar cell made with the active layer. The ink contains a mixture of nanoparticles of elements of groups IB, IIIA and (optionally) VIA. The particles are in a desired particle size range of between about 1 nm and about 500 nm in diameter, where a majority of the mass of the particles comprises particles ranging in size from no more than about 40% above or below an average particle size or, if the average particle size is less than about 5 nanometers, from no more than about 2 nanometers above or below the average particle size. The use of such ink avoids the need to expose the material to an H | 03-07-2013 |
Patent application number | Description | Published |
20090103364 | SERIAL INTERFACE NAND - Embodiments are provided that include operating a NAND memory device via an SPI interface. One such method includes cache loading a NAND memory device including loading data into a cache of the NAND memory device, writing data from the cache of the NAND memory device to an address of a memory array of the NAND memory device, and polling to determine the status of the data being written. Further one such method includes caching of data in a NAND memory device via an SPI interface comprising loading first data to a cache of the NAND memory device, writing the first data to a first address of a NAND memory array of the NAND memory device, polling the status of the cache, if polling indicates that the cache is ready, then loading a portion of the cache with second data, polling the status of the cache and the NAND memory device, and if polling indicates that the cache is ready and the device is ready, writing the second data to a second address of the NAND memory array of the NAND memory device. | 04-23-2009 |
20090274000 | SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP - Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory. | 11-05-2009 |
20130238846 | SERIAL INTERFACE NAND - Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host. | 09-12-2013 |
Patent application number | Description | Published |
20140084984 | LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL FROM OUTPUT POWER DOMAIN AND A METHOD OF CONVERTING A DATA SIGNAL BETWEEN POWER DOMAINS - Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source. | 03-27-2014 |
20140125377 | DUAL FLIP-FLOP CIRCUIT - A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions. | 05-08-2014 |
20140129887 | FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN INPUT - A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal. | 05-08-2014 |
20140167828 | SMALL AREA LOW POWER DATA RETENTION FLOP - Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch. | 06-19-2014 |
20140169108 | MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES - Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal. | 06-19-2014 |
Patent application number | Description | Published |
20120027252 | HAND GESTURE DETECTION - A method for detecting presence of a hand gesture in video frames includes receiving video frames having an original resolution, downscaling the received video frames into video frames having a lower resolution, and detecting a motion corresponding to the predefined hand gesture in the downscaled video frames based on temporal motion information in the downscaled video frames. The method also includes detecting a hand shape corresponding to the predefined hand gesture in a candidate search window within one of the downscaled video frames using a binary classifier. The candidate search window corresponds to a motion region containing the detected motion. The method further includes determining whether the received video frames contain the predefined hand gesture based on the hand shape detection. | 02-02-2012 |
20120027263 | HAND GESTURE DETECTION - A method for detecting presence of a hand gesture in video frames includes receiving video frames having an original resolution, downscaling the received video frames into video frames having a lower resolution, and detecting a motion corresponding to the predefined hand gesture in the downscaled video frames based on temporal motion information in the downscaled video frames. The method also includes detecting a hand shape corresponding to the predefined hand gesture in a candidate search window within one of the downscaled video frames using a binary classifier. The candidate search window corresponds to a motion region containing the detected motion. The method further includes determining whether the received video frames contain the predefined hand gesture based on the hand shape detection. | 02-02-2012 |
20120068917 | SYSTEM AND METHOD FOR DYNAMIC GESTURE RECOGNITION USING GEOMETRIC CLASSIFICATION - A gesture recognition system and method that inputs videos of a moving hand and outputs the recognized gesture states for the input sequence. In each image, the hand area is segmented from the background and used to estimate parameters of all five fingers. The system further classifies the hand image as one of the postures in the pre-defined database and applies a geometric classification algorithm to recognize the gesture. The system combines a skin color model with motion information to achieve real-time hand segmentation performance, and considers each dynamic gesture as a multi-dimensional volume and uses a geometric algorithm to classify each volume. | 03-22-2012 |
20120069168 | GESTURE RECOGNITION SYSTEM FOR TV CONTROL - A gesture recognition system using a skin-color based method combined with motion information to achieve real-time segmentation. A Kalman filter is used to track the centroid of the hand. The palm center, palm bottom, as well as the largest distance from the palm center to the contour from extracted hand mask are computed. The computed distance to a threshold is then compared to decide if the current posture is “open” or “closed.” In a preferred embodiment, the transition between the “open” and “closed” posture to decide if the current gesture is in “select” or “grab” state. | 03-22-2012 |
20120081572 | APPARATUS FOR AUTOMATIC ESTIMATE OF THE ANGLE IN TILTED IMAGES FOR LEVEL CORRECTION - A method of and an apparatus for automatically estimating the tilting angle in tilted images enables level correction of the images. A preferred orientation of objects in an image and the deviation of the current orientation from the preferred orientation is determined by tilt image analysis without object recognition. Tilt image analysis includes several steps such as gradient feature computation, line segment tracking, line segment estimation and orientation deviation estimation. Once the tilt angle is determined, the image can be corrected so that an object or scene is not tilted or is tilted by only the appropriate amount. | 04-05-2012 |
20120141015 | VANISHING POINT ESTIMATION SYSTEM AND METHODS - System and methods for estimating a vanishing point within an image, including comprising: programming executable on a processor for computing line segment estimation of one or more lines in said image, wherein one or more of the lines comprise multiple line segments as a single least-mean-square-error (LMSE) fitted lines. Additionally the one or more lines having multiple line segments are represented as a single least-mean-square-error (LMSE) fitted line, and the one or more lines are intersected to locate a vanishing point in a density space. | 06-07-2012 |
20120219221 | System and method for effectively performing a scene rectification procedure - A system and method for effectively performing a scene rectification procedure comprises an image manager that includes a segmentation module, a label module, and a rectification module. The segmentation module initially performs a segmentation procedure upon an image to produce corresponding sub-scenes. The label module then categorizes the sub-scenes by assigning initial labels without utilizing context information from other sub-scenes in the image. The rectification module performs a semantic grouping procedure upon the sub-scenes to produce semantic group nodes corresponding to pairs of the sub-scenes that have a predefined semantic relationship. The rectification module converts a sub-scene graph of the sub-scenes into a semantic graph that includes the semantic group nodes. The rectification module then performs a rectification procedure to convert the initial labels of the sub-scenes into rectified labels. A processor of an electronic device typically controls the image manager for performing the scene rectification procedure. | 08-30-2012 |
20120250987 | System and method for effectively performing an image identification procedure - A system and method for effectively performing an image identification procedure includes an image matching manager that derives source characteristics for a source image and target characteristics for target images. The image matching manager compares the source characteristics and the target characteristics to determine whether the source image matches any of the target images. The source characteristics and the target characteristics may include color-space characteristics and curve-space characteristics from the respective images. A processor of an electronic device typically controls the image matching manager to effectively perform the image identification procedure. | 10-04-2012 |
20120251000 | System and method for effectively performing an integrated segmentation procedure - A system and method for effectively performing an integrated segmentation procedure comprises an image segmenter that includes a texture modeler, a contrast modeler, and a model integrator. The texture modeler creates a texture model based upon an original image. Similarly, the contrast modeler creates a contrast model based upon the original image. The model integrator then performs a model integration procedure to create a final segmented image by integrating the texture model and the contrast model according to a calculated texture model metric. A processor of an electronic device typically controls the image segmenter to perform the integrated segmentation procedure. | 10-04-2012 |
20130216134 | System And Method For Effectively Performing A Scene Representation Procedure - A system for performing a scene representation procedure includes an image manager that processes source images from a given scene to define subscenes in the source images. The image manager creates an image understanding graph for each of the source images, and also creates a scene representation graph for each of the source images based upon the corresponding subscenes and certain image characteristics. The image manager further generates an integrated scene representation to represent all of the source images with a single representation. A processor of an electronic device controls the image manager to perform the scene representation procedure. | 08-22-2013 |
20130216138 | System And Method For Effectively Performing An Image Categorization Procedure - A system for performing an image categorization procedure includes an image manager with a keypoint generator, a support region filter, an orientation filter, and a matching module. The keypoint generator computes initial descriptors for keypoints in a test image. The support region filter and the orientation filter perform respective filtering procedures upon the initial descriptors to produce filtered descriptors. The matching module compares the filtered descriptors to one or more database image sets for categorizing said test image. A processor of an electronic device typically controls the image manager to effectively perform the image categorization procedure. | 08-22-2013 |
20130230220 | AUTOMATIC IMAGE ALIGNMENT - A method for automatically aligning images includes (a) determining initial correspondent point features between a first image and a second image, (b) creating a triangular meshes for the images from the initial correspondent point features within the images, and (c) refining point correspondence between the first and second images based on affine transformation estimation using the triangular meshes. The method may also include (d) creating refined triangular meshes for the images from the point correspondence refined in (c), and (e) determining coordinate alignment within the areas of pairs of correspondent triangles in the refined triangular meshes through interpolation of affine transformation on the pairs of correspondent triangles. | 09-05-2013 |
20130243302 | AUTOMATED SYNCHRONIZED NAVIGATION SYSTEM FOR DIGITAL PATHOLOGY IMAGING - A method for synchronizing navigation in pathology stain images includes (a) downscaling the pathology stain images, (b) estimating rotation of the downscaled images, (c) aligning the downscaled images to generate aligned coordinates, and (d) transforming the aligned coordinates to original image coordinates in the pathology stain images to thereby generate alignment data. Also provided is a system for synchronized navigation in pathology stain images having original resolutions comprising a downscaler, a rotation estimator, an alignment module, and a coordinate transformer. The system may also include an image display system to display corresponding areas of the pathology stain images. | 09-19-2013 |
20140126785 | METHOD AND APPARATUS FOR TISSUE REGION IDENTIFICATION - Certain aspects of an apparatus and method for method and apparatus for tissue region identification may include segmenting the image into a plurality of regions, filtering out regions in the plurality of regions which are curvilinear, and isolating a target area where the tissue sample is identified as the plurality of regions not filtered. | 05-08-2014 |
20140126786 | METHOD AND APPARATUS FOR ORIENTING TISSUE SAMPLES FOR COMPARISON - Certain aspects of an apparatus and method for orienting tissue samples for comparison may include incrementally rotating orientation of a first image by a predetermined rotation angle while maintaining orientation of a second image at a fixed angle, checking alignment of the orientation of the first image with the orientation of the second image at each predetermined rotation angle by matching a plurality of points in the first image and the second image, determining whether a predetermined rotation angle is a correct rotation angle for alignment based on a count of the plurality of points being greater than a threshold value and rotating to the next predetermined rotation angle when the count of the plurality of points is less than or equal to a threshold value. | 05-08-2014 |
20160027178 | IMAGE REGISTRATION SYSTEM WITH NON-RIGID REGISTRATION AND METHOD OF OPERATION THEREOF - An image registration system, and a method of operation of an image registration system thereof, including: an imaging unit for obtaining a pre-operation non-invasive imaging volume and for obtaining an intra-operation non-invasive imaging volume; and a processing unit including: a rigid registration module for generating a rigid registered volume based on the pre-operation non-invasive imaging volume, a region of interest module for isolating a region of interest from the intra-operation non-invasive imaging volume, a point generation module, coupled to the region of interest module, for determining feature points of the region of interest, an optimization module, coupled to the point generation module, for matching the feature points with corresponding points of the rigid registered volume for generating a matched point cloud, and an interpolation module, coupled to the optimization module, for generating a non-rigid registered volume based on the matched point cloud for display on a display interface. | 01-28-2016 |
Patent application number | Description | Published |
20110033041 | INDEX-BASED CODING WITH A PSEUDO-RANDOM SOURCE - Outputs from at least one pseudo-random source are used to encode hidden value. The hidden value is encoded using index based quantities, for example, based on numerically ordering a sequence of outputs from pseudo-random source(s). In some examples, the numerical ordering of re-generated device-specific quantities is used to re-generate the hidden value, without necessarily requiring additional error correction mechanisms. Information leak may be reduced by constructing system whose “syndrome” helper bits are random, as measured, for example, by NIST's Statistical Tests for Randomness In some examples, index based coding provides coding gain that exponentially reduces total error correction code complexity, resulting in efficiently realizable PRS-based key generation systems. In some examples, index based coding allows noisy PRS to be robust across conditions where conventional error correction code cannot error correct. | 02-10-2011 |
20110066670 | COMBINATION OF VALUES FROM A PSEUDO-RANDOM SOURCE - Values generated by at least one pseudo-random source (PRS) are recombined to form one or more recombined values. The method involves using analog, digital, or hybrid manipulation techniques to transform characteristics of PRS, including but not limited to statistical characteristics, and input/output characteristics. In some examples, the recombination method provides a way to de-bias output bits from PRS without appreciable increase in self noise. In some examples, the recombined result passes NIST's Statistical Tests for Randomness even if underlying PRS natively does not. In some examples, the recombination method provides a way to make a PRS challengeable, even if the underlying PRS is not natively challengeable. In some examples, recombination is used to allow single PRS to have multiple outputs, and in some cases multi-dimensional (orthogonal) outputs. In some examples, a multi-modal system is created via recombination using multiple PRS. In some examples, post recombined result exhibit super error characteristics (prior to application of any error correction codes) compared to native PRS output. In some examples, the recombined values are applied to security applications, for instance authentication and/or cryptographic functions, which may provide improved characteristics (e.g., cryptographic strength) in view of a de-biased output which in some examples also passes NIST's Statistical Tests. | 03-17-2011 |
20130010957 | CRYPTOGRAPHIC SECURITY USING FUZZY CREDENTIALS FOR DEVICE AND SERVER COMMUNICATIONS - An approach to cryptographic security uses a “fuzzy” credential, in contrast to a “hard” credential, to eliminate cryptographic algorithmic repeatability on a device that may be subject to physical attacks. By eliminating repeatability performed at an algorithmic (e.g., gate or software) level, a device inherently lacks one of the fundamental setup assumptions associated with certain classes of side channel, fault injection, timing, and related attacks, thus helps to protect the system against such attacks while preserving the cryptographic security of the system. | 01-10-2013 |
Patent application number | Description | Published |
20130298211 | AUTHENTICATION TOKEN - The disclosed invention is a system and method that allows for authentication of a user to a network using a token. The token interacts with a device and authenticates the user to the system. The token may be part of the device or stand alone. The various aspects of the present invention capture a novel design for an authentication token that eliminates the need for user interaction with the token. | 11-07-2013 |
20140214354 | SYSTEM AND METHOD OF DETECTION AND ANALYSIS FOR SEMICONDUCTOR CONDITION PREDICTION - The invention described here enables in-operation, low-cost, non-invasive measurement of component performance and condition for assessing device longevity prediction, resilience and reliability. The non-invasive component measurements to be performed and subsequently evaluated are based on at least a set of physically unclonable functions and other measurements which can be error corrected, and the error correction factor and other measurements provides insight to the device condition. The system as well is adaptive and allows the introduction of new measurements across not only similar components but to include the family of components similarly fabricated. | 07-31-2014 |
20140331288 | ACCESS GATING OF NOISY PHYSICAL FUNCTIONS - A system and methods are disclosed that limiting the number of challenge/response pairs available to an adversary. In accordance with the various aspects of the present invention, gate the access to an authentication module with a gatekeeper. The system can create a challenge/response protocol whereby the amount of challenge/response information leaked is controlled by the server. The device cannot leak challenge/response pairs when the device is in the possession of or being queried by an adversary or false device. | 11-06-2014 |
20150026545 | SYSTEM AND METHOD FOR GENERATING CONSTELLATION-BASED INFORMATION CODING USING PHYSICAL NOISY PSEUDO-RANDOM SOURCES - A method and system are provided for a symbol-oriented approach that addresses information recovery from manufacturing variations (MVs) readings in a high noise environment. The multi-bits-per-symbol approach, which is in accordance with the various aspects of the present invention, is in contrast with how manufacturing-variation-derived bits are normally treated in the context of PUF Key Generation's error correction process. The multi-bit-per-symbol approach also offers a natural distance metric (distance to the most-likely symbol, distance to the next-most-likely symbol, etc.) which can aid soft-decision decoding or list-decoding, and can be used to improve the provisioning of a more reliably encoded secret and its associated helper data value. | 01-22-2015 |
20150074157 | RANDOM NUMBER GENERATOR USING AN INCREMENTING FUNCTION - A random number generator uses a looped circuit that produces pulses dependent on manufacturing variations and noise, and fed into a counting circuit. In certain embodiments, the technology can be merged with a Physical Unclonable Function (PUF) such that a single circuit provides both 1) bits that are unique to each chip that remain fairly similar each time they are queried on the same chip; as well as 2) bits that are random, i.e., different each time the randomness is queried, even on the same device. | 03-12-2015 |
Patent application number | Description | Published |
20090278173 | MEMORY DEVICE INTERCONNECTS AND METHOD OF MANUFACTURING - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 11-12-2009 |
20140145337 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines. | 05-29-2014 |
20140151887 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 06-05-2014 |
20140377948 | METHOD OF DEPOSITING COPPER USING PHYSICAL VAPOR DEPOSITION - The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less. | 12-25-2014 |
20140377949 | METHOD OF DEPOSITING COPPER USING PHYSICAL VAPOR DEPOSITION - The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less. | 12-25-2014 |
Patent application number | Description | Published |
20090015721 | METHODS AND APPARATUS USING SHARED STORAGE FOR CANNEL ERROR CORRECTION AND MULTIMEDIA DECODING AND PROCESSING IN A DIGITAL TV SYSTEM - An OFDM receiver is provided that comprises a channel decoder; a source decoder; and a memory controller coupled to the channel decoder and source decoder to control the channel decoder, the source decoder and a memory separate from the apparatus such that the memory is shared by both the channel decoder and the source decoder. | 01-15-2009 |
20090016428 | METHOD AND APPARATUS FOR DECODING OF VIDEO SIGNALS HAVING REDUCED MEMORY AND A NOVEL METHOD FOR OUTPUT THEREFORE - A method and apparatus for in mobile communication systems, wherein the display image size is less than that of in the home entertainment purpose, are provided. Instead of using the high definition video decoding from incoming bit stream to the memory and the display for any size video display, the image is scaled during the decoding process to save the memory size and memory access bandwidth at a macro-block level. As the result, the power consumption involved will be substantially reduced, and the reduce display optimized. | 01-15-2009 |
20090019068 | DECODER WITH REDUCED MEMORY REQUIREMENTS DECODING OF VIDEO SIGNALS - A decoder decoding at a block level provided. The decoder comprises: a down-scalar receiving a multiplicity of blocks of data and down-scaling the blocks of data at the block level and storing the down-scaled data in a memory; and an output device for outputting the down-scaled blocks of data at the block level. | 01-15-2009 |
20090079882 | ANALOG TV SIGNAL DECODING USING DIGITAL TUNER WITH I AND Q OUTPUT - A dual use TV receiver for both analog TV and DTV using a digital tuner for processing analog signals and converting same to its respective I and Q components is provided. A method for producing a television receiver comprising the step of providing a digital tuner for processing analog signals to its respective I and Q components is provided. | 03-26-2009 |
20100027614 | ERROR AWARENESS AND MEANS FOR REMEDYING SAME IN VIDEO DECODING - A DTV receiver having method using elastic decoding method is provided. The method comprises the steps of: receiving a signal for processing; decoding the signal using a source decoder; determining a portion of the signal that are problematic; and using elastic decoding to remedy the portion of the signal that are problematic. | 02-04-2010 |
20100031130 | FORWARD ERROR CORRECTION (FEC) AND VARIABLE LENGTH CODE (VLC) JOINT DECODING - A method for decoding is provided. The method comprises the step of: using information known to a channel decoder to determine a path between two data points, whereby reducing error or bad data effects. | 02-04-2010 |
20100229073 | ENCODING AND ERROR CORRECTION SYSTEM FOR ENHANCED PERFORMANCE OF LEGACY COMMUNICATIONS NETWORKS - A system includes a header stripper configured to strip header data from a plurality of legacy system frames. Each of the plurality of legacy system frames (i) being in accordance with a legacy system frame format and (ii) including a header block and a traffic channel block. A first encoder is configured to encode speech data for a plurality of slots of the traffic channel blocks. A second encoder is configured to encode the stripped header data as a frame header. A combiner is configured to combine the frame header and the encoded speech data to generate a frame. A segmenter segments the frame into a plurality of segments. A transmitter is configured to transmit the plurality of segments as traffic channel data in accordance with the legacy system frame format. | 09-09-2010 |