Patent application number | Description | Published |
20080303065 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage. In the functional circuit of the semiconductor device and the display device, a power supply wiring and a ground wiring are formed in a comb-like arrangement, and the tips thereof are electrically connected with a first wiring, a second wiring, and a contact between the first wiring and the second wiring, thereby forming in a grid-like arrangement. The drop in power supply voltage and the rise in ground voltage can be decreased and the arrangement area can be decreased in the grid-like arrangement. | 12-11-2008 |
20090004846 | WIRING BOARD, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to the invention, first to third wirings, first and second interlayer insulating films and first and second contact holes are formed over a substrate having an insulating surface. The second wiring is wider than the first wiring, or the third wiring is wider than the first wiring or the second wiring. The second contact hole has a larger diameter than the first contact hole. | 01-01-2009 |
20090072862 | Semiconductor Device and Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 03-19-2009 |
20100327911 | Semiconductor Device and a Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 12-30-2010 |
20120032181 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage. In the functional circuit of the semiconductor device and the display device, a power supply wiring and a ground wiring are formed in a comb-like arrangement, and the tips thereof are electrically connected with a first wiring, a second wiring, and a contact between the first wiring and the second wiring, thereby forming in a grid-like arrangement. The drop in power supply voltage and the rise in ground voltage can be decreased and the arrangement area can be decreased in the grid-like arrangement. | 02-09-2012 |
20120229166 | Semiconductor Device and a Display Device - A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. | 09-13-2012 |
20120306837 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage. | 12-06-2012 |
Patent application number | Description | Published |
20090077319 | Arithmetic Processing Device and Electronic Appliance Using Arithmetic Processing Device - A CPU incorporating a cache memory is provided, in which a high processing speed and low power consumption are realized at the same time. A CPU incorporating an associative cache memory including a plurality of sets is provided, which includes a means for observing a cache memory area which does not contribute to improving processing performance of the CPU in accordance with an operating condition, and changing such a cache memory area to a resting state dynamically. By employing such a structure, a high-performance and low-power consumption CPU can be provided. | 03-19-2009 |
20090218576 | THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers. | 09-03-2009 |
20090236600 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer. | 09-24-2009 |
20090269911 | NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate ( | 10-29-2009 |
20120250407 | MEMORY CIRCUIT, MEMORY UNIT, AND SIGNAL PROCESSING CIRCUIT - A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit. | 10-04-2012 |
20120257439 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME - A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from a main memory device and/or the arithmetic unit, in accordance with an instruction from the control unit. The buffer memory device includes a plurality of memory cells. The memory cells each include a transistor including a channel formation region including an oxide semiconductor, and a memory element to which charge with an amount in accordance with a value of the data is supplied through the transistor. Further, a data retention time of the memory cell corresponding to a valid bit is shorter than a data retention time of the memory cell corresponding to a data field. | 10-11-2012 |
20150076527 | IMAGING DEVICE - Objects are to provide a small imaging device that can take an image of a thick book without distortion of an image of a gutter and to improve the portability of an imaging device by downsizing the imaging device. The imaging device has imaging planes on both surfaces. All elements included in the imaging device are preferably provided over one substrate. In other words, the imaging device has a first imaging plane and a second imaging plane facing opposite to the first imaging plane. | 03-19-2015 |
Patent application number | Description | Published |
20140211558 | SIGNAL PROCESSING CIRCUIT - It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor. | 07-31-2014 |
20140285755 | PHOTODETECTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND LIGHT-EMITTING DEVICE - One embodiment of the present invention includes a first light-blocking layer and a second light-blocking layer which are over a light-transmitting substrate, a first photodiode over the first light-blocking layer, a second photodiode over the second light-blocking layer, a first color filter covering the first photodiode, a second color filter covering the second photodiode, and a third light-blocking layer formed using the first color filter and the second color filter and disposed between the first photodiode and the second photodiode. | 09-25-2014 |
20140346632 | PHOTODETECTOR CIRCUIT - A photodetector circuit is provided that includes: a first wiring connected to an input terminal; a second wiring connected to an output terminal; and first and second photosensors each including a first terminal connected to the first wiring and a second terminal connected to the second wiring, wherein the first wiring and the second wiring are arranged in parallel, and the sum of resistance values of a first path from the input terminal to the output terminal via the first wiring, the first photosensor, and the second wiring is identical to the sum of resistance values of a second path from the input terminal to the output terminal via the first wiring, the second photosensor, and the second wiring. | 11-27-2014 |