Patent application number | Description | Published |
20080304349 | VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit. | 12-11-2008 |
20090067255 | NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES - A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage. | 03-12-2009 |
20090073764 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE CAPABLE OF HIGH-SPEED WRITING - A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation. | 03-19-2009 |
20090212852 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals. | 08-27-2009 |
20110231687 | MEMORY SYSTEM AND SERVER SYSTEM - According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode. | 09-22-2011 |
20130262901 | MEMORY SYSTEM AND SERVER SYSTEM - According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode. | 10-03-2013 |
20140140152 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal. | 05-22-2014 |
20150131397 | MEMORY SYSTEM AND ASSEMBLING METHOD OF MEMORY SYSTEM - According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information. | 05-14-2015 |