Patent application number | Description | Published |
20090154241 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 06-18-2009 |
20100067302 | NAND-TYPE FLASH MEMORY AND NAND-TYPE FLASH MEMORY CONTROLLING METHOD - A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current. | 03-18-2010 |
20100124113 | SEMICONDUCTOR MEMORY WRITE METHOD - A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage level, and a final data write operation of additionally writing final data at the threshold voltage level, includes making at least one of a write time of the preliminary data write operation, a word-line waiting time of verify read, and a bit-line waiting time of verify read, shorter than that of the final data write operation. | 05-20-2010 |
20100124128 | NAND FLASH MEMORY - A NAND flash memory in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed via a first gate insulating film on a well formed on a semiconductor substrate and a control gate which is formed on the floating gate via a second gate insulating film, and being capable of rewriting data by controlling an amount of charge accumulated on the floating gate; and a row decoder having a plurality of n-type transfer MOS transistors having drains respectively connected to word lines respectively connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate voltages and source voltages of the transfer MOS transistors. | 05-20-2010 |
20100165733 | NAND NONVOLATILE SEMICONDUCTOR MEMORY - A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation. | 07-01-2010 |
20100177563 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 07-15-2010 |
20100177570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF COMPENSATING VARIATION WITH TIME OF PROGRAM VOLTAGE - A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase. | 07-15-2010 |
20100232229 | SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a bit line, a source line, a source line driver, a sense amplifier, a counter, a detector, a controller. The sense amplifier reads the data by sensing current flowing through the bit line. The counter counts ON memory cells and/or OFF memory cells. The detector detects whether the voltage of the source line has exceeded a reference voltage. The controller controls the number of times of data sensing by the sense amplifier in accordance with the detection result in the detector, and controls a driving force of the source line driver in accordance with the count in the counter. | 09-16-2010 |
20100303485 | IMAGE FORMING APPARATUS AND IMAGE FORMING METHOD - An image forming apparatus includes a receiver to receive image information from an external device, a movable intermediate transfer member, a plurality of latent image bearing members on which a latent image is formed based on the image information, a plurality of developing devices, each of which disposed in proximity to the latent image baring member, to develop the latent image on the latent image bearing member with toner to form a toner image thereon, a transfer bias application mechanism to apply a transfer bias to the intermediate transfer member and halt temporarily and periodically application of the transfer bias in a continuous output mode in which a plurality of images are continuously formed on different recording media sheets based on the image information of the plurality of images received continuously by the receiver, and a secondary transfer member to transfer the superimposed toner image onto a recording medium. | 12-02-2010 |
20110069546 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections such that the respective sections provide writing voltages for writing different target threshold levels, and brings the bit line connected to the memory cell to be written with any of the target threshold levels into a selected state synchronously to the section for applying the writing voltage for writing that target threshold level. | 03-24-2011 |
20110157994 | NAND-TYPE FLASH MEMORY AND NAND-TYPE FLASH MEMORY CONTROLLING METHOD - A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current. | 06-30-2011 |
20110299339 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 12-08-2011 |
20120032243 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode. | 02-09-2012 |